mb/google/brya/var/agah: Add GPU power sequencing
[coreboot.git] / src / mainboard / google / brya / variants / agah / overridetree.cb
blob70bc09289d424929bdc968cf8d91e3291676b2bd
1 chip soc/intel/alderlake
2 # Intel Common SoC Config
3 #+-------------------+---------------------------+
4 #| Field | Value |
5 #+-------------------+---------------------------+
6 #| I2C0 | Audio |
7 #| I2C1 | GPU |
8 #| I2C2 | External graphic |
9 #| I2C3 | cr50 TPM. Early init is |
10 #| | required to set up a BAR |
11 #| | for TPM communication |
12 #| I2C5 | Trackpad |
13 #+-------------------+---------------------------+
14 register "common_soc_config" = "{
15 .i2c[0] = {
16 .speed = I2C_SPEED_FAST,
18 .i2c[1] = {
19 .speed = I2C_SPEED_FAST,
21 .i2c[2] = {
22 .speed = I2C_SPEED_FAST,
24 .i2c[3] = {
25 .early_init = 1,
26 .speed = I2C_SPEED_FAST,
28 .i2c[5] = {
29 .speed = I2C_SPEED_FAST,
33 register "sagv" = "SaGv_Enabled"
34 register "tcss_aux_ori" = "0x10"
35 register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
37 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
38 register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN
39 register "usb2_ports[4]" = "USB2_PORT_EMPTY" #
40 register "usb2_ports[6]" = "USB2_PORT_EMPTY" #
41 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2
43 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2
44 register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
46 register "serial_io_i2c_mode" = "{
47 [PchSerialIoIndexI2C0] = PchSerialIoPci,
48 [PchSerialIoIndexI2C1] = PchSerialIoPci,
49 [PchSerialIoIndexI2C2] = PchSerialIoPci,
50 [PchSerialIoIndexI2C3] = PchSerialIoPci,
51 [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
52 [PchSerialIoIndexI2C5] = PchSerialIoPci,
55 register "serial_io_gspi_mode" = "{
56 [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
57 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
60 device domain 0 on
61 device ref pcie4_0 on
62 # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0
63 register "cpu_pcie_rp[CPU_RP(1)]" = "{
64 .clk_req = 0,
65 .clk_src = 0,
66 .flags = PCIE_RP_LTR | PCIE_RP_AER,
68 device pci 00.0 alias dgpu on end
69 end
70 device ref dtt on
71 chip drivers/intel/dptf
72 ## sensor information
73 register "options.tsr[0].desc" = ""DRAM""
74 register "options.tsr[1].desc" = ""Soc""
75 register "options.tsr[2].desc" = ""Charger""
76 register "options.tsr[3].desc" = ""Regulator""
77 # TODO: below values are initial reference values only
78 ## Passive Policy
79 register "policies.passive" = "{
80 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
81 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
82 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
83 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
84 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
86 ## Critical Policy
87 register "policies.critical" = "{
88 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
89 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
90 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
91 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
92 [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
94 register "controls.power_limits" = "{
95 .pl1 = {
96 .min_power = 3000,
97 .max_power = 15000,
98 .time_window_min = 28 * MSECS_PER_SEC,
99 .time_window_max = 32 * MSECS_PER_SEC,
100 .granularity = 200,
102 .pl2 = {
103 .min_power = 55000,
104 .max_power = 55000,
105 .time_window_min = 28 * MSECS_PER_SEC,
106 .time_window_max = 32 * MSECS_PER_SEC,
107 .granularity = 1000,
110 ## Charger Performance Control (Control, mA)
111 register "controls.charger_perf" = "{
112 [0] = { 255, 1700 },
113 [1] = { 24, 1500 },
114 [2] = { 16, 1000 },
115 [3] = { 8, 500 }
117 device generic 0 on end
120 device ref cnvi_wifi on
121 chip drivers/wifi/generic
122 register "wake" = "GPE0_PME_B0"
123 device generic 0 on end
126 device ref i2c0 on
127 chip drivers/i2c/generic
128 register "hid" = ""RTL5682""
129 register "name" = ""RT58""
130 register "desc" = ""Headset Codec""
131 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
132 # Set the jd_src to RT5668_JD1 for jack detection
133 register "property_count" = "1"
134 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
135 register "property_list[0].name" = ""realtek,jd-src""
136 register "property_list[0].integer" = "1"
137 device i2c 1a on end
139 end #I2C0
140 device ref i2c1 on end # GPU
141 device ref i2c2 on end # External GPU
142 device ref i2c3 on
143 chip drivers/i2c/tpm
144 register "hid" = ""GOOG0005""
145 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
146 device i2c 50 on end
149 device ref i2c5 on
150 chip drivers/i2c/generic
151 register "hid" = ""ELAN0000""
152 register "desc" = ""ELAN Touchpad""
153 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
154 register "wake" = "GPE0_DW2_14"
155 register "probed" = "1"
156 device i2c 15 on end
159 device ref pcie_rp3 on
160 chip drivers/net
161 register "customized_leds" = "0x05af"
162 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)"
163 register "stop_delay_ms" = "12" # NIC needs time to quiesce
164 register "stop_off_delay_ms" = "1"
165 register "has_power_resource" = "1"
166 register "wake" = "GPE0_DW0_07"
167 device pci 00.0 on end
169 end #RTL8111H Ethernet NIC
170 device ref pcie_rp4 off end
171 device ref pcie_rp6 off end
172 device ref pcie_rp7 off end
173 device ref pcie_rp8 on
174 chip soc/intel/common/block/pcie/rtd3
175 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
176 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
177 register "srcclk_pin" = "3"
178 device generic 0 on end
180 end #PCIE8 SD card
181 device ref hda on
182 chip drivers/generic/max98357a
183 register "hid" = ""MX98360A""
184 register "sdmode_gpio" =
185 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
186 register "sdmode_delay" = "5"
187 device generic 0 on end
190 device ref pch_espi on
191 chip ec/google/chromeec
192 use conn0 as mux_conn[0]
193 use conn1 as mux_conn[1]
194 device pnp 0c09.0 on end
197 device ref pmc hidden
198 chip drivers/intel/pmc_mux
199 device generic 0 on
200 chip drivers/intel/pmc_mux/conn
201 use usb2_port1 as usb2_port
202 use tcss_usb3_port1 as usb3_port
203 device generic 0 alias conn0 on end
205 chip drivers/intel/pmc_mux/conn
206 use usb2_port3 as usb2_port
207 use tcss_usb3_port3 as usb3_port
208 device generic 1 alias conn1 on end
213 device ref tcss_xhci on
214 chip drivers/usb/acpi
215 device ref tcss_root_hub on
216 chip drivers/usb/acpi
217 register "desc" = ""USB3 Type-C Port C0 (MLB)""
218 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
219 register "use_custom_pld" = "true"
220 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
221 device ref tcss_usb3_port1 on end
223 chip drivers/usb/acpi
224 register "desc" = ""USB3 Type-C Port C2 (MLB)""
225 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
226 register "use_custom_pld" = "true"
227 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
228 device ref tcss_usb3_port3 on end
233 device ref xhci on
234 chip drivers/usb/acpi
235 device ref xhci_root_hub on
236 chip drivers/usb/acpi
237 register "desc" = ""USB2 Type-C Port C0 (MLB)""
238 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
239 register "use_custom_pld" = "true"
240 register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
241 device ref usb2_port1 on end
243 chip drivers/usb/acpi
244 register "desc" = ""USB2 Type-C Port C2 (MLB)""
245 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
246 register "use_custom_pld" = "true"
247 register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
248 device ref usb2_port3 on end
250 chip drivers/usb/acpi
251 register "desc" = ""USB2 Camera""
252 register "type" = "UPC_TYPE_INTERNAL"
253 device ref usb2_port6 on end
255 chip drivers/usb/acpi
256 register "desc" = ""USB2 Type-A Port 2""
257 register "type" = "UPC_TYPE_A"
258 register "use_custom_pld" = "true"
259 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 2))"
260 device ref usb2_port8 on end
262 chip drivers/usb/acpi
263 register "desc" = ""USB2 Type-A Port 0""
264 register "type" = "UPC_TYPE_A"
265 register "use_custom_pld" = "true"
266 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
267 device ref usb2_port9 on end
269 chip drivers/usb/acpi
270 register "desc" = ""USB2 Bluetooth""
271 register "type" = "UPC_TYPE_INTERNAL"
272 register "reset_gpio" =
273 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
274 device ref usb2_port10 on end
276 chip drivers/usb/acpi
277 register "desc" = ""USB3 Type-A Port 0""
278 register "type" = "UPC_TYPE_USB3_A"
279 register "use_custom_pld" = "true"
280 register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
281 device ref usb3_port1 on end
283 chip drivers/usb/acpi
284 register "desc" = ""USB3 Type-A Port 2""
285 register "type" = "UPC_TYPE_USB3_A"
286 register "use_custom_pld" = "true"
287 register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 2))"
288 device ref usb3_port2 on end