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sb/intel/common/spi: Properly check if setting FRP succeeded
[coreboot.git] / src / southbridge / intel / common / spi.c
blobe8c8f01407c54586258102d07fb183f157466eb1
1 /*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
4 * Copyright (C) 2011 Stefan Tauner
5 * Copyright (C) 2018 Siemens AG
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but without any warranty; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 /* This file is derived from the flashrom project. */
19 #include <stdint.h>
20 #include <stdlib.h>
21 #include <string.h>
22 #include <bootstate.h>
23 #include <commonlib/helpers.h>
24 #include <delay.h>
25 #include <device/mmio.h>
26 #include <device/pci_ops.h>
27 #include <console/console.h>
28 #include <device/device.h>
29 #include <device/pci.h>
30 #include <spi_flash.h>
31
32 #include <spi-generic.h>
33
34 #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
35 #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
36 #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
37 #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
38
39 static int spi_is_multichip(void);
40
41 struct ich7_spi_regs {
42 uint16_t spis;
43 uint16_t spic;
44 uint32_t spia;
45 uint64_t spid[8];
46 uint64_t _pad;
47 uint32_t bbar;
48 uint16_t preop;
49 uint16_t optype;
50 uint8_t opmenu[8];
51 uint32_t pbr[3];
52 } __packed;
53
54 struct ich9_spi_regs {
55 uint32_t bfpr;
56 uint16_t hsfs;
57 uint16_t hsfc;
58 uint32_t faddr;
59 uint32_t _reserved0;
60 uint32_t fdata[16];
61 uint32_t frap;
62 uint32_t freg[5];
63 uint32_t _reserved1[3];
64 uint32_t pr[5];
65 uint32_t _reserved2[2];
66 uint8_t ssfs;
67 uint8_t ssfc[3];
68 uint16_t preop;
69 uint16_t optype;
70 uint8_t opmenu[8];
71 uint32_t bbar;
72 uint8_t _reserved3[12];
73 uint32_t fdoc;
74 uint32_t fdod;
75 uint8_t _reserved4[8];
76 uint32_t afc;
77 uint32_t lvscc;
78 uint32_t uvscc;
79 uint8_t _reserved5[4];
80 uint32_t fpb;
81 uint8_t _reserved6[28];
82 uint32_t srdl;
83 uint32_t srdc;
84 uint32_t srd;
85 } __packed;
86
87 struct ich_spi_controller {
88 int locked;
89 uint32_t flmap0;
90 uint32_t flcomp;
91 uint32_t hsfs;
92
93 union {
94 struct ich9_spi_regs *ich9_spi;
95 struct ich7_spi_regs *ich7_spi;
96 };
97 uint8_t *opmenu;
98 int menubytes;
99 uint16_t *preop;
100 uint16_t *optype;
101 uint32_t *addr;
102 uint8_t *data;
103 unsigned databytes;
104 uint8_t *status;
105 uint16_t *control;
106 uint32_t *bbar;
107 uint32_t *fpr;
108 uint8_t fpr_max;
109 };
110
111 static struct ich_spi_controller g_cntlr;
112
113 enum {
114 SPIS_SCIP = 0x0001,
115 SPIS_GRANT = 0x0002,
116 SPIS_CDS = 0x0004,
117 SPIS_FCERR = 0x0008,
118 SSFS_AEL = 0x0010,
119 SPIS_LOCK = 0x8000,
120 SPIS_RESERVED_MASK = 0x7ff0,
121 SSFS_RESERVED_MASK = 0x7fe2
122 };
123
124 enum {
125 SPIC_SCGO = 0x000002,
126 SPIC_ACS = 0x000004,
127 SPIC_SPOP = 0x000008,
128 SPIC_DBC = 0x003f00,
129 SPIC_DS = 0x004000,
130 SPIC_SME = 0x008000,
131 SSFC_SCF_MASK = 0x070000,
132 SSFC_RESERVED = 0xf80000
133 };
134
135 enum {
136 HSFS_FDONE = 0x0001,
137 HSFS_FCERR = 0x0002,
138 HSFS_AEL = 0x0004,
139 HSFS_BERASE_MASK = 0x0018,
140 HSFS_BERASE_SHIFT = 3,
141 HSFS_SCIP = 0x0020,
142 HSFS_FDOPSS = 0x2000,
143 HSFS_FDV = 0x4000,
144 HSFS_FLOCKDN = 0x8000
145 };
146
147 enum {
148 HSFC_FGO = 0x0001,
149 HSFC_FCYCLE_MASK = 0x0006,
150 HSFC_FCYCLE_SHIFT = 1,
151 HSFC_FDBC_MASK = 0x3f00,
152 HSFC_FDBC_SHIFT = 8,
153 HSFC_FSMIE = 0x8000
154 };
155
156 enum {
157 SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0,
158 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1,
159 SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2,
160 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3
161 };
162
163 #if CONFIG(DEBUG_SPI_FLASH)
164
165 static u8 readb_(const void *addr)
166 {
167 u8 v = read8(addr);
168
169 printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
170 v, ((unsigned) addr & 0xffff) - 0xf020);
171 return v;
172 }
173
174 static u16 readw_(const void *addr)
175 {
176 u16 v = read16(addr);
177
178 printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
179 v, ((unsigned) addr & 0xffff) - 0xf020);
180 return v;
181 }
182
183 static u32 readl_(const void *addr)
184 {
185 u32 v = read32(addr);
186
187 printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
188 v, ((unsigned) addr & 0xffff) - 0xf020);
189 return v;
190 }
191
192 static void writeb_(u8 b, void *addr)
193 {
194 write8(addr, b);
195 printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
196 b, ((unsigned) addr & 0xffff) - 0xf020);
197 }
198
199 static void writew_(u16 b, void *addr)
200 {
201 write16(addr, b);
202 printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
203 b, ((unsigned) addr & 0xffff) - 0xf020);
204 }
205
206 static void writel_(u32 b, void *addr)
207 {
208 write32(addr, b);
209 printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
210 b, ((unsigned) addr & 0xffff) - 0xf020);
211 }
212
213 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
214
215 #define readb_(a) read8(a)
216 #define readw_(a) read16(a)
217 #define readl_(a) read32(a)
218 #define writeb_(val, addr) write8(addr, val)
219 #define writew_(val, addr) write16(addr, val)
220 #define writel_(val, addr) write32(addr, val)
221
222 #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
223
224 static void write_reg(const void *value, void *dest, uint32_t size)
225 {
226 const uint8_t *bvalue = value;
227 uint8_t *bdest = dest;
228
229 while (size >= 4) {
230 writel_(*(const uint32_t *)bvalue, bdest);
231 bdest += 4; bvalue += 4; size -= 4;
232 }
233 while (size) {
234 writeb_(*bvalue, bdest);
235 bdest++; bvalue++; size--;
236 }
237 }
238
239 static void read_reg(const void *src, void *value, uint32_t size)
240 {
241 const uint8_t *bsrc = src;
242 uint8_t *bvalue = value;
243
244 while (size >= 4) {
245 *(uint32_t *)bvalue = readl_(bsrc);
246 bsrc += 4; bvalue += 4; size -= 4;
247 }
248 while (size) {
249 *bvalue = readb_(bsrc);
250 bsrc++; bvalue++; size--;
251 }
252 }
253
254 static void ich_set_bbar(uint32_t minaddr)
255 {
256 struct ich_spi_controller *cntlr = &g_cntlr;
257 const uint32_t bbar_mask = 0x00ffff00;
258 uint32_t ichspi_bbar;
259
260 minaddr &= bbar_mask;
261 ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask;
262 ichspi_bbar |= minaddr;
263 writel_(ichspi_bbar, cntlr->bbar);
264 }
265
266 void spi_init(void)
267 {
268 struct ich_spi_controller *cntlr = &g_cntlr;
269 uint8_t *rcrb; /* Root Complex Register Block */
270 uint32_t rcba; /* Root Complex Base Address */
271 uint8_t bios_cntl;
272 struct ich9_spi_regs *ich9_spi;
273 struct ich7_spi_regs *ich7_spi;
274 uint16_t hsfs;
275
276 #ifdef __SIMPLE_DEVICE__
277 pci_devfn_t dev = PCI_DEV(0, 31, 0);
278 #else
279 struct device *dev = pcidev_on_root(31, 0);
280 #endif
281
282 rcba = pci_read_config32(dev, 0xf0);
283 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
284 rcrb = (uint8_t *)(rcba & 0xffffc000);
285 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
286 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
287 cntlr->ich7_spi = ich7_spi;
288 cntlr->opmenu = ich7_spi->opmenu;
289 cntlr->menubytes = sizeof(ich7_spi->opmenu);
290 cntlr->optype = &ich7_spi->optype;
291 cntlr->addr = &ich7_spi->spia;
292 cntlr->data = (uint8_t *)ich7_spi->spid;
293 cntlr->databytes = sizeof(ich7_spi->spid);
294 cntlr->status = (uint8_t *)&ich7_spi->spis;
295 cntlr->control = &ich7_spi->spic;
296 cntlr->bbar = &ich7_spi->bbar;
297 cntlr->preop = &ich7_spi->preop;
298 cntlr->fpr = &ich7_spi->pbr[0];
299 cntlr->fpr_max = 3;
300 } else {
301 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
302 cntlr->ich9_spi = ich9_spi;
303 hsfs = readw_(&ich9_spi->hsfs);
304 cntlr->hsfs = hsfs;
305 cntlr->opmenu = ich9_spi->opmenu;
306 cntlr->menubytes = sizeof(ich9_spi->opmenu);
307 cntlr->optype = &ich9_spi->optype;
308 cntlr->addr = &ich9_spi->faddr;
309 cntlr->data = (uint8_t *)ich9_spi->fdata;
310 cntlr->databytes = sizeof(ich9_spi->fdata);
311 cntlr->status = &ich9_spi->ssfs;
312 cntlr->control = (uint16_t *)ich9_spi->ssfc;
313 cntlr->bbar = &ich9_spi->bbar;
314 cntlr->preop = &ich9_spi->preop;
315 cntlr->fpr = &ich9_spi->pr[0];
316 cntlr->fpr_max = 5;
317
318 if (cntlr->hsfs & HSFS_FDV) {
319 writel_(4, &ich9_spi->fdoc);
320 cntlr->flmap0 = readl_(&ich9_spi->fdod);
321 writel_(0x1000, &ich9_spi->fdoc);
322 cntlr->flcomp = readl_(&ich9_spi->fdod);
323 }
324 }
325
326 ich_set_bbar(0);
327
328 /* Disable the BIOS write protect so write commands are allowed. */
329 bios_cntl = pci_read_config8(dev, 0xdc);
330 /* Deassert SMM BIOS Write Protect Disable. */
331 bios_cntl &= ~(1 << 5);
332 pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
333 }
334
335 static int spi_locked(void)
336 {
337 struct ich_spi_controller *cntlr = &g_cntlr;
338 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
339 return !!(readw_(&cntlr->ich7_spi->spis) & HSFS_FLOCKDN);
340 } else {
341 return !!(readw_(&cntlr->ich9_spi->hsfs) | HSFS_FLOCKDN);
342 }
343 }
344
345 static void spi_init_cb(void *unused)
346 {
347 spi_init();
348 }
349
350 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
351
352 typedef struct spi_transaction {
353 const uint8_t *out;
354 uint32_t bytesout;
355 uint8_t *in;
356 uint32_t bytesin;
357 uint8_t type;
358 uint8_t opcode;
359 uint32_t offset;
360 } spi_transaction;
361
362 static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
363 {
364 trans->out += bytes;
365 trans->bytesout -= bytes;
366 }
367
368 static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
369 {
370 trans->in += bytes;
371 trans->bytesin -= bytes;
372 }
373
374 static void spi_setup_type(spi_transaction *trans)
375 {
376 trans->type = 0xFF;
377
378 /* Try to guess spi type from read/write sizes. */
379 if (trans->bytesin == 0) {
380 if (trans->bytesout > 4)
381 /*
382 * If bytesin = 0 and bytesout > 4, we presume this is
383 * a write data operation, which is accompanied by an
384 * address.
385 */
386 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
387 else
388 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
389 return;
390 }
391
392 if (trans->bytesout == 1) { /* and bytesin is > 0 */
393 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
394 return;
395 }
396
397 if (trans->bytesout == 4) { /* and bytesin is > 0 */
398 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
399 }
400
401 /* Fast read command is called with 5 bytes instead of 4 */
402 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
403 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
404 --trans->bytesout;
405 }
406 }
407
408 static int spi_setup_opcode(spi_transaction *trans)
409 {
410 struct ich_spi_controller *cntlr = &g_cntlr;
411 uint16_t optypes;
412 uint8_t opmenu[cntlr->menubytes];
413
414 trans->opcode = trans->out[0];
415 spi_use_out(trans, 1);
416 if (!spi_locked()) {
417 /* The lock is off, so just use index 0. */
418 writeb_(trans->opcode, cntlr->opmenu);
419 optypes = readw_(cntlr->optype);
420 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
421 writew_(optypes, cntlr->optype);
422 return 0;
423 }
424
425 /* The lock is on. See if what we need is on the menu. */
426 uint8_t optype;
427 uint16_t opcode_index;
428
429 /* Write Enable is handled as atomic prefix */
430 if (trans->opcode == SPI_OPCODE_WREN)
431 return 0;
432
433 read_reg(cntlr->opmenu, opmenu, sizeof(opmenu));
434 for (opcode_index = 0; opcode_index < cntlr->menubytes;
435 opcode_index++) {
436 if (opmenu[opcode_index] == trans->opcode)
437 break;
438 }
439
440 if (opcode_index == cntlr->menubytes) {
441 printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
442 trans->opcode);
443 return -1;
444 }
445
446 optypes = readw_(cntlr->optype);
447 optype = (optypes >> (opcode_index * 2)) & 0x3;
448 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
449 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
450 trans->bytesout >= 3) {
451 /* We guessed wrong earlier. Fix it up. */
452 trans->type = optype;
453 }
454 if (optype != trans->type) {
455 printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
456 optype);
457 return -1;
458 }
459 return opcode_index;
460 }
461
462 static int spi_setup_offset(spi_transaction *trans)
463 {
464 /* Separate the SPI address and data. */
465 switch (trans->type) {
466 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
467 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
468 return 0;
469 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
470 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
471 trans->offset = ((uint32_t)trans->out[0] << 16) |
472 ((uint32_t)trans->out[1] << 8) |
473 ((uint32_t)trans->out[2] << 0);
474 spi_use_out(trans, 3);
475 return 1;
476 default:
477 printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type);
478 return -1;
479 }
480 }
481
482 /*
483 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
484 * below is True) or 0. In case the wait was for the bit(s) to set - write
485 * those bits back, which would cause resetting them.
486 *
487 * Return the last read status value on success or -1 on failure.
488 */
489 static int ich_status_poll(u16 bitmask, int wait_til_set)
490 {
491 struct ich_spi_controller *cntlr = &g_cntlr;
492 int timeout = 600000; /* This will result in 6 seconds */
493 u16 status = 0;
494
495 while (timeout--) {
496 status = readw_(cntlr->status);
497 if (wait_til_set ^ ((status & bitmask) == 0)) {
498 if (wait_til_set)
499 writew_((status & bitmask), cntlr->status);
500 return status;
501 }
502 udelay(10);
503 }
504
505 printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, bitmask %x\n",
506 status, bitmask);
507 return -1;
508 }
509
510 static int spi_is_multichip(void)
511 {
512 struct ich_spi_controller *cntlr = &g_cntlr;
513 if (!(cntlr->hsfs & HSFS_FDV))
514 return 0;
515 return !!((cntlr->flmap0 >> 8) & 3);
516 }
517
518 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
519 size_t bytesout, void *din, size_t bytesin)
520 {
521 struct ich_spi_controller *cntlr = &g_cntlr;
522 uint16_t control;
523 int16_t opcode_index;
524 int with_address;
525 int status;
526
527 spi_transaction trans = {
528 dout, bytesout,
529 din, bytesin,
530 0xff, 0xff, 0
531 };
532
533 /* There has to always at least be an opcode. */
534 if (!bytesout || !dout) {
535 printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
536 return -1;
537 }
538 /* Make sure if we read something we have a place to put it. */
539 if (bytesin != 0 && !din) {
540 printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
541 return -1;
542 }
543
544 if (ich_status_poll(SPIS_SCIP, 0) == -1)
545 return -1;
546
547 writew_(SPIS_CDS | SPIS_FCERR, cntlr->status);
548
549 spi_setup_type(&trans);
550 if ((opcode_index = spi_setup_opcode(&trans)) < 0)
551 return -1;
552 if ((with_address = spi_setup_offset(&trans)) < 0)
553 return -1;
554
555 if (trans.opcode == SPI_OPCODE_WREN) {
556 /*
557 * Treat Write Enable as Atomic Pre-Op if possible
558 * in order to prevent the Management Engine from
559 * issuing a transaction between WREN and DATA.
560 */
561 if (!spi_locked())
562 writew_(trans.opcode, cntlr->preop);
563 return 0;
564 }
565
566 /* Preset control fields */
567 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
568
569 /* Issue atomic preop cycle if needed */
570 if (readw_(cntlr->preop))
571 control |= SPIC_ACS;
572
573 if (!trans.bytesout && !trans.bytesin) {
574 /* SPI addresses are 24 bit only */
575 if (with_address)
576 writel_(trans.offset & 0x00FFFFFF, cntlr->addr);
577
578 /*
579 * This is a 'no data' command (like Write Enable), its
580 * bitesout size was 1, decremented to zero while executing
581 * spi_setup_opcode() above. Tell the chip to send the
582 * command.
583 */
584 writew_(control, cntlr->control);
585
586 /* wait for the result */
587 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
588 if (status == -1)
589 return -1;
590
591 if (status & SPIS_FCERR) {
592 printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n");
593 return -1;
594 }
595
596 goto spi_xfer_exit;
597 }
598
599 /*
600 * Check if this is a write command attempting to transfer more bytes
601 * than the controller can handle. Iterations for writes are not
602 * supported here because each SPI write command needs to be preceded
603 * and followed by other SPI commands, and this sequence is controlled
604 * by the SPI chip driver.
605 */
606 if (trans.bytesout > cntlr->databytes) {
607 printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
608 " spi_crop_chunk()?\n");
609 return -1;
610 }
611
612 /*
613 * Read or write up to databytes bytes at a time until everything has
614 * been sent.
615 */
616 while (trans.bytesout || trans.bytesin) {
617 uint32_t data_length;
618
619 /* SPI addresses are 24 bit only */
620 writel_(trans.offset & 0x00FFFFFF, cntlr->addr);
621
622 if (trans.bytesout)
623 data_length = min(trans.bytesout, cntlr->databytes);
624 else
625 data_length = min(trans.bytesin, cntlr->databytes);
626
627 /* Program data into FDATA0 to N */
628 if (trans.bytesout) {
629 write_reg(trans.out, cntlr->data, data_length);
630 spi_use_out(&trans, data_length);
631 if (with_address)
632 trans.offset += data_length;
633 }
634
635 /* Add proper control fields' values */
636 control &= ~((cntlr->databytes - 1) << 8);
637 control |= SPIC_DS;
638 control |= (data_length - 1) << 8;
639
640 /* write it */
641 writew_(control, cntlr->control);
642
643 /* Wait for Cycle Done Status or Flash Cycle Error. */
644 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
645 if (status == -1)
646 return -1;
647
648 if (status & SPIS_FCERR) {
649 printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n");
650 return -1;
651 }
652
653 if (trans.bytesin) {
654 read_reg(cntlr->data, trans.in, data_length);
655 spi_use_in(&trans, data_length);
656 if (with_address)
657 trans.offset += data_length;
658 }
659 }
660
661 spi_xfer_exit:
662 /* Clear atomic preop now that xfer is done */
663 writew_(0, cntlr->preop);
664
665 return 0;
666 }
667
668 /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
669 static void ich_hwseq_set_addr(uint32_t addr)
670 {
671 struct ich_spi_controller *cntlr = &g_cntlr;
672 uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
673
674 writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
675 }
676
677 /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
678 Resets all error flags in HSFS.
679 Returns 0 if the cycle completes successfully without errors within
680 timeout us, 1 on errors. */
681 static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
682 unsigned int len)
683 {
684 struct ich_spi_controller *cntlr = &g_cntlr;
685 uint16_t hsfs;
686 uint32_t addr;
687
688 timeout /= 8; /* scale timeout duration to counter */
689 while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) &
690 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
691 --timeout) {
692 udelay(8);
693 }
694 writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
695
696 if (!timeout) {
697 uint16_t hsfc;
698 addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF;
699 hsfc = readw_(&cntlr->ich9_spi->hsfc);
700 printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
701 "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
702 addr, addr + len - 1, addr, len - 1,
703 hsfc, hsfs);
704 return 1;
705 }
706
707 if (hsfs & HSFS_FCERR) {
708 uint16_t hsfc;
709 addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF;
710 hsfc = readw_(&cntlr->ich9_spi->hsfc);
711 printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
712 "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
713 addr, addr + len - 1, addr, len - 1,
714 hsfc, hsfs);
715 return 1;
716 }
717 return 0;
718 }
719
720
721 static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
722 size_t len)
723 {
724 struct ich_spi_controller *cntlr = &g_cntlr;
725 u32 start, end, erase_size;
726 int ret;
727 uint16_t hsfc;
728 uint16_t timeout = 1000 * 60;
729
730 erase_size = flash->sector_size;
731 if (offset % erase_size || len % erase_size) {
732 printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n");
733 return -1;
734 }
735
736 ret = spi_claim_bus(&flash->spi);
737 if (ret) {
738 printk(BIOS_ERR, "SF: Unable to claim SPI bus\n");
739 return ret;
740 }
741
742 start = offset;
743 end = start + len;
744
745 while (offset < end) {
746 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
747 writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
748
749 ich_hwseq_set_addr(offset);
750
751 offset += erase_size;
752
753 hsfc = readw_(&cntlr->ich9_spi->hsfc);
754 hsfc &= ~HSFC_FCYCLE; /* clear operation */
755 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
756 hsfc |= HSFC_FGO; /* start */
757 writew_(hsfc, &cntlr->ich9_spi->hsfc);
758 if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
759 printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
760 ret = -1;
761 goto out;
762 }
763 }
764
765 printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start);
766
767 out:
768 spi_release_bus(&flash->spi);
769 return ret;
770 }
771
772 static void ich_read_data(uint8_t *data, int len)
773 {
774 struct ich_spi_controller *cntlr = &g_cntlr;
775 int i;
776 uint32_t temp32 = 0;
777
778 for (i = 0; i < len; i++) {
779 if ((i % 4) == 0)
780 temp32 = readl_(cntlr->data + i);
781
782 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
783 }
784 }
785
786 static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
787 void *buf)
788 {
789 struct ich_spi_controller *cntlr = &g_cntlr;
790 uint16_t hsfc;
791 uint16_t timeout = 100 * 60;
792 uint8_t block_len;
793
794 if (addr + len > flash->size) {
795 printk(BIOS_ERR,
796 "Attempt to read %x-%x which is out of chip\n",
797 (unsigned) addr,
798 (unsigned) addr+(unsigned) len);
799 return -1;
800 }
801
802 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
803 writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
804
805 while (len > 0) {
806 block_len = min(len, cntlr->databytes);
807 if (block_len > (~addr & 0xff))
808 block_len = (~addr & 0xff) + 1;
809 ich_hwseq_set_addr(addr);
810 hsfc = readw_(&cntlr->ich9_spi->hsfc);
811 hsfc &= ~HSFC_FCYCLE; /* set read operation */
812 hsfc &= ~HSFC_FDBC; /* clear byte count */
813 /* set byte count */
814 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
815 hsfc |= HSFC_FGO; /* start */
816 writew_(hsfc, &cntlr->ich9_spi->hsfc);
817
818 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
819 return 1;
820 ich_read_data(buf, block_len);
821 addr += block_len;
822 buf += block_len;
823 len -= block_len;
824 }
825 return 0;
826 }
827
828 /* Fill len bytes from the data array into the fdata/spid registers.
829 *
830 * Note that using len > flash->pgm->spi.max_data_write will trash the registers
831 * following the data registers.
832 */
833 static void ich_fill_data(const uint8_t *data, int len)
834 {
835 struct ich_spi_controller *cntlr = &g_cntlr;
836 uint32_t temp32 = 0;
837 int i;
838
839 if (len <= 0)
840 return;
841
842 for (i = 0; i < len; i++) {
843 if ((i % 4) == 0)
844 temp32 = 0;
845
846 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
847
848 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
849 writel_(temp32, cntlr->data + (i - (i % 4)));
850 }
851 i--;
852 if ((i % 4) != 3) /* Write remaining data to regs. */
853 writel_(temp32, cntlr->data + (i - (i % 4)));
854 }
855
856 static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
857 const void *buf)
858 {
859 struct ich_spi_controller *cntlr = &g_cntlr;
860 uint16_t hsfc;
861 uint16_t timeout = 100 * 60;
862 uint8_t block_len;
863 uint32_t start = addr;
864
865 if (addr + len > flash->size) {
866 printk(BIOS_ERR,
867 "Attempt to write 0x%x-0x%x which is out of chip\n",
868 (unsigned)addr, (unsigned) (addr+len));
869 return -1;
870 }
871
872 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
873 writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);
874
875 while (len > 0) {
876 block_len = min(len, cntlr->databytes);
877 if (block_len > (~addr & 0xff))
878 block_len = (~addr & 0xff) + 1;
879
880 ich_hwseq_set_addr(addr);
881
882 ich_fill_data(buf, block_len);
883 hsfc = readw_(&cntlr->ich9_spi->hsfc);
884 hsfc &= ~HSFC_FCYCLE; /* clear operation */
885 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
886 hsfc &= ~HSFC_FDBC; /* clear byte count */
887 /* set byte count */
888 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
889 hsfc |= HSFC_FGO; /* start */
890 writew_(hsfc, &cntlr->ich9_spi->hsfc);
891
892 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
893 printk(BIOS_ERR, "SF: write failure at %x\n",
894 addr);
895 return -1;
896 }
897 addr += block_len;
898 buf += block_len;
899 len -= block_len;
900 }
901 printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
902 (unsigned) (addr - start), start);
903 return 0;
904 }
905
906 static const struct spi_flash_ops spi_flash_ops = {
907 .read = ich_hwseq_read,
908 .write = ich_hwseq_write,
909 .erase = ich_hwseq_erase,
910 };
911
912 static int spi_flash_programmer_probe(const struct spi_slave *spi,
913 struct spi_flash *flash)
914 {
915 struct ich_spi_controller *cntlr = &g_cntlr;
916
917 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
918 return spi_flash_generic_probe(spi, flash);
919
920 /* Try generic probing first if spi_is_multichip returns 0. */
921 if (!spi_is_multichip() && !spi_flash_generic_probe(spi, flash))
922 return 0;
923
924 memcpy(&flash->spi, spi, sizeof(*spi));
925 flash->name = "Opaque HW-sequencing";
926
927 ich_hwseq_set_addr(0);
928 switch ((cntlr->hsfs >> 3) & 3) {
929 case 0:
930 flash->sector_size = 256;
931 break;
932 case 1:
933 flash->sector_size = 4096;
934 break;
935 case 2:
936 flash->sector_size = 8192;
937 break;
938 case 3:
939 flash->sector_size = 65536;
940 break;
941 }
942
943 flash->size = 1 << (19 + (cntlr->flcomp & 7));
944
945 flash->ops = &spi_flash_ops;
946
947 if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3))
948 flash->size += 1 << (19 + ((cntlr->flcomp >> 3) & 7));
949 printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
950
951 return 0;
952 }
953
954 static int xfer_vectors(const struct spi_slave *slave,
955 struct spi_op vectors[], size_t count)
956 {
957 return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
958 }
959
960 #define SPI_FPR_SHIFT 12
961 #define ICH7_SPI_FPR_MASK 0xfff
962 #define ICH9_SPI_FPR_MASK 0x1fff
963 #define SPI_FPR_BASE_SHIFT 0
964 #define ICH7_SPI_FPR_LIMIT_SHIFT 12
965 #define ICH9_SPI_FPR_LIMIT_SHIFT 16
966 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */
967 #define SPI_FPR_WPE (1 << 31) /* Write Protect */
968
969 static u32 spi_fpr(u32 base, u32 limit)
970 {
971 u32 ret;
972 u32 mask, limit_shift;
973
974 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
975 mask = ICH7_SPI_FPR_MASK;
976 limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT;
977 } else {
978 mask = ICH9_SPI_FPR_MASK;
979 limit_shift = ICH9_SPI_FPR_LIMIT_SHIFT;
980 }
981 ret = ((limit >> SPI_FPR_SHIFT) & mask) << limit_shift;
982 ret |= ((base >> SPI_FPR_SHIFT) & mask) << SPI_FPR_BASE_SHIFT;
983 return ret;
984 }
985
986 /*
987 * Protect range of SPI flash defined by [start, start+size-1] using Flash
988 * Protected Range (FPR) register if available.
989 * Returns 0 on success, -1 on failure of programming fpr registers.
990 */
991 static int spi_flash_protect(const struct spi_flash *flash,
992 const struct region *region,
993 const enum ctrlr_prot_type type)
994 {
995 struct ich_spi_controller *cntlr = &g_cntlr;
996 u32 start = region_offset(region);
997 u32 end = start + region_sz(region) - 1;
998 u32 reg;
999 u32 protect_mask = 0;
1000 int fpr;
1001 uint32_t *fpr_base;
1002
1003 fpr_base = cntlr->fpr;
1004
1005 /* Find first empty FPR */
1006 for (fpr = 0; fpr < cntlr->fpr_max; fpr++) {
1007 reg = read32(&fpr_base[fpr]);
1008 if (reg == 0)
1009 break;
1010 }
1011
1012 if (fpr == cntlr->fpr_max) {
1013 printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
1014 return -1;
1015 }
1016
1017 switch (type) {
1018 case WRITE_PROTECT:
1019 protect_mask |= SPI_FPR_WPE;
1020 break;
1021 case READ_PROTECT:
1022 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
1023 return -1;
1024 protect_mask |= ICH9_SPI_FPR_RPE;
1025 break;
1026 case READ_WRITE_PROTECT:
1027 if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
1028 return -1;
1029 protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE);
1030 break;
1031 default:
1032 printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n");
1033 return -1;
1034 }
1035
1036 /* Set protected range base and limit */
1037 reg = spi_fpr(start, end) | protect_mask;
1038
1039 /* Set the FPR register and verify it is protected */
1040 write32(&fpr_base[fpr], reg);
1041 if (reg != read32(&fpr_base[fpr])) {
1042 printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
1043 return -1;
1044 }
1045
1046 printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n",
1047 __func__, fpr, start, end);
1048 return 0;
1049 }
1050
1051 static const struct spi_ctrlr spi_ctrlr = {
1052 .xfer_vector = xfer_vectors,
1053 .max_xfer_size = member_size(struct ich9_spi_regs, fdata),
1054 .flash_probe = spi_flash_programmer_probe,
1055 .flash_protect = spi_flash_protect,
1056 };
1057
1058 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
1059 {
1060 .ctrlr = &spi_ctrlr,
1061 .bus_start = 0,
1062 .bus_end = 0,
1063 },
1064 };
1065
1066 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
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