3 config NO_BOOTBLOCK_CONSOLE
6 config BOOTBLOCK_CONSOLE
7 bool "Enable early (bootblock) console output."
8 depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE
11 Use console during the bootblock if supported
13 config POSTCAR_CONSOLE
14 bool "Enable console output during postcar."
15 depends on POSTCAR_STAGE
18 Use console during the postcar if supported
20 config SQUELCH_EARLY_SMP
21 bool "Squelch AP CPUs from early console."
25 When selected only the BSP CPU will output to early console.
27 Console drivers have unpredictable behaviour if multiple threads
28 attempt to share the same resources without a spinlock.
33 bool "Serial port console output"
35 depends on DRIVERS_UART
37 Send coreboot debug output to a serial port.
39 The type of serial port driver selected based on your configuration is
40 shown on the following menu line. Supporting multiple different types
41 of UARTs in one build is not supported.
43 config FIXED_UART_FOR_CONSOLE
46 Select to remove the prompt from UART_FOR_CONSOLE in case a
47 specific UART has to be used (e.g. when the platform code
48 performs dangerous configurations).
52 comment "I/O mapped, 8250-compatible"
53 depends on DRIVERS_UART_8250IO
55 comment "memory mapped, 8250-compatible"
56 depends on DRIVERS_UART_8250MEM
58 comment "device-specific UART"
59 depends on HAVE_UART_SPECIAL
61 config UART_FOR_CONSOLE
63 prompt "Index for UART port to use for console" if !FIXED_UART_FOR_CONSOLE
66 Select an I/O port to use for serial console:
67 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
69 # FIXME: Early programming in romstage is incorrect as we should
70 # program different LDN to actually change the physical port.
73 depends on DRIVERS_UART
74 default 0x3f8 if UART_FOR_CONSOLE = 0
75 default 0x2f8 if UART_FOR_CONSOLE = 1
76 default 0x3e8 if UART_FOR_CONSOLE = 2
77 default 0x2e8 if UART_FOR_CONSOLE = 3
79 Map the COM port number to the respective I/O port.
81 comment "Serial port base address = 0x3f8"
82 depends on UART_FOR_CONSOLE = 0
83 comment "Serial port base address = 0x2f8"
84 depends on UART_FOR_CONSOLE = 1
85 comment "Serial port base address = 0x3e8"
86 depends on UART_FOR_CONSOLE = 2
87 comment "Serial port base address = 0x2e8"
88 depends on UART_FOR_CONSOLE = 3
90 config UART_OVERRIDE_BAUDRATE
93 Set to "y" when the platform overrides the baudrate by providing
94 a get_uart_baudrate routine.
96 if !UART_OVERRIDE_BAUDRATE
100 default CONSOLE_SERIAL_115200
102 config CONSOLE_SERIAL_921600
105 Set serial port Baud rate to 921600.
106 config CONSOLE_SERIAL_460800
109 Set serial port Baud rate to 460800.
110 config CONSOLE_SERIAL_230400
113 Set serial port Baud rate to 230400.
114 config CONSOLE_SERIAL_115200
117 Set serial port Baud rate to 115200.
118 config CONSOLE_SERIAL_57600
121 Set serial port Baud rate to 57600.
122 config CONSOLE_SERIAL_38400
125 Set serial port Baud rate to 38400.
126 config CONSOLE_SERIAL_19200
129 Set serial port Baud rate to 19200.
130 config CONSOLE_SERIAL_9600
133 Set serial port Baud rate to 9600.
137 #FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!)
140 default 921600 if CONSOLE_SERIAL_921600
141 default 460800 if CONSOLE_SERIAL_460800
142 default 230400 if CONSOLE_SERIAL_230400
143 default 115200 if CONSOLE_SERIAL_115200
144 default 57600 if CONSOLE_SERIAL_57600
145 default 38400 if CONSOLE_SERIAL_38400
146 default 19200 if CONSOLE_SERIAL_19200
147 default 9600 if CONSOLE_SERIAL_9600
149 Map the Baud rates to an integer.
153 # TODO: Allow user-friendly selection of settings other than 8n1.
157 depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM
159 endif # CONSOLE_SERIAL
162 bool "spkmodem (console on speaker) console output"
166 Send coreboot debug output through speaker
169 bool "USB dongle console output"
173 Send coreboot debug output to USB.
175 Configuration for USB hardware is under menu Generic Drivers.
178 # TODO: Improve description.
179 config ONBOARD_VGA_IS_PRIMARY
180 bool "Use onboard VGA as primary video device"
184 If not selected, the last adapter found will be used.
187 bool "Network console over NE2000 compatible Ethernet adapter"
191 Send coreboot debug output to a Ethernet console, it works
192 same way as Linux netconsole, packets are received to UDP
193 port 6666 on IP/MAC specified with options bellow.
194 Use following netcat command: nc -u -l -p 6666
196 config CONSOLE_NE2K_DST_MAC
197 depends on CONSOLE_NE2K
198 string "Destination MAC address of remote system"
199 default "00:13:d4:76:a2:ac"
201 Type in either MAC address of logging system or MAC address
204 config CONSOLE_NE2K_DST_IP
205 depends on CONSOLE_NE2K
206 string "Destination IP of logging system"
209 This is IP address of the system running for example
210 netcat command to dump the packets.
212 config CONSOLE_NE2K_SRC_IP
213 depends on CONSOLE_NE2K
214 string "IP address of coreboot system"
217 This is the IP of the coreboot system
219 config CONSOLE_NE2K_IO_PORT
220 depends on CONSOLE_NE2K
221 hex "NE2000 adapter fixed IO port address"
224 This is the IO port address for the IO port
225 on the card, please select some non-conflicting region,
226 32 bytes of IO spaces will be used (and align on 32 bytes
227 boundary, qemu needs broader align)
230 bool "Send console output to a CBMEM buffer"
233 Enable this to save the console output in a CBMEM buffer. This would
234 allow to see coreboot console output from Linux space.
238 config CONSOLE_CBMEM_BUFFER_SIZE
239 hex "Room allocated for console output in CBMEM"
242 Space allocated for console output storage in CBMEM. The default
243 value (128K or 0x20000 bytes) is large enough to accommodate
244 even the BIOS_SPEW level.
246 config CONSOLE_CBMEM_DUMP_TO_UART
247 depends on !CONSOLE_SERIAL
248 bool "Dump CBMEM console on resets"
251 Enable this to have CBMEM console buffer contents dumped on the
252 serial output in case serial console is disabled and the device
253 resets itself while trying to boot the payload.
257 config CONSOLE_SPI_FLASH
258 bool "SPI Flash console output"
260 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if !COMMON_CBFS_SPI_WRAPPER
262 Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area
264 This option can cause premature wear on the SPI flash and should not
265 be used as a normal means of debugging. It is only to be enabled and
266 used when porting a new motherboard which has no other console
267 available (no UART, no POST, no cbmem access(non bootable)). Since
268 a non bootable machine will require the use of an external SPI Flash
269 programmer, the developer can grab the console log at the same time.
271 The flash console will not be erased on reboot, so once it is full,
272 the flashconsole driver will stop writing to it. This is to avoid
273 wear on the flash, and to avoid erasing sectors (which may freeze
274 the SPI controller on skylake).
276 The 'CONSOLE' area can be extracted from the FMAP with :
277 cbfstool rom.bin read -r CONSOLE -f console.log
279 config CONSOLE_SPI_FLASH_BUFFER_SIZE
280 hex "Room allocated for console output in FMAP"
282 depends on CONSOLE_SPI_FLASH
284 Space allocated for console output storage in FMAP. The default
285 value (128K or 0x20000 bytes) is large enough to accommodate
286 even the BIOS_SPEW level.
288 config CONSOLE_QEMU_DEBUGCON
289 bool "QEMU debug console output"
290 depends on BOARD_EMULATION_QEMU_X86
293 Send coreboot debug output to QEMU's isa-debugcon device:
296 -chardev file,id=debugcon,path=/dir/file.log \
297 -device isa-debugcon,iobase=0x402,chardev=debugcon
299 config CONSOLE_QEMU_DEBUGCON_PORT
300 hex "QEMU debug console port"
301 depends on CONSOLE_QEMU_DEBUGCON
305 bool "SPI debug console output"
306 depends on HAVE_SPI_CONSOLE_SUPPORT && !DEBUG_SPI_FLASH
308 Enable support for the debug console on the Dediprog EM100Pro.
309 This is currently working only in ramstage due to how the spi
312 config CONSOLE_OVERRIDE_LOGLEVEL
315 Set to "y" when the platform overrides the loglevel by providing
316 a get_console_loglevel routine.
318 if !CONSOLE_OVERRIDE_LOGLEVEL
321 prompt "Default console log level"
322 default DEFAULT_CONSOLE_LOGLEVEL_8 if CHROMEOS
323 default DEFAULT_CONSOLE_LOGLEVEL_7
325 config DEFAULT_CONSOLE_LOGLEVEL_8
328 Way too many details.
329 config DEFAULT_CONSOLE_LOGLEVEL_7
332 Debug-level messages.
333 config DEFAULT_CONSOLE_LOGLEVEL_6
336 Informational messages.
337 config DEFAULT_CONSOLE_LOGLEVEL_5
340 Normal but significant conditions.
341 config DEFAULT_CONSOLE_LOGLEVEL_4
345 config DEFAULT_CONSOLE_LOGLEVEL_3
349 config DEFAULT_CONSOLE_LOGLEVEL_2
353 config DEFAULT_CONSOLE_LOGLEVEL_1
356 Action must be taken immediately.
357 config DEFAULT_CONSOLE_LOGLEVEL_0
364 config DEFAULT_CONSOLE_LOGLEVEL
366 default 0 if DEFAULT_CONSOLE_LOGLEVEL_0
367 default 1 if DEFAULT_CONSOLE_LOGLEVEL_1
368 default 2 if DEFAULT_CONSOLE_LOGLEVEL_2
369 default 3 if DEFAULT_CONSOLE_LOGLEVEL_3
370 default 4 if DEFAULT_CONSOLE_LOGLEVEL_4
371 default 5 if DEFAULT_CONSOLE_LOGLEVEL_5
372 default 6 if DEFAULT_CONSOLE_LOGLEVEL_6
373 default 7 if DEFAULT_CONSOLE_LOGLEVEL_7
374 default 8 if DEFAULT_CONSOLE_LOGLEVEL_8
376 Map the log level config names to an integer.
381 bool "Don't show any POST codes"
385 bool "Store post codes in CMOS for debugging"
386 depends on !NO_POST && PC80_SYSTEM
389 If enabled, coreboot will store post codes in CMOS and switch between
390 two offsets on each boot so the last post code in the previous boot
391 can be retrieved. This uses 3 bytes of CMOS.
393 config CMOS_POST_OFFSET
394 hex "Offset into CMOS to store POST codes"
398 If CMOS_POST is enabled then an offset into CMOS must be provided.
399 If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
400 defined in the mainboard option table.
402 config CMOS_POST_EXTRA
403 bool "Store extra logging info into CMOS"
407 This will enable extra logging of work that happens between post
408 codes into CMOS for debug. This uses an additional 8 bytes of CMOS.
411 bool "Show POST codes on the debug console"
415 If enabled, coreboot will additionally print POST codes (which are
416 usually displayed using a so-called "POST card" ISA/PCI/PCI-E
417 device) on the debug console.
420 bool "Send POST codes to an external device"
425 prompt "Device to send POST codes to"
426 depends on POST_DEVICE
427 default POST_DEVICE_NONE
429 config POST_DEVICE_NONE
431 config POST_DEVICE_LPC
434 config POST_DEVICE_PCI_PCIE
440 bool "Send POST codes to an IO port"
441 depends on PC80_SYSTEM && !NO_POST
444 If enabled, POST codes will be written to an IO port.
448 hex "IO port for POST codes"
451 POST codes on x86 are typically written to the LPC bus on port
452 0x80. However, it may be desirable to change the port number
453 depending on the presence of coprocessors/microcontrollers or if the
454 platform does not support IO in the conventional x86 manner.
456 config NO_EARLY_BOOTBLOCK_POSTCODES
459 Some chipsets require that the routing for the port 80h POST
460 code be configured before any POST codes are sent out.
461 This can be done in the boot block, but there are a couple of
462 POST codes that go out before the chipset's bootblock initialization
463 can happen. This option suppresses those POST codes.
465 config HWBASE_DEBUG_CB
467 default y if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
470 config HWBASE_DEBUG_NULL
472 depends on !HWBASE_DEBUG_CB