src/soc/intel/apollolake/bootblock/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2016-2018 Intel Corp.
   5  * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <bootblock_common.h>
  19 #include <cpu/x86/pae.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ops.h>
  22 #include <intelblocks/cpulib.h>
  23 #include <intelblocks/fast_spi.h>
  24 #include <intelblocks/p2sb.h>
  25 #include <intelblocks/pcr.h>
  26 #include <intelblocks/rtc.h>
  27 #include <intelblocks/systemagent.h>
  28 #include <intelblocks/pmclib.h>
  29 #include <intelblocks/tco.h>
  30 #include <intelblocks/uart.h>
  31 #include <soc/iomap.h>
  32 #include <soc/cpu.h>
  33 #include <soc/gpio.h>
  34 #include <soc/systemagent.h>
  35 #include <soc/pci_devs.h>
  36 #include <soc/pm.h>
  37 #include <spi-generic.h>
  38 #include <timestamp.h>
  39
  40 static const struct pad_config tpm_spi_configs[] = {
  41 #if CONFIG(SOC_INTEL_GLK)
  42         PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */
  43 #else
  44         PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),        /* FST_SPI_CS2_N */
  45 #endif
  46 };
  47
  48 static void tpm_enable(void)
  49 {
  50         /* Configure gpios */
  51         gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
  52 }
  53
  54 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  55 {
  56         pci_devfn_t dev;
  57
  58         bootblock_systemagent_early_init();
  59
  60         p2sb_enable_bar();
  61         p2sb_configure_hpet();
  62
  63         /* Decode the ACPI I/O port range for early firmware verification.*/
  64         dev = PCH_DEV_PMC;
  65         pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
  66         pci_write_config16(dev, PCI_COMMAND,
  67                                 PCI_COMMAND_IO | PCI_COMMAND_MASTER);
  68
  69         enable_rtc_upper_bank();
  70
  71         /* Call lib/bootblock.c main */
  72         bootblock_main_with_timestamp(base_timestamp, NULL, 0);
  73 }
  74
  75 static void enable_pmcbar(void)
  76 {
  77         pci_devfn_t pmc = PCH_DEV_PMC;
  78
  79         /* Set PMC base addresses and enable decoding. */
  80         pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
  81         pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */
  82         pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
  83         pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
  84         pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS);
  85         pci_write_config16(pmc, PCI_COMMAND,
  86                                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  87                                 PCI_COMMAND_MASTER);
  88 }
  89
  90 void bootblock_soc_early_init(void)
  91 {
  92         enable_pmcbar();
  93
  94         /* Clear global reset promotion bit */
  95         pmc_global_reset_enable(0);
  96
  97         /* Prepare UART for serial console. */
  98         if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
  99                 uart_bootblock_init();
 100
 101         if (CONFIG(TPM_ON_FAST_SPI))
 102                 tpm_enable();
 103
 104         enable_pm_timer_emulation();
 105
 106         fast_spi_early_init(SPI_BASE_ADDRESS);
 107
 108         fast_spi_cache_bios_region();
 109
 110         /* Initialize GPE for use as interrupt status */
 111         pmc_gpe_init();
 112
 113         /* Program TCO Timer Halt */
 114         tco_configure();
 115
 116         /* Use Nx and paging to prevent the frontend from writing back dirty
 117          * cache-as-ram lines to backing store that doesn't exist when the L1I
 118          * speculatively fetches a line that is sitting in the L1D. */
 119         if (CONFIG(PAGING_IN_CACHE_AS_RAM)) {
 120                 paging_set_nxe(1);
 121                 paging_set_default_pat();
 122                 paging_enable_for_car("pdpt", "pt");
 123         }
 124 }
 125
 126 void bootblock_soc_init(void)
 127 {
 128         /*
 129          * Clear the GPI interrupt enable & status registers to avoid any
 130          * interrupt storm during the kernel bootup.
 131          */
 132         gpi_clear_int_cfg();
 133 }