AGESA boards: Clean up some includes
[coreboot.git] / util / romcc / romcc.1
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1 .TH ROMCC 1 "September 19, 2006"
2 .SH NAME
3 romcc \- compile C programs into binaries that don't use any RAM
4 .SH SYNOPSIS
5 .B romcc
6 [OPTIONS]
7 <source>.c
8 .SH DESCRIPTION
9 .B romcc
10 is a C compiler which produces binaries which do not rely on RAM, but
11 instead only use CPU registers.
12 .PP
13 It is prominently used in the coreboot project to compile C code which
14 needs to run before the firmware has initialized the RAM, but can be
15 used for other purposes, too.
16 .SH OPTIONS
17 .TP
18 .B "\-o" <filename>
19 Output file name.
20 .TP
21 .B "\-f<option>"
22 Specify a generic compiler option.
23 .TP
24 .B "\-m<option>"
25 Specify an architecture-dependent compiler option.
26 .TP
27 .B "\-\-"
28 Specify that this is the last option.
29 .SH "GENERIC COMPILER OPTIONS"
30 .B "\-O"
31 .TP
32 .B "\-O2"
33 .TP
34 .B "\-E"
35 .TP
36 .B "\-ftrigraphs"
37 .TP
38 .B "\-fno-trigraphs"
39 .TP
40 .B "\-fpp-only"
41 .TP
42 .B "\-fno-pp-only"
43 .TP
44 .B "\-feliminate-inefectual-code"
45 .TP
46 .B "\-fno-eliminate-inefectual-code"
47 .TP
48 .B "\-fsimplify"
49 .TP
50 .B "\-fno-simplify"
51 .TP
52 .B "\-fscc-transform"
53 .TP
54 .B "\-fno-scc-transform"
55 .TP
56 .B "\-fsimplify-op"
57 .TP
58 .B "\-fno-simplify-op"
59 .TP
60 .B "\-fsimplify-phi"
61 .TP
62 .B "\-fno-simplify-phi"
63 .TP
64 .B "\-fsimplify-label"
65 .TP
66 .B "\-fno-simplify-label"
67 .TP
68 .B "\-fsimplify-branch"
69 .TP
70 .B "\-fno-simplify-branch"
71 .TP
72 .B "\-fsimplify-copy"
73 .TP
74 .B "\-fno-simplify-copy"
75 .TP
76 .B "\-fsimplify-arith"
77 .TP
78 .B "\-fno-simplify-arith"
79 .TP
80 .B "\-fsimplify-shift"
81 .TP
82 .B "\-fno-simplify-shift"
83 .TP
84 .B "\-fsimplify-bitwise"
85 .TP
86 .B "\-fno-simplify-bitwise"
87 .TP
88 .B "\-fsimplify-logical"
89 .TP
90 .B "\-fno-simplify-logical"
91 .TP
92 .B "\-fsimplify-bitfield"
93 .TP
94 .B "\-fno-simplify-bitfield"
95 .TP
96 .B "\-finline-policy=always"
97 .TP
98 .B "\-finline-policy=never"
99 .TP
100 .B "\-finline-policy=defaulton"
102 .B "\-finline-policy=defaultoff"
104 .B "\-finline-policy=nopenalty"
106 .B "\-fdebug-all"
108 .B "\-fno-debug-all"
110 .B "\-fdebug-abort-on-error"
112 .B "\-fno-debug-abort-on-error"
114 .B "\-fdebug-basic-blocks"
116 .B "\-fno-debug-basic-blocks"
118 .B "\-fdebug-fdominators"
120 .B "\-fno-debug-fdominators"
122 .B "\-fdebug-rdominators"
124 .B "\-fno-debug-rdominators"
126 .B "\-fdebug-triples"
128 .B "\-fno-debug-triples"
130 .B "\-fdebug-interference"
132 .B "\-fno-debug-interference"
134 .B "\-fdebug-scc-transform"
136 .B "\-fno-debug-scc-transform"
138 .B "\-fdebug-scc-transform2"
140 .B "\-fno-debug-scc-transform2"
142 .B "\-fdebug-rebuild-ssa-form"
144 .B "\-fno-debug-rebuild-ssa-form"
146 .B "\-fdebug-inline"
148 .B "\-fno-debug-inline"
150 .B "\-fdebug-live-range-conflicts"
152 .B "\-fno-debug-live-range-conflicts"
154 .B "\-fdebug-live-range-conflicts2"
156 .B "\-fno-debug-live-range-conflicts2"
158 .B "\-fdebug-color-graph"
160 .B "\-fno-debug-color-graph"
162 .B "\-fdebug-color-graph2"
164 .B "\-fno-debug-color-graph2"
166 .B "\-fdebug-coalescing"
168 .B "\-fno-debug-coalescing"
170 .B "\-fdebug-coalescing2"
172 .B "\-fno-debug-coalescing2"
174 .B "\-fdebug-verification"
176 .B "\-fno-debug-verification"
178 .B "\-fdebug-calls"
180 .B "\-fno-debug-calls"
182 .B "\-fdebug-calls2"
184 .B "\-fno-debug-calls2"
186 .B "\-fdebug-tokens"
188 .B "\-fno-debug-tokens"
190 .B "\-flabel-prefix=<prefix for assembly language labels>"
192 .B "\-\-label-prefix=<prefix for assembly language labels>"
194 .B "\-I<include path>"
196 .B "\-D<macro>[=defn]"
198 .B "\-U<macro>"
199 .SH "ARCHITECTURE-SPECIFIC COMPILER OPTIONS"
200 .B "\-mmmx"
202 .B "\-mno-mmx"
204 .B "\-msse"
206 .B "\-mno-sse"
208 .B "\-mnoop-copy"
210 .B "\-mno-noop-copy"
212 .B "\-mcpu=i386"
214 .B "\-mcpu=p2"
216 .B "\-mcpu=p3"
218 .B "\-mcpu=p4"
220 .B "\-mcpu=k7"
222 .B "\-mcpu=k8"
224 .B "\-mcpu=c3"
226 .B "\-mcpu=c3-2"
227 .SH BUGS
228 Please report any bugs to https://ticket.coreboot.org/projects/coreboot or the
229 coreboot mailing list at <coreboot@coreboot.org>.
230 .SH LICENCE
231 .B romcc
232 is covered by the GNU General Public License (GPL), version 2.
233 .SH SEE ALSO
234 .BR flashrom (1),
235 .BR abuild (1).
236 .SH COPYRIGHT
237 2003-2006 Eric W. Biederman
238 .SH AUTHORS
239 Eric W. Biederman <ebiederman@lnxi.com>
241 Some contributions by others.
243 This manual page was written by Uwe Hermann <uwe@hermann-uwe.de>.
244 It is licensed under the terms of the GNU GPL (v2 or later).