src/mainboard/intel/adlrvp/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/variants.h>
   4 #include <soc/romstage.h>
   5
   6 #include "board_id.h"
   7
   8 static const struct mb_cfg ddr4_mem_config = {
   9         .type = MEM_TYPE_DDR4,
  10
  11         .rcomp = {
  12                 /* Baseboard uses only 100ohm Rcomp resistor */
  13                 .resistor = 100,
  14
  15                 /* Baseboard Rcomp target values */
  16                 .targets = { 50, 20, 25, 25, 25 },
  17         },
  18
  19         .ect = true, /* Early Command Training */
  20
  21         .UserBd = BOARD_TYPE_MOBILE,
  22
  23         .LpDdrDqDqsReTraining = 1,
  24
  25         .ddr_config = {
  26                 .dq_pins_interleaved = false,
  27         },
  28 };
  29
  30 static const struct mb_cfg lpddr4_mem_config = {
  31         .type = MEM_TYPE_LP4X,
  32
  33         /* DQ byte map */
  34         .lpx_dq_map = {
  35                 .ddr0 = {
  36                         .dq0 = {  0,  2,  3,  1,  6,  7,  5,  4, },
  37                         .dq1 = { 10,  8, 11,  9, 14, 12, 13, 15, },
  38                 },
  39                 .ddr1 = {
  40                         .dq0 = { 12,  8, 14, 10, 11, 13, 15,  9, },
  41                         .dq1 = {  5,  0,  7,  3,  6,  2,  1,  4, },
  42                 },
  43                 .ddr2 = {
  44                         .dq0 = {  3,  0,  2,  1,  6,  5,  4,  7, },
  45                         .dq1 = { 12, 13, 14, 15, 10,  9,  8, 11, },
  46                 },
  47                 .ddr3 = {
  48                         .dq0 = {  2,  6,  7,  1,  3,  4,  0,  5, },
  49                         .dq1 = {  9, 13,  8, 15, 14, 11, 12, 10, },
  50                 },
  51                 .ddr4 = {
  52                         .dq0 = {  3,  0,  1,  2,  7,  4,  6,  5, },
  53                         .dq1 = { 10,  8, 11,  9, 14, 13, 12, 15, },
  54                 },
  55                 .ddr5 = {
  56                         .dq0 = { 10, 12, 14,  8,  9, 13, 15, 11, },
  57                         .dq1 = {  3,  7,  6,  2,  0,  4,  5,  1, },
  58                 },
  59                 .ddr6 = {
  60                         .dq0 = { 12, 15, 14, 13,  9, 10, 11,  8, },
  61                         .dq1 = {  7,  4,  6,  5,  0,  1,  3,  2, },
  62                 },
  63                 .ddr7 = {
  64                         .dq0 = {  0,  2,  4,  3,  1,  6,  7,  5, },
  65                         .dq1 = { 13,  9, 10, 11,  8, 12, 14, 15, },
  66                 },
  67         },
  68
  69         /* DQS CPU<>DRAM map */
  70         .lpx_dqs_map = {
  71                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
  72                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
  73                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  74                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  75                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
  76                 .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
  77                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  78                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  79         },
  80
  81         .LpDdrDqDqsReTraining = 1,
  82
  83         .ect = true, /* Early Command Training */
  84
  85         .UserBd = BOARD_TYPE_MOBILE,
  86 };
  87
  88 static const struct mb_cfg lp5_mem_config = {
  89         .type = MEM_TYPE_LP5X,
  90
  91         /* DQ byte map */
  92         .lpx_dq_map = {
  93                 .ddr0 = {
  94                         .dq0 = {  3,  2,  1,  0,  5,  4,  6,  7, },
  95                         .dq1 = { 15, 14, 12, 13,  8,  9, 10, 11, },
  96                 },
  97                 .ddr1 = {
  98                         .dq0 = {  0,  2,  3,  1,  5,  7,  4,  6, },
  99                         .dq1 = { 14, 13, 15, 12,  8,  9, 11, 10, },
 100                 },
 101                 .ddr2 = {
 102                         .dq0 = {  1,  2,  0,  3,  4,  6,  5,  7, },
 103                         .dq1 = { 15, 13, 12, 14,  9, 10,  8, 11, },
 104                 },
 105                 .ddr3 = {
 106                         .dq0 = {  2,  1,  3,  0,  7,  4,  5,  6, },
 107                         .dq1 = { 13, 12, 15, 14,  9, 11,  8, 10, },
 108                 },
 109                 .ddr4 = {
 110                         .dq0 = {  1,  2,  3,  0,  6,  4,  5,  7, },
 111                         .dq1 = { 15, 13, 14, 12, 10,  9,  8, 11, },
 112                 },
 113                 .ddr5 = {
 114                         .dq0 = {  1,  0,  3,  2,  6,  7,  4,  5, },
 115                         .dq1 = { 14, 12, 15, 13,  8,  9, 10, 11, },
 116                 },
 117                 .ddr6 = {
 118                         .dq0 = {  0,  2,  1,  3,  4,  7,  5,  6, },
 119                         .dq1 = { 12, 13, 15, 14,  9, 11, 10,  8, },
 120                 },
 121                 .ddr7 = {
 122                         .dq0 = {  3,  2,  1,  0,  5,  4,  6,  7, },
 123                         .dq1 = { 13, 15, 11, 12, 10,  9, 14,  8, },
 124                 },
 125         },
 126
 127         /* DQS CPU<>DRAM map */
 128         .lpx_dqs_map = {
 129                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
 130                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
 131                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
 132                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
 133                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
 134                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
 135                 .ddr6 = { .dqs0 = 0, .dqs1 = 1 },
 136                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
 137         },
 138
 139         .ect = false, /* Early Command Training */
 140
 141         .LpDdrDqDqsReTraining = 1,
 142
 143         .UserBd = BOARD_TYPE_MOBILE,
 144
 145         .lp5x_config = {
 146                 .ccc_config = 0xff,
 147         },
 148 };
 149
 150 static const struct mb_cfg ddr5_mem_config = {
 151         .type = MEM_TYPE_DDR5,
 152
 153         .rcomp = {
 154                 /* Baseboard uses only 100ohm Rcomp resistor */
 155                 .resistor = 100,
 156
 157                 /* Baseboard Rcomp target values */
 158                 .targets = { 50, 30, 30, 30, 27 },
 159         },
 160
 161         .ect = true, /* Early Command Training */
 162
 163         .UserBd = BOARD_TYPE_MOBILE,
 164
 165         .LpDdrDqDqsReTraining = 1,
 166
 167         .ddr_config = {
 168                 .dq_pins_interleaved = false,
 169         }
 170 };
 171
 172 static const struct mb_cfg adlm_lp4_mem_config = {
 173         .type = MEM_TYPE_LP4X,
 174
 175         /* DQ byte map */
 176         .lpx_dq_map = {
 177                 .ddr0 = {
 178                         .dq0 = { 13, 12, 14, 8, 11, 10, 9, 15, }, /* DDR0_DQ0[7:0] */
 179                         .dq1 = {  3,  2,  7, 6,  0,  1, 5,  4, }, /* DDR0_DQ1[7:0] */
 180                 },
 181                 .ddr1 = {
 182                         .dq0 = { 11, 15, 10, 9, 12, 8, 14, 13, },  /* DDR1_DQ0[7:0] */
 183                         .dq1 = {  0,  1,  7, 6,  2, 5,  4,  3, },  /* DDR1_DQ1[7:0] */
 184                 },
 185                 .ddr2 = {
 186                         .dq0 = {  6, 7,  3,  2,  0, 4,  1,  5, }, /* DDR2_DQ0[7:0] */
 187                         .dq1 = { 14, 8, 13, 12, 11, 9, 10, 15, }, /* DDR2_DQ1[7:0] */
 188                 },
 189                 .ddr3 = {
 190                         .dq0 = { 2,  6,  7,  3,  1,  5, 0,  4, }, /* DDR3_DQ0[7:0] */
 191                         .dq1 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
 192                 },
 193                 .ddr4 = {
 194                         .dq0 = { 8, 14, 13, 12, 10, 11, 9, 15, }, /* DDR3_DQ1[7:0] */
 195                         .dq1 = { 1,  0,  5,  4,  6,  2, 3,  7, }, /* DDR4_DQ1[7:0] */
 196                 },
 197                 .ddr5 = {
 198                         .dq0 = { 8, 10, 9, 12, 14, 11, 13, 15, }, /* DDR5_DQ0[7:0] */
 199                         .dq1 = { 0,  7, 2,  6,  3,  1,  4,  5, }, /* DDR5_DQ1[7:0] */
 200                 },
 201                 .ddr6 = {
 202                         .dq0 = { 14, 12, 9, 8, 15, 10, 13, 11, }, /* DDR6_DQ0[7:0] */
 203                         .dq1 = {  4,  0, 5, 6,  3,  2,  1,  7, }, /* DDR6_DQ1[7:0] */
 204                 },
 205                 .ddr7 = {
 206                         .dq0 = { 10, 15, 12, 11, 9, 14, 13, 8, }, /* DDR7_DQ0[7:0] */
 207                         .dq1 = {  7,  1,  2,  3, 6,  0,  5, 4, }, /* DDR7_DQ1[7:0] */
 208                 },
 209         },
 210
 211         /* DQS CPU<>DRAM map */
 212         .lpx_dqs_map = {
 213                 .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
 214                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
 215                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
 216                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
 217                 .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
 218                 .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
 219                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
 220                 .ddr7 = { .dqs0 = 1, .dqs1 = 0 }
 221         },
 222
 223         .ect = true, /* Early Command Training */
 224
 225         .CmdMirror = 0xCC,
 226
 227         .LpDdrDqDqsReTraining = 1,
 228
 229         .UserBd = BOARD_TYPE_ULT_ULX,
 230 };
 231
 232 static const struct mb_cfg adlm_lp5_mem_config = {
 233         .type = MEM_TYPE_LP5X,
 234
 235         /* DQ byte map */
 236         .lpx_dq_map = {
 237                 .ddr0 = {
 238                         .dq0 = {  4,  5,  7,  6,  3,  2,  1,  0, },
 239                         .dq1 = { 12, 10,  8, 15, 11,  9, 14, 13, },
 240                 },
 241                 .ddr1 = {
 242                         .dq0 = {  1,  0,  2,  3,  7,  4,  5,  6, },
 243                         .dq1 = { 14, 15, 10, 11, 13, 12,  8,  9, },
 244                 },
 245                 .ddr2 = {
 246                         .dq0 = {  7,  4,  2,  0,  3,  1,  6,  5, },
 247                         .dq1 = { 14, 13, 15, 12,  8,  9, 10, 11, },
 248                 },
 249                 .ddr3 = {
 250                         .dq0 = {  3,  2,  0,  1,  7,  5,  6,  4, },
 251                         .dq1 = { 12, 14, 15, 13, 11,  8, 10,  9, },
 252                 },
 253                 .ddr4 = {
 254                         .dq0 = {  2,  3,  0,  1,  6,  4,  7,  5, },
 255                         .dq1 = { 14,  9, 11, 13, 12,  8, 15, 10, },
 256                 },
 257                 .ddr5 = {
 258                         .dq0 = {  4,  7,  3,  1,  5,  2,  6,  0, },
 259                         .dq1 = { 14,  8, 11,  9, 12, 15, 10, 13, },
 260                 },
 261                 .ddr6 = {
 262                         .dq0 = { 10, 11, 13,  9, 15, 12,  8, 14, },
 263                         .dq1 = {  2,  4,  7,  0,  6,  3,  5,  1, },
 264                 },
 265                 .ddr7 = {
 266                         .dq0 = { 13, 15, 11, 14, 10, 12,  8,  9, },
 267                         .dq1 = {  6,  5,  4,  7,  3,  1,  2,  0, },
 268                 },
 269         },
 270
 271         /* DQS CPU<>DRAM map */
 272         .lpx_dqs_map = {
 273                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
 274                 .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
 275                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
 276                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
 277                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
 278                 .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
 279                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
 280                 .ddr7 = { .dqs0 = 1, .dqs1 = 0 }
 281         },
 282
 283         .ect = false, /* Early Command Training */
 284
 285         .UserBd = BOARD_TYPE_ULT_ULX,
 286
 287         .lp5x_config = {
 288                 .ccc_config = 0xff,
 289         },
 290 };
 291
 292 const struct mb_cfg *variant_memory_params(void)
 293 {
 294         int board_id = get_board_id();
 295
 296         switch (board_id) {
 297         case ADL_P_LP4_1:
 298         case ADL_P_LP4_2:
 299                 return &lpddr4_mem_config;
 300         case ADL_P_DDR4_1:
 301         case ADL_P_DDR4_2:
 302                 return &ddr4_mem_config;
 303         case ADL_P_DDR5_1:
 304         case ADL_P_DDR5_2:
 305                 return &ddr5_mem_config;
 306         case ADL_P_LP5_1:
 307         case ADL_P_LP5_2:
 308                 return &lp5_mem_config;
 309         case ADL_M_LP4:
 310                 return &adlm_lp4_mem_config;
 311         case ADL_M_LP5:
 312                 return &adlm_lp5_mem_config;
 313         default:
 314                 die("unsupported board id : 0x%x\n", board_id);
 315         }
 316 }