src/soc/amd/stoneyridge/bootblock/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2016 Intel Corporation..
   5  * Copyright (C) 2017 Advanced Micro Devices
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <assert.h>
  19 #include <console/console.h>
  20 #include <cpu/x86/msr.h>
  21 #include <cpu/x86/mtrr.h>
  22 #include <cpu/amd/amdfam15.h>
  23 #include <smp/node.h>
  24 #include <bootblock_common.h>
  25 #include <agesawrapper.h>
  26 #include <agesawrapper_call.h>
  27 #include <soc/pci_devs.h>
  28 #include <soc/northbridge.h>
  29 #include <soc/southbridge.h>
  30 #include <amdblocks/psp.h>
  31
  32 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
  33 {
  34         /*
  35          * Call lib/bootblock.c main with BSP, shortcut for APs
  36          *  todo: rearchitect AGESA entry points to remove need
  37          *        to run amdinitreset, amdinitearly from bootblock.
  38          *        Remove AP shortcut.
  39          */
  40         if (!boot_cpu())
  41                 bootblock_soc_early_init(); /* APs will not return */
  42
  43         bootblock_main_with_timestamp(base_timestamp);
  44 }
  45
  46 /* Set the MMIO Configuration Base Address and Bus Range. */
  47 static void amd_initmmio(void)
  48 {
  49         msr_t mmconf;
  50         msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
  51         int mtrr;
  52
  53         mmconf.hi = 0;
  54         mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
  55                         | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
  56         wrmsr(MMIO_CONF_BASE, mmconf);
  57
  58         /*
  59          * todo: AGESA currently writes variable MTRRs.  Once that is
  60          *       corrected, un-hardcode this MTRR.
  61          */
  62         mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
  63         set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
  64 }
  65
  66 void bootblock_soc_early_init(void)
  67 {
  68         amd_initmmio();
  69
  70         if (!boot_cpu())
  71                 bootblock_soc_init(); /* APs will not return */
  72
  73         bootblock_fch_early_init();
  74
  75         post_code(0x90);
  76         if (CONFIG_STONEYRIDGE_UART)
  77                 configure_stoneyridge_uart();
  78 }
  79
  80 /*
  81  * This step is in bootblock because the SMU FW1 must be loaded prior to
  82  * issuing any reset to the system.  Set up just enough to get the command
  83  * to the PSP.  A side effect of placing this step here is we will always
  84  * load a RO version of FW1 and never a RW version.
  85  *
  86  * todo: If AMD develops a more robust methodology, move this function to
  87  *       romstage.
  88  */
  89 static void load_smu_fw1(void)
  90 {
  91         u32 base, limit;
  92
  93         /* Open a posted hole from 0x80000000 : 0xfed00000-1 */
  94         base =  0x80000000;
  95         base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
  96         limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
  97         pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
  98         pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
  99
 100         /* Preload a value into "BAR3" and enable it */
 101         pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
 102         pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
 103
 104         psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
 105 }
 106
 107 void bootblock_soc_init(void)
 108 {
 109         if (IS_ENABLED(CONFIG_STONEYRIDGE_UART))
 110                 assert(CONFIG_UART_FOR_CONSOLE >= 0
 111                                         && CONFIG_UART_FOR_CONSOLE <= 1);
 112
 113         u32 val = cpuid_eax(1);
 114         printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
 115
 116         if (boot_cpu() && IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
 117                 load_smu_fw1();
 118
 119         post_code(0x37);
 120         AGESAWRAPPER(amdinitreset);
 121
 122         post_code(0x38);
 123         AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */
 124 }