src/mainboard/asrock/z97_extreme6/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/pnp_ops.h>
   4 #include <southbridge/intel/lynxpoint/pch.h>
   5 #include <superio/nuvoton/common/nuvoton.h>
   6 #include <superio/nuvoton/nct6791d/nct6791d.h>
   7
   8 #define GLOBAL_DEV      PNP_DEV(0x2e, 0)
   9 #define SERIAL_DEV      PNP_DEV(0x2e, NCT6791D_SP1)
  10 #define ACPI_DEV        PNP_DEV(0x2e, NCT6791D_ACPI)
  11 #define GPIO_PP_OD_DEV  PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD)
  12
  13 /*
  14  * Asrock Z97 Extreme6 Super I/O GPIOs
  15  *
  16  * +------+-----+---------------------------+
  17  * | GPIO | Pin | Description               |
  18  * +------+-----+---------------------------+
  19  * | GP00 | 121 | N/C                       |
  20  * | GP01 | 122 | CHA_FAN2 PWM output       |
  21  * | GP02 | 123 | CHA_FAN3 PWM output       |
  22  * | GP03 |   2 | N/C                       |
  23  * | GP04 |   3 | CHA_FAN3 tach input       |
  24  * | GP05 |   4 | CHA_FAN2 tach input       |
  25  * | GP06 |   5 | PWR_FAN  tach input       |
  26  * | GP07 |   6 | N/C            (SE_IFDET) |
  27  * +------+-----+---------------------------+
  28  * | GP10 |  14 | HDD Saver power switch    |
  29  * | GP11 |  13 | Assert HDA_SDO (SIO_GP11) |
  30  * | GP12 |  12 | CPU_FAN2 FON#             |
  31  * | GP13 |  11 | SATA_SEL (for eSATA)      |
  32  * | GP14 |  10 | N/C                       |
  33  * | GP15 |   9 | N/C          (UARTP80_EN) |
  34  * | GP16 |   8 | OTP for VCORE (OTE_GATE1) |
  35  * | GP17 |   7 | LED_EN#                   |
  36  * +------+-----+---------------------------+
  37  * | GP20 |  59 | KDAT                      |
  38  * | GP21 |  58 | KCLK                      |
  39  * | GP22 |  57 | MDAT                      |
  40  * | GP23 |  56 | MCLK                      |
  41  * | GP24 |  95 | SE_DEVSLP (SATA Express)  |
  42  * | GP25 |  96 | N/C            (SIO_GP25) |
  43  * | GP26 |  53 | N/C                       |
  44  * | GP27 |  98 | M2_2_SE_IFDET             |
  45  * +------+-----+---------------------------+
  46  * | GP30 |  83 | N/C           (RESETCON#) |
  47  * | GP31 |  76 | BIOS_A (or SML1DAT)       |
  48  * | GP32 |  75 | BIOS_B (or SML1CLK)       |
  49  * | GP33 |  71 | 3VSBSW#                   |
  50  * | GP34 |  55 | VCORE_OFFSET#             |
  51  * | GP35 |  54 | N/C                       |
  52  * | GP36 |  53 | N/C                       |
  53  * | GP37 |   7 | LED_EN#                   |
  54  * +------+-----+---------------------------+
  55  * | GP40 |  62 | N/C             (TEST_EN) |
  56  * | GP41 |  52 | N/C                       |
  57  * | GP42 |  51 | WLAN1_ON/OFF#             |
  58  * | GP43 |  41 | Port 80 display - DGL_0#  |
  59  * | GP44 |  40 | PWR_LED gate              |
  60  * | GP45 |  39 | HDD_LED gate              |
  61  * | GP46 |  38 | CHA_FAN3 FON#             |
  62  * | GP47 |  37 | CHA_FAN2 FON#             |
  63  * +------+-----+---------------------------+
  64  * | GP50 |  93 | N/C            (SUSWARN#) |
  65  * | GP51 |  92 | CPU_FAN2 tach input       |
  66  * | GP52 |  91 | N/C             (SUSACK#) |
  67  * | GP53 |  90 | SUSWARN_5VDUAL            |
  68  * | GP54 |  89 | SLP_SUS#                  |
  69  * | GP55 |  88 | SLP_SUS_FET               |
  70  * | GP56 |  87 | PEG12V_DET (Molex conn)   |
  71  * | GP57 |  86 | PCIE4_SEL (PCIE3 / mPCIe) |
  72  * +------+-----+---------------------------+
  73  * | GP70 |  69 | N/C              (DSW_EN) |
  74  * | GP71 |  68 | N/C                       |
  75  * | GP72 |  67 | N/C                       |
  76  * | GP73 |  66 | M.2 / SATA Express select |
  77  * | GP74 |  79 | RESET# of long PCIe ports |
  78  * | GP75 |  78 | RESET# for on-board chips |
  79  * | GP76 |  77 | RESET# SATA Express / M.2 |
  80  * | GP77 |  86 | HDD_LED gate              |
  81  * +------+-----+---------------------------+
  82  *
  83  * HWM voltage inputs
  84  *
  85  * +------+-----+---------------------------+
  86  * | Name | Pin | Voltage (resistor values) |
  87  * +------+-----+---------------------------+
  88  * | VIN0 | 104 | +12V         (110K / 10K) |
  89  * | VIN1 | 105 | +5V           (20K / 10K) |
  90  * | VIN2 | 106 | CPU_VRING                 |
  91  * | VIN3 | 107 | CPU_VSA                   |
  92  * | VIN4 | 111 | CPU_VCORE0                |
  93  * | VIN5 | 114 | CPU_VGFX                  |
  94  * | VIN6 | 115 | V_VCCIOA_LOAD             |
  95  * | VIN7 | 116 | N/C                       |
  96  * | VIN8 | 103 | CPU_VIO                   |
  97  * +------+-----+---------------------------+
  98  */
  99
 100 void mainboard_config_superio(void)
 101 {
 102         nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
 103
 104         /* Select SIO pin mux states */
 105         pnp_write_config(GLOBAL_DEV, 0x1b, 0xe6);
 106         pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
 107         pnp_write_config(GLOBAL_DEV, 0x24, 0xfc);
 108         pnp_write_config(GLOBAL_DEV, 0x2a, 0x40);
 109         pnp_write_config(GLOBAL_DEV, 0x2b, 0x20);
 110         pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
 111         pnp_write_config(GLOBAL_DEV, 0x2d, 0x02);
 112
 113         /* Select push-pull vs. open-drain output */
 114         pnp_set_logical_device(GPIO_PP_OD_DEV);
 115         pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe);
 116         pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x79);
 117         pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x6f);
 118
 119         /* Power RAM in S3 */
 120         pnp_set_logical_device(ACPI_DEV);
 121         pnp_write_config(ACPI_DEV, 0xe4, 0x10);
 122
 123         nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
 124
 125         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 126 }