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northbridge/intel: Remove unneeded includes
[coreboot.git] / src / northbridge / intel / sandybridge / northbridge.c
blob8c2aaf34e71c644eec0fe93a99b5bc8cfcc9bf03
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <console/console.h>
18 #include <arch/acpi.h>
19 #include <arch/io.h>
20 #include <stdint.h>
21 #include <delay.h>
22 #include <cpu/intel/model_206ax/model_206ax.h>
23 #include <cpu/x86/msr.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
27 #include <stdlib.h>
28 #include <string.h>
29 #include <cpu/cpu.h>
30 #include <cbmem.h>
31 #include "chip.h"
32 #include "sandybridge.h"
33 #include <cpu/intel/smm/gen1/smi.h>
34
35 static int bridge_revision_id = -1;
36
37 /* IGD UMA memory */
38 static uint64_t uma_memory_base = 0;
39 static uint64_t uma_memory_size = 0;
40
41 int bridge_silicon_revision(void)
42 {
43 if (bridge_revision_id < 0) {
44 uint8_t stepping = cpuid_eax(1) & 0xf;
45 uint8_t bridge_id = pci_read_config16(
46 dev_find_slot(0, PCI_DEVFN(0, 0)),
47 PCI_DEVICE_ID) & 0xf0;
48 bridge_revision_id = bridge_id | stepping;
49 }
50 return bridge_revision_id;
51 }
52
53 /* Reserve everything between A segment and 1MB:
54 *
55 * 0xa0000 - 0xbffff: legacy VGA
56 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
57 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
58 */
59 static const int legacy_hole_base_k = 0xa0000 / 1024;
60 static const int legacy_hole_size_k = 384;
61
62 static int get_pcie_bar(u32 *base)
63 {
64 struct device *dev;
65 u32 pciexbar_reg;
66
67 *base = 0;
68
69 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
70 if (!dev)
71 return 0;
72
73 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
74
75 if (!(pciexbar_reg & (1 << 0)))
76 return 0;
77
78 switch ((pciexbar_reg >> 1) & 3) {
79 case 0: // 256MB
80 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
81 return 256;
82 case 1: // 128M
83 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
84 return 128;
85 case 2: // 64M
86 *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
87 return 64;
88 }
89
90 return 0;
91 }
92
93 static void add_fixed_resources(struct device *dev, int index)
94 {
95 mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
96
97 mmio_resource(dev, index++, legacy_hole_base_k,
98 (0xc0000 >> 10) - legacy_hole_base_k);
99 reserved_ram_resource(dev, index++, 0xc0000 >> 10,
100 (0x100000 - 0xc0000) >> 10);
101
102 #if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
103 reserved_ram_resource(dev, index++,
104 CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
105 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
106 #endif
107
108 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
109 /* Required for SandyBridge sighting 3715511 */
110 bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
111 bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
112 }
113
114 /* Reserve IOMMU BARs */
115 const u32 capid0_a = pci_read_config32(dev, 0xe4);
116 if (!(capid0_a & (1 << 23))) {
117 mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4);
118 mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4);
119 }
120 }
121
122 static void pci_domain_set_resources(struct device *dev)
123 {
124 uint64_t tom, me_base, touud;
125 uint32_t tseg_base, uma_size, tolud;
126 uint16_t ggc;
127 unsigned long long tomk;
128
129 /* Total Memory 2GB example:
130 *
131 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
132 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
133 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
134 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
135 * 7f200000 2034MB TOLUD
136 * 7f800000 2040MB MEBASE
137 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
138 * 80000000 2048MB TOM
139 * 100000000 4096MB-4102MB 6MB RAM (writeback)
140 *
141 * Total Memory 4GB example:
142 *
143 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
144 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
145 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
146 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
147 * afa00000 2810MB TOLUD
148 * ff800000 4088MB MEBASE
149 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
150 * 100000000 4096MB TOM
151 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
152 * 14fe00000 5368MB TOUUD
153 */
154
155 /* Top of Upper Usable DRAM, including remap */
156 touud = pci_read_config32(dev, TOUUD+4);
157 touud <<= 32;
158 touud |= pci_read_config32(dev, TOUUD);
159
160 /* Top of Lower Usable DRAM */
161 tolud = pci_read_config32(dev, TOLUD);
162
163 /* Top of Memory - does not account for any UMA */
164 tom = pci_read_config32(dev, 0xa4);
165 tom <<= 32;
166 tom |= pci_read_config32(dev, 0xa0);
167
168 printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
169 touud, tolud, tom);
170
171 /* ME UMA needs excluding if total memory <4GB */
172 me_base = pci_read_config32(dev, 0x74);
173 me_base <<= 32;
174 me_base |= pci_read_config32(dev, 0x70);
175
176 printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);
177
178 uma_memory_base = tolud;
179 tomk = tolud >> 10;
180 if (me_base == tolud) {
181 /* ME is from MEBASE-TOM */
182 uma_size = (tom - me_base) >> 10;
183 /* Increment TOLUD to account for ME as RAM */
184 tolud += uma_size << 10;
185 /* UMA starts at old TOLUD */
186 uma_memory_base = tomk * 1024ULL;
187 uma_memory_size = uma_size * 1024ULL;
188 printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
189 me_base, uma_size >> 10);
190 }
191
192 /* Graphics memory comes next */
193 ggc = pci_read_config16(dev, GGC);
194 if (!(ggc & 2)) {
195 printk(BIOS_DEBUG, "IGD decoded, subtracting ");
196
197 /* Graphics memory */
198 uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
199 printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10);
200 tomk -= uma_size;
201 uma_memory_base = tomk * 1024ULL;
202 uma_memory_size += uma_size * 1024ULL;
203
204 /* GTT Graphics Stolen Memory Size (GGMS) */
205 uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
206 tomk -= uma_size;
207 uma_memory_base = tomk * 1024ULL;
208 uma_memory_size += uma_size * 1024ULL;
209 printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10);
210 }
211
212 /* Calculate TSEG size from its base which must be below GTT */
213 tseg_base = pci_read_config32(dev, 0xb8);
214 uma_size = (uma_memory_base - tseg_base) >> 10;
215 tomk -= uma_size;
216 uma_memory_base = tomk * 1024ULL;
217 uma_memory_size += uma_size * 1024ULL;
218 printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n",
219 tseg_base, uma_size >> 10);
220
221 printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
222
223 /* Report the memory regions */
224 ram_resource(dev, 3, 0, legacy_hole_base_k);
225 ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
226 (tomk - (legacy_hole_base_k + legacy_hole_size_k)));
227
228 /*
229 * If >= 4GB installed then memory from TOLUD to 4GB
230 * is remapped above TOM, TOUUD will account for both
231 */
232 touud >>= 10; /* Convert to KB */
233 if (touud > 4096 * 1024) {
234 ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
235 printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
236 (touud >> 10) - 4096);
237 }
238
239 add_fixed_resources(dev, 6);
240
241 assign_resources(dev->link_list);
242 }
243
244 static const char *northbridge_acpi_name(const struct device *dev)
245 {
246 if (dev->path.type == DEVICE_PATH_DOMAIN)
247 return "PCI0";
248
249 if (dev->path.type != DEVICE_PATH_PCI)
250 return NULL;
251
252 switch (dev->path.pci.devfn) {
253 case PCI_DEVFN(0, 0):
254 return "MCHC";
255 }
256
257 return NULL;
258 }
259
260 /* TODO We could determine how many PCIe busses we need in
261 * the bar. For now that number is hardcoded to a max of 64.
262 * See e7525/northbridge.c for an example.
263 */
264 static struct device_operations pci_domain_ops = {
265 .read_resources = pci_domain_read_resources,
266 .set_resources = pci_domain_set_resources,
267 .enable_resources = NULL,
268 .init = NULL,
269 .scan_bus = pci_domain_scan_bus,
270 .write_acpi_tables = northbridge_write_acpi_tables,
271 .acpi_name = northbridge_acpi_name,
272 };
273
274 static void mc_read_resources(struct device *dev)
275 {
276 u32 pcie_config_base;
277 int buses;
278
279 pci_dev_read_resources(dev);
280
281 buses = get_pcie_bar(&pcie_config_base);
282 if (buses) {
283 struct resource *resource = new_resource(dev, PCIEXBAR);
284 mmconf_resource_init(resource, pcie_config_base, buses);
285 }
286 }
287
288 static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
289 {
290 if (!vendor || !device) {
291 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
292 pci_read_config32(dev, PCI_VENDOR_ID));
293 } else {
294 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
295 ((device & 0xffff) << 16) | (vendor & 0xffff));
296 }
297 }
298
299 static void northbridge_dmi_init(struct device *dev)
300 {
301 u32 reg32;
302
303 /* Clear error status bits */
304 DMIBAR32(0x1c4) = 0xffffffff;
305 DMIBAR32(0x1d0) = 0xffffffff;
306
307 /* Steps prior to DMI ASPM */
308 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
309 reg32 = DMIBAR32(0x250);
310 reg32 &= ~((1 << 22)|(1 << 20));
311 reg32 |= (1 << 21);
312 DMIBAR32(0x250) = reg32;
313 }
314
315 reg32 = DMIBAR32(0x238);
316 reg32 |= (1 << 29);
317 DMIBAR32(0x238) = reg32;
318
319 if (bridge_silicon_revision() >= SNB_STEP_D0) {
320 reg32 = DMIBAR32(0x1f8);
321 reg32 |= (1 << 16);
322 DMIBAR32(0x1f8) = reg32;
323 } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
324 reg32 = DMIBAR32(0x1f8);
325 reg32 &= ~(1 << 26);
326 reg32 |= (1 << 16);
327 DMIBAR32(0x1f8) = reg32;
328
329 reg32 = DMIBAR32(0x1fc);
330 reg32 |= (1 << 12) | (1 << 23);
331 DMIBAR32(0x1fc) = reg32;
332 }
333
334 /* Enable ASPM on SNB link, should happen before PCH link */
335 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
336 reg32 = DMIBAR32(0xd04);
337 reg32 |= (1 << 4);
338 DMIBAR32(0xd04) = reg32;
339 }
340
341 reg32 = DMIBAR32(0x88);
342 reg32 |= (1 << 1) | (1 << 0);
343 DMIBAR32(0x88) = reg32;
344 }
345
346 /* Disable unused PEG devices based on devicetree */
347 static void disable_peg(void)
348 {
349 struct device *dev;
350 u32 reg;
351
352 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
353 reg = pci_read_config32(dev, DEVEN);
354
355 dev = dev_find_slot(0, PCI_DEVFN(1, 2));
356 if (!dev || !dev->enabled) {
357 printk(BIOS_DEBUG, "Disabling PEG12.\n");
358 reg &= ~DEVEN_PEG12;
359 }
360 dev = dev_find_slot(0, PCI_DEVFN(1, 1));
361 if (!dev || !dev->enabled) {
362 printk(BIOS_DEBUG, "Disabling PEG11.\n");
363 reg &= ~DEVEN_PEG11;
364 }
365 dev = dev_find_slot(0, PCI_DEVFN(1, 0));
366 if (!dev || !dev->enabled) {
367 printk(BIOS_DEBUG, "Disabling PEG10.\n");
368 reg &= ~DEVEN_PEG10;
369 }
370 dev = dev_find_slot(0, PCI_DEVFN(2, 0));
371 if (!dev || !dev->enabled) {
372 printk(BIOS_DEBUG, "Disabling IGD.\n");
373 reg &= ~DEVEN_IGD;
374 }
375 dev = dev_find_slot(0, PCI_DEVFN(4, 0));
376 if (!dev || !dev->enabled) {
377 printk(BIOS_DEBUG, "Disabling Device 4.\n");
378 reg &= ~DEVEN_D4EN;
379 }
380 dev = dev_find_slot(0, PCI_DEVFN(6, 0));
381 if (!dev || !dev->enabled) {
382 printk(BIOS_DEBUG, "Disabling PEG60.\n");
383 reg &= ~DEVEN_PEG60;
384 }
385 dev = dev_find_slot(0, PCI_DEVFN(7, 0));
386 if (!dev || !dev->enabled) {
387 printk(BIOS_DEBUG, "Disabling Device 7.\n");
388 reg &= ~DEVEN_D7EN;
389 }
390
391 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
392 pci_write_config32(dev, DEVEN, reg);
393 if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) {
394 /* Set the PEG clock gating bit.
395 * Disables the IO clock on all PEG devices. */
396 MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
397 printk(BIOS_DEBUG, "Disabling PEG IO clock.\n");
398 }
399 }
400
401 static void northbridge_init(struct device *dev)
402 {
403 u8 bios_reset_cpl;
404 u32 bridge_type;
405
406 northbridge_dmi_init(dev);
407
408 bridge_type = MCHBAR32(0x5f10);
409 bridge_type &= ~0xff;
410
411 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
412 /* Enable Power Aware Interrupt Routing */
413 u8 pair = MCHBAR8(0x5418);
414 pair &= ~0xf; /* Clear 3:0 */
415 pair |= 0x4; /* Fixed Priority */
416 MCHBAR8(0x5418) = pair;
417
418 /* 30h for IvyBridge */
419 bridge_type |= 0x30;
420 } else {
421 /* 20h for Sandybridge */
422 bridge_type |= 0x20;
423 }
424 MCHBAR32(0x5f10) = bridge_type;
425
426 /* Turn off unused devices. Has to be done before
427 * setting BIOS_RESET_CPL.
428 */
429 disable_peg();
430
431 /*
432 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
433 * that BIOS has initialized memory and power management
434 */
435 bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
436 bios_reset_cpl |= 1;
437 MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
438 printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
439
440 /* Configure turbo power limits 1ms after reset complete bit */
441 mdelay(1);
442 set_power_limits(28);
443
444 /*
445 * CPUs with configurable TDP also need power limits set
446 * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
447 */
448 if (cpu_config_tdp_levels()) {
449 msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT);
450 MCHBAR32(0x59A0) = msr.lo;
451 MCHBAR32(0x59A4) = msr.hi;
452 }
453
454 /* Set here before graphics PM init */
455 MCHBAR32(0x5500) = 0x00100001;
456 }
457
458 static u32 northbridge_get_base_reg(struct device *dev, int reg)
459 {
460 u32 value;
461
462 value = pci_read_config32(dev, reg);
463 /* Base registers are at 1MiB granularity. */
464 value &= ~((1 << 20) - 1);
465 return value;
466 }
467
468 u32 northbridge_get_tseg_base(void)
469 {
470 struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
471
472 return northbridge_get_base_reg(dev, TSEG);
473 }
474
475 void northbridge_write_smram(u8 smram)
476 {
477 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);
478 }
479
480 static struct pci_operations intel_pci_ops = {
481 .set_subsystem = intel_set_subsystem,
482 };
483
484 static struct device_operations mc_ops = {
485 .read_resources = mc_read_resources,
486 .set_resources = pci_dev_set_resources,
487 .enable_resources = pci_dev_enable_resources,
488 .init = northbridge_init,
489 .scan_bus = 0,
490 .ops_pci = &intel_pci_ops,
491 .acpi_fill_ssdt_generator = generate_cpu_entries,
492 };
493
494 static const struct pci_driver mc_driver_0100 __pci_driver = {
495 .ops = &mc_ops,
496 .vendor = PCI_VENDOR_ID_INTEL,
497 .device = 0x0100,
498 };
499
500 static const struct pci_driver mc_driver __pci_driver = {
501 .ops = &mc_ops,
502 .vendor = PCI_VENDOR_ID_INTEL,
503 .device = 0x0104, /* Sandy bridge */
504 };
505
506 static const struct pci_driver mc_driver_150 __pci_driver = {
507 .ops = &mc_ops,
508 .vendor = PCI_VENDOR_ID_INTEL,
509 .device = 0x0150, /* Ivy bridge */
510 };
511
512 static const struct pci_driver mc_driver_1 __pci_driver = {
513 .ops = &mc_ops,
514 .vendor = PCI_VENDOR_ID_INTEL,
515 .device = 0x0154, /* Ivy bridge */
516 };
517
518 static const struct pci_driver mc_driver_158 __pci_driver = {
519 .ops = &mc_ops,
520 .vendor = PCI_VENDOR_ID_INTEL,
521 .device = 0x0158, /* Ivy bridge */
522 };
523
524 static void cpu_bus_init(struct device *dev)
525 {
526 initialize_cpus(dev->link_list);
527 }
528
529 static struct device_operations cpu_bus_ops = {
530 .read_resources = DEVICE_NOOP,
531 .set_resources = DEVICE_NOOP,
532 .enable_resources = DEVICE_NOOP,
533 .init = cpu_bus_init,
534 .scan_bus = 0,
535 };
536
537 static void enable_dev(struct device *dev)
538 {
539 /* Set the operations if it is a special bus type */
540 if (dev->path.type == DEVICE_PATH_DOMAIN) {
541 dev->ops = &pci_domain_ops;
542 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
543 dev->ops = &cpu_bus_ops;
544 }
545 }
546
547 struct chip_operations northbridge_intel_sandybridge_ops = {
548 CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge")
549 .enable_dev = enable_dev,
550 };
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