src/northbridge/intel/haswell/northbridge.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <arch/acpi.h>
  19 #include <arch/io.h>
  20 #include <stdint.h>
  21 #include <delay.h>
  22 #include <cpu/intel/haswell/haswell.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <stdlib.h>
  27 #include <string.h>
  28 #include <cpu/cpu.h>
  29 #include <cpu/x86/smm.h>
  30 #include <boot/tables.h>
  31 #include <cbmem.h>
  32 #include "chip.h"
  33 #include "haswell.h"
  34
  35 static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base,
  36                         u32 *len)
  37 {
  38         u32 pciexbar_reg;
  39         u32 mask;
  40
  41         *base = 0;
  42         *len = 0;
  43
  44         pciexbar_reg = pci_read_config32(dev, index);
  45
  46         if (!(pciexbar_reg & (1 << 0)))
  47                 return 0;
  48
  49         switch ((pciexbar_reg >> 1) & 3) {
  50         case 0: // 256MB
  51                 mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
  52                 *base = pciexbar_reg & mask;
  53                 *len = 256 * 1024 * 1024;
  54                 return 1;
  55         case 1: // 128M
  56                 mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
  57                 mask |= (1 << 27);
  58                 *base = pciexbar_reg & mask;
  59                 *len = 128 * 1024 * 1024;
  60                 return 1;
  61         case 2: // 64M
  62                 mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28);
  63                 mask |= (1 << 27) | (1 << 26);
  64                 *base = pciexbar_reg & mask;
  65                 *len = 64 * 1024 * 1024;
  66                 return 1;
  67         }
  68
  69         return 0;
  70 }
  71
  72 static void pci_domain_set_resources(struct device *dev)
  73 {
  74         assign_resources(dev->link_list);
  75 }
  76
  77         /* TODO We could determine how many PCIe busses we need in
  78          * the bar. For now that number is hardcoded to a max of 64.
  79          * See e7525/northbridge.c for an example.
  80          */
  81 static struct device_operations pci_domain_ops = {
  82         .read_resources   = pci_domain_read_resources,
  83         .set_resources    = pci_domain_set_resources,
  84         .enable_resources = NULL,
  85         .init             = NULL,
  86         .scan_bus         = pci_domain_scan_bus,
  87         .write_acpi_tables = northbridge_write_acpi_tables,
  88 };
  89
  90 static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
  91 {
  92         u32 bar;
  93
  94         bar = pci_read_config32(dev, index);
  95
  96         /* If not enabled don't report it. */
  97         if (!(bar & 0x1))
  98                 return 0;
  99
 100         /* Knock down the enable bit. */
 101         *base = bar & ~1;
 102
 103         return 1;
 104 }
 105
 106 /* There are special BARs that actually are programmed in the MCHBAR. These
 107  * Intel special features, but they do consume resources that need to be
 108  * accounted for. */
 109 static int get_bar_in_mchbar(struct device *dev, unsigned int index,
 110                              u32 *base, u32 *len)
 111 {
 112         u32 bar;
 113
 114         bar = MCHBAR32(index);
 115
 116         /* If not enabled don't report it. */
 117         if (!(bar & 0x1))
 118                 return 0;
 119
 120         /* Knock down the enable bit. */
 121         *base = bar & ~1;
 122
 123         return 1;
 124 }
 125
 126 struct fixed_mmio_descriptor {
 127         unsigned int index;
 128         u32 size;
 129         int (*get_resource)(struct device *dev, unsigned int index,
 130                             u32 *base, u32 *size);
 131         const char *description;
 132 };
 133
 134 #define SIZE_KB(x) ((x)*1024)
 135 struct fixed_mmio_descriptor mc_fixed_resources[] = {
 136         { PCIEXBAR, SIZE_KB(0),  get_pcie_bar,      "PCIEXBAR" },
 137         { MCHBAR,   SIZE_KB(32), get_bar,           "MCHBAR"   },
 138         { DMIBAR,   SIZE_KB(4),  get_bar,           "DMIBAR"   },
 139         { EPBAR,    SIZE_KB(4),  get_bar,           "EPBAR"    },
 140         { 0x5420,   SIZE_KB(4),  get_bar_in_mchbar, "GDXCBAR"  },
 141         { 0x5408,   SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" },
 142 };
 143 #undef SIZE_KB
 144
 145 /*
 146  * Add all known fixed MMIO ranges that hang off the host bridge/memory
 147  * controller device.
 148  */
 149 static void mc_add_fixed_mmio_resources(struct device *dev)
 150 {
 151         int i;
 152
 153         for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) {
 154                 u32 base;
 155                 u32 size;
 156                 struct resource *resource;
 157                 unsigned int index;
 158
 159                 size = mc_fixed_resources[i].size;
 160                 index = mc_fixed_resources[i].index;
 161                 if (!mc_fixed_resources[i].get_resource(dev, index,
 162                                                         &base, &size))
 163                         continue;
 164
 165                 resource = new_resource(dev, mc_fixed_resources[i].index);
 166                 resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 167                                   IORESOURCE_STORED | IORESOURCE_RESERVE |
 168                                   IORESOURCE_ASSIGNED;
 169                 resource->base = base;
 170                 resource->size = size;
 171                 printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
 172                        __func__, mc_fixed_resources[i].description, index,
 173                        (unsigned long)base, (unsigned long)(base + size - 1));
 174         }
 175 }
 176
 177 /* Host Memory Map:
 178  *
 179  * +--------------------------+ TOUUD
 180  * |                          |
 181  * +--------------------------+ 4GiB
 182  * |     PCI Address Space    |
 183  * +--------------------------+ TOLUD (also maps into MC address space)
 184  * |     iGD                  |
 185  * +--------------------------+ BDSM
 186  * |     GTT                  |
 187  * +--------------------------+ BGSM
 188  * |     TSEG                 |
 189  * +--------------------------+ TSEGMB
 190  * |     Usage DRAM           |
 191  * +--------------------------+ 0
 192  *
 193  * Some of the base registers above can be equal making the size of those
 194  * regions 0. The reason is because the memory controller internally subtracts
 195  * the base registers from each other to determine sizes of the regions. In
 196  * other words, the memory map is in a fixed order no matter what.
 197  */
 198
 199 struct map_entry {
 200         int reg;
 201         int is_64_bit;
 202         int is_limit;
 203         const char *description;
 204 };
 205
 206 static void read_map_entry(struct device *dev, struct map_entry *entry,
 207                            uint64_t *result)
 208 {
 209         uint64_t value;
 210         uint64_t mask;
 211
 212         /* All registers are on a 1MiB granularity. */
 213         mask = ((1ULL<<20)-1);
 214         mask = ~mask;
 215
 216         value = 0;
 217
 218         if (entry->is_64_bit) {
 219                 value = pci_read_config32(dev, entry->reg + 4);
 220                 value <<= 32;
 221         }
 222
 223         value |= pci_read_config32(dev, entry->reg);
 224         value &= mask;
 225
 226         if (entry->is_limit)
 227                 value |= ~mask;
 228
 229         *result = value;
 230 }
 231
 232 #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \
 233         { \
 234                 .reg = reg_,           \
 235                 .is_64_bit = is_64_,   \
 236                 .is_limit = is_limit_, \
 237                 .description = desc_,  \
 238         }
 239
 240 #define MAP_ENTRY_BASE_64(reg_, desc_) \
 241         MAP_ENTRY(reg_, 1, 0, desc_)
 242 #define MAP_ENTRY_LIMIT_64(reg_, desc_) \
 243         MAP_ENTRY(reg_, 1, 1, desc_)
 244 #define MAP_ENTRY_BASE_32(reg_, desc_) \
 245         MAP_ENTRY(reg_, 0, 0, desc_)
 246
 247 enum {
 248         TOM_REG,
 249         TOUUD_REG,
 250         MESEG_BASE_REG,
 251         MESEG_LIMIT_REG,
 252         REMAP_BASE_REG,
 253         REMAP_LIMIT_REG,
 254         TOLUD_REG,
 255         BGSM_REG,
 256         BDSM_REG,
 257         TSEG_REG,
 258         // Must be last.
 259         NUM_MAP_ENTRIES
 260 };
 261
 262 static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
 263         [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"),
 264         [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"),
 265         [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"),
 266         [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"),
 267         [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"),
 268         [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"),
 269         [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"),
 270         [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"),
 271         [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"),
 272         [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"),
 273 };
 274
 275 static void mc_read_map_entries(struct device *dev, uint64_t *values)
 276 {
 277         int i;
 278         for (i = 0; i < NUM_MAP_ENTRIES; i++) {
 279                 read_map_entry(dev, &memory_map[i], &values[i]);
 280         }
 281 }
 282
 283 static void mc_report_map_entries(struct device *dev, uint64_t *values)
 284 {
 285         int i;
 286         for (i = 0; i < NUM_MAP_ENTRIES; i++) {
 287                 printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n",
 288                        memory_map[i].description, values[i]);
 289         }
 290         /* One can validate the BDSM and BGSM against the GGC. */
 291         printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
 292 }
 293
 294 static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
 295 {
 296         unsigned long base_k, size_k;
 297         unsigned long touud_k;
 298         unsigned long index;
 299         struct resource *resource;
 300         uint64_t mc_values[NUM_MAP_ENTRIES];
 301
 302         /* Read in the MAP registers and report their values. */
 303         mc_read_map_entries(dev, &mc_values[0]);
 304         mc_report_map_entries(dev, &mc_values[0]);
 305
 306         /*
 307          * These are the host memory ranges that should be added:
 308          * - 0 -> 0xa0000: cacheable
 309          * - 0xc0000 -> TSEG : cacheable
 310          * - TESG -> BGSM: cacheable with standard MTRRs and reserved
 311          * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
 312          * - 4GiB -> TOUUD: cacheable
 313          *
 314          * The default SMRAM space is reserved so that the range doesn't
 315          * have to be saved during S3 Resume. Once marked reserved the OS
 316          * cannot use the memory. This is a bit of an odd place to reserve
 317          * the region, but the CPU devices don't have dev_ops->read_resources()
 318          * called on them.
 319          *
 320          * The range 0xa0000 -> 0xc0000 does not have any resources
 321          * associated with it to handle legacy VGA memory. If this range
 322          * is not omitted the mtrr code will setup the area as cacheable
 323          * causing VGA access to not work.
 324          *
 325          * The TSEG region is mapped as cacheable so that one can perform
 326          * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
 327          * precedence over the existing MTRRs covering this region.
 328          *
 329          * It should be noted that cacheable entry types need to be added in
 330          * order. The reason is that the current MTRR code assumes this and
 331          * falls over itself if it isn't.
 332          *
 333          * The resource index starts low and should not meet or exceed
 334          * PCI_BASE_ADDRESS_0.
 335          */
 336         index = *resource_cnt;
 337
 338         /* 0 - > 0xa0000 */
 339         base_k = 0;
 340         size_k = (0xa0000 >> 10) - base_k;
 341         ram_resource(dev, index++, base_k, size_k);
 342
 343         /* 0xc0000 -> TSEG */
 344         base_k = 0xc0000 >> 10;
 345         size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
 346         ram_resource(dev, index++, base_k, size_k);
 347
 348         /* TSEG -> BGSM */
 349         resource = new_resource(dev, index++);
 350         resource->base = mc_values[TSEG_REG];
 351         resource->size = mc_values[BGSM_REG] - resource->base;
 352         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 353                           IORESOURCE_STORED | IORESOURCE_RESERVE |
 354                           IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
 355
 356         /* BGSM -> TOLUD */
 357         resource = new_resource(dev, index++);
 358         resource->base = mc_values[BGSM_REG];
 359         resource->size = mc_values[TOLUD_REG] - resource->base;
 360         resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
 361                           IORESOURCE_STORED | IORESOURCE_RESERVE |
 362                           IORESOURCE_ASSIGNED;
 363
 364         /* 4GiB -> TOUUD */
 365         base_k = 4096 * 1024; /* 4GiB */
 366         touud_k = mc_values[TOUUD_REG] >> 10;
 367         size_k = touud_k - base_k;
 368         if (touud_k > base_k)
 369                 ram_resource(dev, index++, base_k, size_k);
 370
 371         /* Reserve everything between A segment and 1MB:
 372          *
 373          * 0xa0000 - 0xbffff: legacy VGA
 374          * 0xc0000 - 0xfffff: RAM
 375          */
 376         mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
 377         reserved_ram_resource(dev, index++, (0xc0000 >> 10),
 378                               (0x100000 - 0xc0000) >> 10);
 379 #if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS)
 380         reserved_ram_resource(dev, index++,
 381                         CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
 382                         CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
 383 #endif
 384         *resource_cnt = index;
 385 }
 386
 387 static void mc_read_resources(struct device *dev)
 388 {
 389         int index = 0;
 390         const bool vtd_capable =
 391                 !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
 392
 393         /* Read standard PCI resources. */
 394         pci_dev_read_resources(dev);
 395
 396         /* Add all fixed MMIO resources. */
 397         mc_add_fixed_mmio_resources(dev);
 398
 399         /* Add VT-d MMIO resources if capable */
 400         if (vtd_capable) {
 401                 mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
 402                         GFXVT_BASE_SIZE / KiB);
 403                 mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
 404                         VTVC0_BASE_SIZE / KiB);
 405         }
 406
 407         /* Calculate and add DRAM resources. */
 408         mc_add_dram_resources(dev, &index);
 409 }
 410
 411 static void intel_set_subsystem(struct device *dev, unsigned vendor,
 412                                 unsigned device)
 413 {
 414         if (!vendor || !device) {
 415                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 416                                 pci_read_config32(dev, PCI_VENDOR_ID));
 417         } else {
 418                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
 419                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
 420         }
 421 }
 422
 423 static void northbridge_init(struct device *dev)
 424 {
 425         u8 bios_reset_cpl, pair;
 426
 427         /* Enable Power Aware Interrupt Routing */
 428         pair = MCHBAR8(0x5418);
 429         pair &= ~0x7;   /* Clear 2:0 */
 430         pair |= 0x4;    /* Fixed Priority */
 431         MCHBAR8(0x5418) = pair;
 432
 433         /*
 434          * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
 435          * that BIOS has initialized memory and power management
 436          */
 437         bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
 438         bios_reset_cpl |= 3;
 439         MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
 440         printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
 441
 442         /* Configure turbo power limits 1ms after reset complete bit */
 443         mdelay(1);
 444         set_power_limits(28);
 445
 446         /* Set here before graphics PM init */
 447         MCHBAR32(0x5500) = 0x00100001;
 448 }
 449
 450 static struct pci_operations intel_pci_ops = {
 451         .set_subsystem    = intel_set_subsystem,
 452 };
 453
 454 static struct device_operations mc_ops = {
 455         .read_resources   = mc_read_resources,
 456         .set_resources    = pci_dev_set_resources,
 457         .enable_resources = pci_dev_enable_resources,
 458         .init             = northbridge_init,
 459         .acpi_fill_ssdt_generator = generate_cpu_entries,
 460         .scan_bus         = 0,
 461         .ops_pci          = &intel_pci_ops,
 462 };
 463
 464 static const struct pci_driver mc_driver_hsw_mobile __pci_driver = {
 465         .ops    = &mc_ops,
 466         .vendor = PCI_VENDOR_ID_INTEL,
 467         .device = PCI_DEVICE_ID_HSW_MOBILE,
 468 };
 469
 470 static const struct pci_driver mc_driver_hsw_ult __pci_driver = {
 471         .ops    = &mc_ops,
 472         .vendor = PCI_VENDOR_ID_INTEL,
 473         .device = PCI_DEVICE_ID_HSW_ULT,
 474 };
 475
 476 static void cpu_bus_init(struct device *dev)
 477 {
 478         bsp_init_and_start_aps(dev->link_list);
 479 }
 480
 481 static struct device_operations cpu_bus_ops = {
 482         .read_resources   = DEVICE_NOOP,
 483         .set_resources    = DEVICE_NOOP,
 484         .enable_resources = DEVICE_NOOP,
 485         .init             = cpu_bus_init,
 486         .scan_bus         = 0,
 487 };
 488
 489 static void enable_dev(struct device *dev)
 490 {
 491         /* Set the operations if it is a special bus type */
 492         if (dev->path.type == DEVICE_PATH_DOMAIN) {
 493                 dev->ops = &pci_domain_ops;
 494         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 495                 dev->ops = &cpu_bus_ops;
 496         }
 497 }
 498
 499 struct chip_operations northbridge_intel_haswell_ops = {
 500         CHIP_NAME("Intel i7 (Haswell) integrated Northbridge")
 501         .enable_dev = enable_dev,
 502 };