src/soc/intel/common/block/include/intelblocks/cse.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2017 Intel Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef SOC_INTEL_COMMON_CSE_H
  18 #define SOC_INTEL_COMMON_CSE_H
  19
  20 #include <stdint.h>
  21
  22 /* MKHI Command groups */
  23 #define MKHI_GROUP_ID_CBM       0x0
  24 #define MKHI_GROUP_ID_HMRFPO    0x5
  25
  26 /* Global Reset Command ID */
  27 #define MKHI_CBM_GLOBAL_RESET_REQ       0xb
  28
  29 /* Origin of Global Reset command */
  30 #define GR_ORIGIN_BIOS_POST     0x2
  31
  32 /* HMRFPO Command Ids */
  33 #define MKHI_HMRFPO_ENABLE      0x1
  34 #define MKHI_HMRFPO_GET_STATUS  0x3
  35
  36 /* ME Current Working States */
  37 #define ME_HFS1_CWS_NORMAL      0x5
  38
  39 /* ME Current Operation Modes */
  40 #define ME_HFS1_COM_NORMAL      0x0
  41 #define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3
  42 #define ME_HFS1_COM_SECOVER_MEI_MSG     0x5
  43
  44 /* HFSTS register offsets in PCI config space */
  45 enum {
  46         PCI_ME_HFSTS1 = 0x40,
  47         PCI_ME_HFSTS2 = 0x48,
  48         PCI_ME_HFSTS3 = 0x60,
  49         PCI_ME_HFSTS4 = 0x64,
  50         PCI_ME_HFSTS5 = 0x68,
  51         PCI_ME_HFSTS6 = 0x6C,
  52 };
  53
  54 /* MKHI Message Header */
  55 struct mkhi_hdr {
  56         uint8_t group_id;
  57         uint8_t command:7;
  58         uint8_t is_resp:1;
  59         uint8_t rsvd;
  60         uint8_t result;
  61 } __packed;
  62
  63 /* set up device for use in early boot enviroument with temp bar */
  64 void heci_init(uintptr_t bar);
  65 /*
  66  * Receive message into buff not exceeding maxlen. Message is considered
  67  * successfully received if a 'complete' indication is read from ME side
  68  * and there was enough space in the buffer to fit that message. maxlen
  69  * is updated with size of message that was received. Returns 0 on failure
  70  * and 1 on success.
  71  * In case of error heci_reset() may be requiered.
  72  */
  73 int heci_receive(void *buff, size_t *maxlen);
  74 /*
  75  * Send message msg of size len to host from host_addr to cse_addr.
  76  * Returns 1 on success and 0 otherwise.
  77  * In case of error heci_reset() may be requiered.
  78  */
  79 int
  80 heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
  81
  82 /*
  83  * Sends snd_msg of size snd_sz, and reads message into buffer pointed by
  84  * rcv_msg of size rcv_sz
  85  * Returns 0 on failure and 1 on success.
  86  */
  87 int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz);
  88
  89 /*
  90  * Attempt device reset. This is useful and perhaps only thing left to do when
  91  * CPU and CSE are out of sync or CSE fails to respond.
  92  * Returns 0 on failure and 1 on success.
  93  */
  94 int heci_reset(void);
  95
  96 /* Reads config value from a specified offset in the CSE PCI Config space. */
  97 uint32_t me_read_config32(int offset);
  98
  99 /*
 100  * Check if the CSE device is enabled in device tree. Also check if the device
 101  * is visible on the PCI bus by reading config space.
 102  * Return true if device present and config space enabled, else return false.
 103  */
 104 bool is_cse_enabled(void);
 105
 106 /* Makes the host ready to communicate with CSE */
 107 void cse_set_host_ready(void);
 108
 109 /*
 110  * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
 111  * Returns 0 on failure and 1 on success.
 112  */
 113 uint8_t cse_wait_sec_override_mode(void);
 114
 115 enum rst_req_type {
 116         GLOBAL_RESET = 1,
 117         HOST_RESET_ONLY = 2,
 118         CSE_RESET_ONLY = 3,
 119 };
 120
 121 /*
 122  * Sends GLOBAL_RESET_REQ cmd to CSE.
 123  * The reset type can be one of the above defined reset type.
 124  * Returns 0 on failure and 1 on success.
 125  */
 126 int cse_request_global_reset(enum rst_req_type rst_type);
 127
 128 /*
 129  * Send HMRFPO_ENABLE command.
 130  * returns 0 on failure and 1 on success.
 131  */
 132 int cse_hmrfpo_enable(void);
 133
 134 /*
 135  * Send HMRFPO_GET_STATUS command.
 136  * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED)
 137  * on success.
 138  */
 139 int cse_hmrfpo_get_status(void);
 140
 141 /* Fixed Address MEI Header's Host Address field value */
 142 #define BIOS_HOST_ADDR  0x00
 143
 144 /* Fixed Address MEI Header's ME Address field value */
 145 #define HECI_MKHI_ADDR  0x07
 146
 147 /* HMRFPO Status types */
 148 /* Host can't access ME region */
 149 #define MKHI_HMRFPO_DISABLED    0
 150
 151 /*
 152  * ME Firmware locked down HMRFPO Feature.
 153  * Host can't access ME region.
 154  */
 155 #define MKHI_HMRFPO_LOCKED      1
 156
 157 /* Host can access ME region */
 158 #define MKHI_HMRFPO_ENABLED     2
 159
 160 /*
 161  * Checks current working operation state is normal or not.
 162  * Returns true if CSE's current working state is normal, otherwise false.
 163  */
 164 bool cse_is_hfs1_cws_normal(void);
 165
 166 /*
 167  * Checks CSE's current operation mode is normal or not.
 168  * Returns true if CSE's current operation mode is normal, otherwise false.
 169  */
 170 bool cse_is_hfs1_com_normal(void);
 171
 172 /*
 173  * Checks CSE's current operation mode is SECOVER_MEI_MSG or not.
 174  * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false.
 175  */
 176 bool cse_is_hfs1_com_secover_mei_msg(void);
 177
 178 /*
 179  * Checks CSE's current operation mode is Soft Disable Mode or not.
 180  * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false.
 181  */
 182 bool cse_is_hfs1_com_soft_temp_disable(void);
 183
 184 #endif // SOC_INTEL_COMMON_CSE_H