src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb

   1 chip soc/intel/alderlake
   2
   3         device cpu_cluster 0 on
   4                 device lapic 0 on end
   5         end
   6
   7         # GPE configuration
   8         # Note that GPE events called out in ASL code rely on this
   9         # route. i.e. If this route changes then the affected GPE
  10         # offset bits also need to be changed.
  11         register "pmc_gpe0_dw0" = "GPP_B"
  12         register "pmc_gpe0_dw1" = "GPP_D"
  13         register "pmc_gpe0_dw2" = "GPP_E"
  14
  15         # FSP configuration
  16
  17         register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"         # Type-C Port1
  18         register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"         # Type-C Port2
  19         register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"         # Type-C Port3
  20         register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 WWAN
  21         register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"         # Type-C Port4
  22         register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # FPS connector
  23         register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"         # USB3/2 Type A port1
  24         register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"         # USB3/2 Type A port2
  25         register "usb2_ports[8]" = "USB2_PORT_MID(OC3)"         # USB3/2 Type A port3
  26         register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"     # M.2 WLAN
  27
  28         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"     # USB3/2 Type A port1
  29         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"     # USB3/2 Type A port2
  30         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"     # USB3/2 Type A port3
  31         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
  32
  33         # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
  34         register "gen1_dec" = "0x00fc0801"
  35         register "gen2_dec" = "0x000c0201"
  36         # EC memory map range is 0x900-0x9ff
  37         register "gen3_dec" = "0x00fc0901"
  38         register "gen4_dec" = "0x000c0081"
  39
  40         register "PrmrrSize" = "0"
  41
  42         # Enable PCH PCIE RP 5 using CLK 2
  43         register "PcieRpEnable[4]" = "1"
  44         register "PcieClkSrcClkReq[2]" = "2"
  45         register "PcieClkSrcUsage[2]" = "0x4"
  46         register "PcieRpClkReqDetect[4]" = "1"
  47
  48         # Enable PCH PCIE RP 6 using CLK 5
  49         register "PcieRpEnable[5]" = "1"
  50         register "PcieClkSrcClkReq[5]" = "5"
  51         register "PcieClkSrcUsage[5]" = "0x5"
  52         register "PcieRpClkReqDetect[5]" = "1"
  53
  54         # Enable PCH PCIE RP 9 using CLK 1
  55         register "PcieRpEnable[8]" = "1"
  56         register "PcieClkSrcClkReq[1]" = "1"
  57         register "PcieClkSrcUsage[1]" = "0x8"
  58         register "PcieRpClkReqDetect[8]" = "1"
  59
  60         # Enable PCH PCIE RP 11 for optane
  61         register "PcieRpEnable[10]" = "1"
  62         # Hybrid storage mode
  63         register "HybridStorageMode" = "1"
  64
  65         # Enable CPU PCIE RP 1 using PEG CLK 0
  66         register "PcieClkSrcUsage[0]" = "0x40"
  67
  68         # Enable PCU PCIE PEG Slot 1 and 2
  69         register "PcieClkSrcUsage[3]" = "0x41"
  70         register "PcieClkSrcUsage[4]" = "0x42"
  71
  72         # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
  73         register "PcieClkSrcUsage[6]" = "0xff"
  74
  75         register "SataSalpSupport" = "1"
  76
  77         register "SataPortsEnable" = "{
  78                 [0]  = 1,
  79                 [1]  = 1,
  80                 [2]  = 1,
  81                 [3]  = 1,
  82         }"
  83
  84         register "SataPortsDevSlp" = "{
  85                 [0]  = 1,
  86                 [1]  = 1,
  87                 [2]  = 1,
  88                 [3]  = 1,
  89         }"
  90
  91         # Enable EDP in PortA
  92         register "DdiPortAConfig" = "1"
  93         register "DdiPortBConfig" = "1"
  94
  95         # TCSS USB3
  96         register "TcssAuxOri" = "0"
  97
  98         register "s0ix_enable" = "1"
  99
 100         register "SerialIoI2cMode" = "{
 101                 [PchSerialIoIndexI2C0]  = PchSerialIoPci,
 102                 [PchSerialIoIndexI2C1]  = PchSerialIoPci,
 103                 [PchSerialIoIndexI2C2]  = PchSerialIoPci,
 104                 [PchSerialIoIndexI2C3]  = PchSerialIoPci,
 105                 [PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
 106                 [PchSerialIoIndexI2C5]  = PchSerialIoPci,
 107         }"
 108
 109         register "SerialIoGSpiMode" = "{
 110                 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
 111                 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
 112                 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
 113                 [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
 114         }"
 115
 116         register "SerialIoGSpiCsMode" = "{
 117                 [PchSerialIoIndexGSPI0] = 0,
 118                 [PchSerialIoIndexGSPI1] = 0,
 119                 [PchSerialIoIndexGSPI2] = 0,
 120                 [PchSerialIoIndexGSPI3] = 0,
 121         }"
 122
 123         register "SerialIoGSpiCsState" = "{
 124                 [PchSerialIoIndexGSPI0] = 0,
 125                 [PchSerialIoIndexGSPI1] = 0,
 126                 [PchSerialIoIndexGSPI2] = 0,
 127                 [PchSerialIoIndexGSPI3] = 0,
 128         }"
 129
 130         register "SerialIoUartMode" = "{
 131                 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 132                 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
 133                 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
 134         }"
 135
 136         # HD Audio
 137         register "PchHdaDspEnable" = "1"
 138         register "PchHdaAudioLinkHdaEnable" = "0"
 139         register "PchHdaAudioLinkDmicEnable[0]" = "1"
 140         register "PchHdaAudioLinkDmicEnable[1]" = "1"
 141         register "PchHdaAudioLinkSndwEnable[0]" = "1"
 142         register "PchHdaAudioLinkSndwEnable[1]" = "1"
 143         # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
 144         register "PchHdaIDispLinkTmode" = "2"
 145         # iDisp-Link Freq 4: 96MHz, 3: 48MHz.
 146         register "PchHdaIDispLinkFrequency" = "4"
 147         # Not disconnected/enumerable
 148         register "PchHdaIDispCodecDisconnect" = "0"
 149
 150         # Intel Common SoC Config
 151         register "common_soc_config" = "{
 152                 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 153                 .i2c[0] = {
 154                         .speed = I2C_SPEED_FAST,
 155                 },
 156                 .i2c[1] = {
 157                         .speed = I2C_SPEED_FAST,
 158                 },
 159                 .i2c[2] = {
 160                         .speed = I2C_SPEED_FAST,
 161                 },
 162                 .i2c[3] = {
 163                         .speed = I2C_SPEED_FAST,
 164                 },
 165                 .i2c[5] = {
 166                         .speed = I2C_SPEED_FAST,
 167                 },
 168         }"
 169
 170         device domain 0 on
 171                 device pci 00.0 on  end # Host Bridge
 172                 device pci 02.0 on  end # Graphics
 173                 device pci 04.0 on  end # DPTF
 174                 device pci 05.0 on  end # IPU
 175                 device pci 06.0 on  end # PEG60
 176                 device pci 07.0 on  end # TBT_PCIe0
 177                 device pci 07.1 on  end # TBT_PCIe1
 178                 device pci 07.2 on  end # TBT_PCIe2
 179                 device pci 07.3 on  end # TBT_PCIe3
 180                 device pci 08.0 off end # GNA
 181                 device pci 09.0 off end # NPK
 182                 device pci 0a.0 off end # Crash-log SRAM
 183                 device pci 0d.0 on  end # USB xHCI
 184                 device pci 0d.1 on  end # USB xDCI (OTG)
 185                 device pci 0d.2 on  end # TBT DMA0
 186                 device pci 0d.3 on  end # TBT DMA1
 187                 device pci 0e.0 off end # VMD
 188                 device pci 10.0 off end
 189                 device pci 10.1 off end
 190                 device pci 10.2 on  end # CNVi: BT
 191                 device pci 10.6 off end # THC0
 192                 device pci 10.7 off end # THC1
 193                 device pci 11.0 off end
 194                 device pci 11.1 off end
 195                 device pci 11.2 off end
 196                 device pci 11.3 off end
 197                 device pci 11.4 off end
 198                 device pci 11.5 off end
 199                 device pci 12.0 off end # SensorHUB
 200                 device pci 12.5 off end
 201                 device pci 12.6 off end # GSPI2
 202                 device pci 13.0 off end # GSPI3
 203                 device pci 13.1 off end
 204                 device pci 14.0 on
 205                         chip drivers/usb/acpi
 206                                 register "desc" = ""Root Hub""
 207                                 register "type" = "UPC_TYPE_HUB"
 208                                 device usb 0.0 on
 209                                         chip drivers/usb/acpi
 210                                                 register "desc" = ""Bluetooth""
 211                                                 register "type" = "UPC_TYPE_INTERNAL"
 212                                                 device usb 2.9 on end
 213                                         end
 214                                 end
 215                         end
 216                 end # USB3.1 xHCI
 217                 device pci 14.1 off end # USB3.1 xDCI
 218                 device pci 14.2 off end # Shared RAM
 219                 device pci 14.3 on
 220                         chip drivers/wifi/generic
 221                                 register "wake" = "GPE0_PME_B0"
 222                                 device generic 0 on end
 223                         end
 224                 end # CNVi: WiFi
 225                 device pci 15.0 on  end # I2C0
 226                 device pci 15.1 on  end # I2C1
 227                 device pci 15.2 on  end # I2C2
 228                 device pci 15.3 on  end # I2C3
 229                 device pci 16.0 on  end # HECI1
 230                 device pci 16.1 off end # HECI2
 231                 device pci 16.2 off end # CSME
 232                 device pci 16.3 off end # CSME
 233                 device pci 16.4 off end # HECI3
 234                 device pci 16.5 off end # HECI4
 235                 device pci 17.0 on  end # SATA
 236                 device pci 19.0 off end # I2C4
 237                 device pci 19.1 on  end # I2C5
 238                 device pci 19.2 off end # UART2
 239                 device pci 1c.0 on  end # RP1
 240                 device pci 1c.1 off end # RP2
 241                 device pci 1c.2 off end # RP3
 242                 device pci 1c.3 off end # RP4
 243                 device pci 1c.4 on  end # RP5
 244                 device pci 1c.5 on  end # RP6
 245                 device pci 1c.6 off end # RP7
 246                 device pci 1c.7 off end # RP8
 247                 device pci 1d.0 on  end # RP9
 248                 device pci 1d.1 off end # RP10
 249                 device pci 1d.2 on  end # RP11
 250                 device pci 1d.3 off end # RP12
 251                 device pci 1e.0 on  end # UART0
 252                 device pci 1e.1 off end # UART1
 253                 device pci 1e.2 on  end # GSPI0
 254                 device pci 1e.3 off end # GSPI1
 255                 device pci 1f.0 on  end # eSPI
 256                 device pci 1f.1 on  end # P2SB
 257                 device pci 1f.2 hidden  end # PMC
 258                 device pci 1f.3 on
 259                         chip drivers/intel/soundwire
 260                                 device generic 0 on
 261                                         chip drivers/soundwire/alc711
 262                                                 # SoundWire Link 0 ID 1
 263                                                 register "desc" = ""Headset Codec""
 264                                                 device generic 0.1 on end
 265                                         end
 266                                 end
 267                         end
 268                 end # Intel Audio SNDW
 269                 device pci 1f.4 on  end # SMBus
 270                 device pci 1f.5 on  end # SPI
 271                 device pci 1f.6 off end # GbE
 272                 device pci 1f.7 off end # TH
 273         end
 274 end