src/vendorcode/amd/cimx/sb800/SBCMN.c

   1 /**
   2  * @file
   3  *
   4  * Southbridge Initial routine
   5  *
   6  *
   7  *
   8  * @xrefitem bom "File Content Label" "Release Content"
   9  * @e project:      CIMx-SB
  10  * @e sub-project:
  11  * @e \$Revision:$   @e \$Date:$
  12  *
  13  */
  14 /*
  15  *****************************************************************************
  16  *
  17  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  18  * All rights reserved.
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions are met:
  22  *     * Redistributions of source code must retain the above copyright
  23  *       notice, this list of conditions and the following disclaimer.
  24  *     * Redistributions in binary form must reproduce the above copyright
  25  *       notice, this list of conditions and the following disclaimer in the
  26  *       documentation and/or other materials provided with the distribution.
  27  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  28  *       its contributors may be used to endorse or promote products derived
  29  *       from this software without specific prior written permission.
  30  *
  31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  32  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  33  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  35  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  36  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  37  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  38  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  39  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  40  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * ***************************************************************************
  43  *
  44  */
  45
  46 #include "SBPLATFORM.h"
  47 #include "cbtypes.h"
  48 //
  49 // Declaration of local functions
  50 //
  51
  52 VOID abcfgTbl (IN ABTBLENTRY* pABTbl);
  53
  54 /**
  55  * sbUsbPhySetting - USB Phy Calibration Adjustment
  56  *
  57  *
  58  * @param[in] Value  Controller PCI config address (bus# + device# + function#)
  59  *
  60  */
  61 VOID sbUsbPhySetting (IN  UINT32 Value);
  62
  63
  64 /*--------------------------- Documentation Pages ---------------------------*/
  65 /**
  66  *  @page LegacyInterfaceCalls  Legacy Interface Calls
  67  *  <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD>
  68  *  <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD>
  69  *  <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD>
  70  *  <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD>
  71  *  <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD>
  72  *  <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD>
  73  *  <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD>
  74  *  <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD>
  75  *
  76  *  @page LegacyInterfaceCallOuts  Legacy Interface CallOuts
  77  *  <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
  78  *  <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
  79  *
  80 */
  81
  82 /**
  83  * sbEarlyPostByteInitTable - PCI device registers initial during early POST.
  84  *
  85  */
  86 static const REG8MASK sbEarlyPostByteInitTable[] =
  87 {
  88   // SMBUS Device (Bus 0, Dev 20, Func 0)
  89   {0x00, SMBUS_BUS_DEV_FUN, 0},
  90   {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information
  91   {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)},
  92   {0xFF, 0xFF, 0xFF},
  93
  94   // IDE Device (Bus 0, Dev 20, Func 1)
  95   {0x00, IDE_BUS_DEV_FUN, 0},
  96   {SB_IDE_REG62 + 1, ~BIT0, BIT5},  // Enabling IDE Explicit Pre-Fetch  IDE PCI Config 0x62[8]=0
  97   // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
  98   {0xFF, 0xFF, 0xFF},
  99
 100   // Azalia Device (Bus 0, Dev 20, Func 2)
 101   {0x00, AZALIA_BUS_DEV_FUN, 0},
 102   {SB_AZ_REG4C, ~BIT0, BIT0},
 103   {0xFF, 0xFF, 0xFF},
 104
 105   // LPC Device (Bus 0, Dev 20, Func 3)
 106   {0x00, LPC_BUS_DEV_FUN, 0},
 107   {SB_LPC_REG40, ~BIT2, BIT2},     // RPR 1.1 Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b
 108   {SB_LPC_REG78, ~BIT0, 00},       // RPR 1.1 Enabling LPC DMA Function  0x40[2]=1b 0x78[0]=0b
 109   {SB_LPC_REG78, ~BIT1, 00},       // Disables MSI capability
 110   {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5},     // Enabled SPI Prefetch from HOST.
 111   {0xFF, 0xFF, 0xFF},
 112
 113   // PCIB Bridge (Bus 0, Dev 20, Func 4)
 114   {0x00, PCIB_BUS_DEV_FUN, 0},
 115   {SB_PCIB_REG40, 0xFF, BIT5},      // RPR PCI-bridge Subtractive Decode
 116   {SB_PCIB_REG4B, 0xFF, BIT7},      //
 117   {SB_PCIB_REG66, 0xFF, BIT4},      // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
 118   {SB_PCIB_REG65, 0xFF, BIT7},      // RPR proper operation of CLKRUN#.
 119   {SB_PCIB_REG0D, 0x00, 0x40},      // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
 120   {SB_PCIB_REG1B, 0x00, 0x40},      // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
 121   {SB_PCIB_REG66 + 1, 0xFF, BIT1},  // RPR Enable PCI bus GNT3#..
 122   {0xFF, 0xFF, 0xFF},
 123
 124   // SATA Device (Bus 0, Dev 17, Func 0)
 125   {0x00, SATA_BUS_DEV_FUN, 0},
 126   {SB_SATA_REG44, 0xff, BIT0},       // Enables the SATA watchdog timer register prior to the SATA BIOS post
 127   {SB_SATA_REG44 + 2, 0, 0x20},      // RPR 8.12 SATA PCI Watchdog timer setting
 128                                      // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
 129   {0xFF, 0xFF, 0xFF},
 130 };
 131
 132
 133 /**
 134  * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.
 135  *
 136  */
 137 static const AcpiRegWrite sbPmioEPostInitTable[] =
 138 {
 139   // HPET workaround
 140   {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
 141   {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 2, 0x7F, BIT7},
 142   {PMIO_BASE >> 8,  SB_PMIOA_REG54 + 2, 0x7F, 0x00},
 143   // End of HPET workaround
 144   // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3]
 145   // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
 146   // UsbGoodClkDlyEn         4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
 147   // ForceNBCPUPwr           5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
 148   // MergeUsbPerReq          6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
 149   // IMCWatchDogRstEn        7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
 150   // GeventStsFixEn          8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
 151   // PmeTimerFixEn           9 Set to 1 to reset Pme Timer when going to sleep state.
 152   // UserRst2EcEn           10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
 153   // Smbus0ClkSEn           30 Set to 1 to enable SMBus0 controller clock stretch support.
 154   {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4},
 155   {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9},
 156   // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting
 157   {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B},
 158   // RtcSts              19-17 RTC_STS set only in Sleep State.
 159   // GppPme                 20 Set to 1 to enable PME request from SB GPP.
 160   // Pcireset               22 Set to 1 to allow SW to reset PCIe.
 161   {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58},
 162   {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40},
 163
 164   //Item Id:      SB02037: RTC_STS should be set in S state
 165   //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state.
 166   //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E},
 167
 168   //Item Id:      SB02034
 169   //Title:        SB GPP NIC auto wake at second time sleep
 170   //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034
 171
 172   {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4},
 173
 174   //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E},
 175   {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
 176   {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
 177   {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4},
 178   {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3},
 179   {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6},
 180   {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1},
 181   {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0},
 182   //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
 183   {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0},
 184   // RPR Turning off FC clock
 185   {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2},
 186   {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0},
 187   {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29},
 188   {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1},
 189   {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29},
 190   {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29},
 191   {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4},
 192   {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5},
 193   {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6},
 194   {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29},
 195
 196   {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29},
 197   {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29},
 198   {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29},
 199   {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29},
 200   {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29},
 201   {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29},
 202   {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29},
 203   {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29},
 204   {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29},
 205   {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29},
 206   {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29},
 207   {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29},
 208   {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29},
 209   {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29},
 210   {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29},
 211 //
 212   {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11},
 213   {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11},
 214   {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11},
 215   {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11},
 216   {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12},
 217   {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29},
 218   {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13},
 219   {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15},
 220   {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16},
 221   {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17},
 222   {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18},
 223   {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29},
 224   {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29},
 225   {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29},
 226   {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29},
 227   {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19},
 228   {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23},
 229   {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26},
 230   {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27},
 231   {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30},
 232   {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31},
 233
 234   {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29},
 235   {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29},
 236   {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29},
 237
 238 //  {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4},
 239 //  {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0},
 240 //  {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3},
 241   {SMI_BASE >> 8, SB_SMI_REG08,  ~BIT4, 0},
 242   {SMI_BASE >> 8, SB_SMI_REG08+3,  ~BIT2, 0},
 243 //  {SMI_BASE >> 8, SB_SMI_REG0C,  ~BIT4, BIT4},
 244   {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3},
 245   {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9},
 246   {SMI_BASE >> 8, SB_SMI_TMI, 0, 29},
 247   {0xFF, 0xFF, 0xFF, 0xFF},
 248 };
 249
 250 /**
 251  * abTblEntry800 - AB-Link Configuration Table for SB800
 252  *
 253  */
 254 static const ABTBLENTRY abTblEntry800[] =
 255 {
 256   // RPR Enable downstream posted transactions to pass non-posted transactions.
 257   {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
 258
 259   // RPR Enable SB800 to issue memory read/write requests in the upstream direction.
 260   {AXCFG, SB_AB_REG04, BIT2, BIT2},
 261
 262   // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement
 263   // PCIB prefetch   ABCFG 0x10060 [20] = 1   ABCFG 0x10064 [20] = 1
 264   {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, //  PCIB prefetch enable
 265   {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, //  PCIB prefetch enable
 266
 267   // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
 268   // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
 269   {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
 270
 271   // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]
 272   // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17]
 273   {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},
 274
 275   // RPR Disable the credit variable in the downstream arbitration equation
 276   // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
 277   {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0},
 278
 279   // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
 280   // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
 281   {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
 282
 283   // RPR Programming cycle delay for AB and BIF clock gating
 284   // RPR Enable the AB and BIF clock-gating logic.
 285   // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
 286   // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
 287   {ABCFG, SB_ABCFG_REG10054,  0x00FFFFFF, 0x010407FF},
 288   {ABCFG, SB_ABCFG_REG98,  0xFFFF00FF, 0x00034700},
 289   {ABCFG, SB_ABCFG_REG54,  0x00FF0000, 0x00040000},
 290   // RPR Non-Posted Memory Write Support
 291   {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9},
 292   {ABCFG, 0, 0, (UINT8) 0xFF},  // This dummy entry is to clear ab index
 293   { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
 294 };
 295
 296 /**
 297  * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature
 298  *
 299  */
 300 static const ABTBLENTRY SbPcieOrderRule[] =
 301 {
 302 // abPostPassNpDownStreamTbl
 303   {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},
 304   {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
 305   {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
 306   {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
 307   {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
 308   {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9},
 309   {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
 310 // abPostPassNpUpStreamTbl
 311   {ABCFG, SB_ABCFG_REG58, BIT10, BIT10},
 312   {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
 313   {ABCFG, SB_ABCFG_REG54, BIT1, BIT1},
 314   { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
 315 };
 316
 317 /**
 318  * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
 319  *
 320  *    This settings should be done during S3 resume also
 321  *
 322  * @param[in] pConfig Southbridge configuration structure pointer.
 323  *
 324  */
 325 VOID
 326 commonInitEarlyBoot (
 327   IN       AMDSBCFG* pConfig
 328   )
 329 {
 330   UINT32   abValue;
 331   UINT16   dwTempVar;
 332   CPUID_DATA  CpuId;
 333   UINT8   cimNativepciesupport;
 334   UINT8   cimIrConfig;
 335   UINT8   Data;
 336
 337   cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;
 338   cimIrConfig = (UINT8) pConfig->IrConfig;
 339 #if  SB_CIMx_PARAMETER == 0
 340   cimNativepciesupport = cimNativepciesupportDefault;
 341   cimIrConfig = cimIrConfigDefault;
 342 #endif
 343
 344   //IR init Logical device 0x05
 345   if ( cimIrConfig ) {
 346     // Enable EC_PortActive
 347     RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
 348     EnterEcConfig ();
 349     RWEC8 (0x07, 0x00, 0x05);         //Select logical device 05, IR controller
 350     RWEC8 (0x60, 0x00, 0x05);         //Set Base Address to 550h
 351     RWEC8 (0x61, 0x00, 0x50);
 352     RWEC8 (0x70, 0xF0, 0x05);         //Set IRQ to 05h
 353     RWEC8 (0x30, 0x00, 0x01);         //Enable logical device 5, IR controller
 354     Data = 0xAB;
 355     WriteIO (0x550, AccWidthUint8, &Data);
 356     ReadIO (0x551, AccWidthUint8, &Data);
 357     Data = ((Data & 0xFC ) | cimIrConfig);
 358     WriteIO (0x551, AccWidthUint8, &Data);
 359     ExitEcConfig ();
 360     Data = 0xA0;                      // EC APIC index
 361     WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
 362     Data = 0x05;                      // IRQ5
 363     WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
 364   } else {
 365     EnterEcConfig ();
 366     RWEC8 (0x07, 0x00, 0x05);         //Select logical device 05, IR controller
 367     RWEC8 (0x30, 0x00, 0x00);         //Disable logical device 5, IR controller
 368     ExitEcConfig ();
 369   }
 370
 371
 372   CpuidRead (0x01, &CpuId);
 373
 374   //
 375   // SB CFG programming
 376   //
 377   //Make BAR registers of smbus visible.
 378   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
 379   //Early post initialization of pci config space
 380   programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
 381   if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
 382     RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
 383   }
 384   //Make BAR registers of smbus invisible.
 385   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
 386
 387   //
 388   // LPC CFG programming
 389   //
 390   // SSID for LPC Controller
 391   if (pConfig->BuildParameters.LpcSsid != 0 ) {
 392     RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
 393   }
 394   // LPC MSI
 395   if ( pConfig->BuildParameters.LpcMsi) {
 396     RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1);
 397   }
 398
 399   //
 400   // PCIB CFG programming
 401   //
 402   //Disable or Enable PCI Clks based on input
 403   RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
 404   RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4  );
 405   // PCIB MSI
 406   if ( pConfig->BuildParameters.PcibMsi) {
 407     RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3);
 408   }
 409
 410   //
 411   // AB CFG programming
 412   //
 413   // Read Arbiter address, Arbiter address is in PMIO 6Ch
 414   ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar);
 415   RWIO (dwTempVar, AccWidthUint8, 0, 0);        // Write 0 to enable the arbiter
 416
 417   abLinkInitBeforePciEnum (pConfig);            // Set ABCFG registers
 418   // AB MSI
 419   if ( pConfig->BuildParameters.AbMsi) {
 420     abValue = readAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29));
 421     abValue = abValue | BIT20;
 422     writeAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29), abValue);
 423   }
 424
 425
 426   //
 427   // SB Specific Function programming
 428   //
 429
 430   // PCIE Native setting
 431   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0);
 432   if ( pConfig->NativePcieSupport == 1) {
 433     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0);
 434   } else {
 435     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2);
 436   }
 437
 438 #ifdef ACPI_SLEEP_TRAP
 439   // Set SLP_TYPE as SMI event
 440   RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2);
 441   // Disabled SLP function for S1/S3/S4/S5
 442   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00);
 443   // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
 444   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1);
 445   // Enabled Global Smi ( BIT7 clear as 0 to enable )
 446   RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00);
 447 #endif
 448   if ( pConfig->SbUsbPll == 0) {
 449     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);
 450   }
 451   // Set Stutter timer settings
 452   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4);
 453   // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz
 454   if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
 455     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A);
 456     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28);
 457   } else {
 458     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01);
 459     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20);
 460   }
 461
 462   //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled
 463   //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled
 464   //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme.
 465   if (pConfig->MTC1e) {
 466     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1);
 467     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
 468   }
 469
 470   programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
 471 }
 472
 473 /**
 474  * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
 475  *
 476  *
 477  * @param[in] pConfig Southbridge configuration structure pointer.
 478  *
 479  */
 480 VOID
 481 abSpecialSetBeforePciEnum (
 482   IN       AMDSBCFG* pConfig
 483   )
 484 {
 485   UINT32   abValue;
 486   abValue = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29));
 487   abValue &= 0xf0;
 488   if ( pConfig->SbPcieOrderRule && abValue ) {
 489     abValue = readAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29));
 490     abValue = abValue | BIT9;
 491     writeAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29), abValue);
 492   }
 493 }
 494
 495 VOID
 496 usbDesertPll (
 497   IN       AMDSBCFG* pConfig
 498   )
 499 {
 500   if ( pConfig->SbUsbPll == 0) {
 501     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);
 502   }
 503 }
 504
 505 /**
 506  * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
 507  *
 508  *    This settings might not program during S3 resume
 509  *
 510  * @param[in] pConfig Southbridge configuration structure pointer.
 511  *
 512  */
 513 VOID
 514 commonInitEarlyPost (
 515   IN       AMDSBCFG* pConfig
 516   )
 517 {
 518   UINT8  dbPortStatus;
 519   UINT8  cimSpreadSpectrum;
 520   UINT32 cimSpreadSpectrumType;
 521   AMDSBCFG*   pTmp;
 522   pTmp = pConfig;
 523
 524   cimSpreadSpectrum = pConfig->SpreadSpectrum;
 525   cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType;
 526 #if  SB_CIMx_PARAMETER == 0
 527   cimSpreadSpectrum = cimSpreadSpectrumDefault;
 528   cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault;
 529 #endif
 530   programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0]));
 531
 532   // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
 533
 534   if ( cimSpreadSpectrum ) {
 535   // Misc_Reg_40[25]=1 -> allow to change spread profile
 536   // Misc_Reg19=83 -> new spread profile
 537   // Misc_Reg[12:10]=9975be
 538   // Misc_Reg0B=91
 539   // Misc_Reg09=21
 540   // Misc_Misc_Reg_08[0]=1 -> enable spread
 541     RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1);
 542     RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83);
 543     getChipSysMode (&dbPortStatus);
 544     if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) {
 545       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80);
 546     }
 547
 548     if ( cimSpreadSpectrumType == 0 ) {
 549       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99);
 550       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75);
 551       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE);
 552       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91);
 553       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
 554     } else { // Spread profile for Ontario CPU related platform
 555       // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425%
 556       // Misc_Reg[12:10]=828FA8
 557       // Misc_Reg0B=11
 558       // Misc_Reg09=21
 559       // Misc_Reg10[25:24]=01b
 560       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82);
 561       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F);
 562       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8);
 563       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11);
 564       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);
 565       RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1);
 566     }
 567
 568     RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01);
 569   } else {
 570     RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);
 571   }
 572
 573   // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode
 574   getChipSysMode (&dbPortStatus);
 575   if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
 576     RWMEM (ACPI_MMIO_BASE + MISC_BASE +  SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5);
 577   }
 578
 579   // Set ASF SMBUS master function enabled here (temporary)
 580   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2);
 581
 582   programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
 583 #ifndef NO_EC_SUPPORT
 584   // Software IMC enable
 585   if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) {
 586     if (validateImcFirmware (pConfig)) {
 587       softwareToggleImcStrapping (pConfig);
 588     } else {
 589       CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig);
 590     }
 591   }
 592 #endif
 593
 594 }
 595 /**
 596  * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
 597  *
 598  *
 599  * @param[in] pConfig Southbridge configuration structure pointer.
 600  *
 601  */
 602 VOID
 603 abLinkInitBeforePciEnum (
 604   IN       AMDSBCFG* pConfig
 605   )
 606 {
 607   UINT32  cimResetCpuOnSyncFlood;
 608   ABTBLENTRY  *pAbTblPtr;
 609   AMDSBCFG* Temp;
 610
 611   cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;
 612 #if  SB_CIMx_PARAMETER == 0
 613   cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;
 614 #endif
 615   Temp = pConfig;
 616   if ( pConfig->SbPcieOrderRule ) {
 617     pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);
 618     abcfgTbl (pAbTblPtr);
 619   }
 620   pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]);
 621   abcfgTbl (pAbTblPtr);
 622   if ( cimResetCpuOnSyncFlood ) {
 623     rwAlink (SB_ABCFG_REG10050 | ((UINT32) ABCFG << 29), ~BIT2, BIT2);
 624   }
 625 }
 626
 627 /**
 628  * abcfgTbl - Program ABCFG by input table.
 629  *
 630  *
 631  * @param[in] pABTbl  ABCFG config table.
 632  *
 633  */
 634 VOID
 635 abcfgTbl (
 636   IN       ABTBLENTRY* pABTbl
 637   )
 638 {
 639   UINT32   ddValue;
 640
 641   while ( (pABTbl->regType) != 0xFF ) {
 642     if ( pABTbl->regType > AXINDC ) {
 643       ddValue = pABTbl->regIndex | ((UINT32) pABTbl->regType << 29);
 644       writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
 645     } else {
 646       ddValue = 0x30 | ((UINT32) pABTbl->regType << 29);
 647       writeAlink (ddValue, pABTbl->regIndex);
 648       ddValue = 0x34 | ((UINT32) pABTbl->regType << 29);
 649       writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);
 650     }
 651     ++pABTbl;
 652   }
 653
 654   //Clear ALink Access Index
 655   ddValue = 0;
 656   WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
 657 }
 658
 659 /**
 660  * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
 661  *
 662  *
 663  * @param[in] pConfig Southbridge configuration structure pointer.
 664  *
 665  */
 666 VOID
 667 commonInitLateBoot (
 668   IN       AMDSBCFG* pConfig
 669   )
 670 {
 671   UINT8  dbValue;
 672   UINT32  ddVar;
 673   // We need to do the following setting in late post also because some bios core pci enumeration changes these values
 674   // programmed during early post.
 675   // RPR 4.5 Master Latency Timer
 676
 677   dbValue = 0x40;
 678   WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue);
 679   WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue);
 680
 681   //SB P2P AutoClock control settings.
 682   ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow);
 683   WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar);
 684   ddVar = (pConfig->PcibClkStopOverride);
 685   RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
 686
 687   RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5);
 688
 689   // USB Phy Calibration Adjustment
 690   ddVar = (USB1_EHCI_BUS_DEV_FUN << 16);
 691   sbUsbPhySetting (ddVar);
 692   ddVar = (USB2_EHCI_BUS_DEV_FUN << 16);
 693   sbUsbPhySetting (ddVar);
 694   ddVar = (USB3_EHCI_BUS_DEV_FUN << 16);
 695   sbUsbPhySetting (ddVar);
 696
 697   c3PopupSetting (pConfig);
 698   FusionRelatedSetting (pConfig);
 699 }
 700
 701 /**
 702  * sbUsbPhySetting - USB Phy Calibration Adjustment
 703  *
 704  *
 705  * @param[in] Value  Controller PCI config address (bus# + device# + function#)
 706  *
 707  */
 708 VOID
 709 sbUsbPhySetting (
 710   IN       UINT32 Value
 711   )
 712 {
 713   UINT32  ddBarAddress;
 714   UINT32  ddPhyStatus03;
 715   UINT32  ddPhyStatus4;
 716   UINT8   dbRevId;
 717   //Get BAR address
 718   ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
 719   if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
 720     ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03);
 721     ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4);
 722     ddPhyStatus03 &= 0x07070707;
 723     ddPhyStatus4 &= 0x00000007;
 724     if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) {
 725       // RPR 7.7 USB 2.0 Ports Driving Strength step 1
 726       //Make BAR registers of smbus visible.
 727       RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
 728       ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId);
 729       //Make BAR registers of smbus invisible.
 730       RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);
 731       if (dbRevId == 0x41) { // A12
 732         RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500);
 733         RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0);
 734       } else if (dbRevId == 0x42) { // A13
 735         RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00);
 736         RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100);
 737       }
 738     }
 739   }
 740 }
 741
 742 /**
 743  * hpetInit - Program Southbridge HPET function
 744  *
 745  *
 746  *
 747  * @param[in] pConfig         Southbridge configuration structure pointer.
 748  * @param[in] pStaticOptions  Platform build configuration table.
 749  *
 750  */
 751 VOID
 752 hpetInit (
 753   IN       AMDSBCFG* pConfig,
 754   IN       BUILDPARAM *pStaticOptions
 755   )
 756 {
 757   DESCRIPTION_HEADER* pHpetTable;
 758   UINT8 cimHpetTimer;
 759   UINT8 cimHpetMsiDis;
 760
 761   cimHpetTimer = (UINT8) pConfig->HpetTimer;
 762   cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis;
 763 #if  SB_CIMx_PARAMETER == 0
 764   cimHpetTimer = cimHpetTimerDefault;
 765   cimHpetMsiDis = cimHpetMsiDisDefault;
 766 #endif
 767   pHpetTable = NULL;
 768   if ( cimHpetTimer == TRUE ) {
 769     //Program the HPET BAR address
 770     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase);
 771     //Enabling decoding of HPET MMIO
 772     //Enable HPET MSI support
 773     //Enable High Precision Event Timer (also called Multimedia Timer) interrupt
 774     if ( cimHpetMsiDis == FALSE ) {
 775       RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
 776     } else {
 777       RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);
 778     }
 779
 780   } else {
 781     if ( ! (pConfig->S3Resume) ) {
 782       pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('H', 'P', 'E', 'T'));
 783     }
 784     if ( pHpetTable != NULL ) {
 785       pHpetTable->Signature = Int32FromChar('T', 'E', 'P', 'H');
 786     }
 787   }
 788 }
 789
 790 /**
 791  * c3PopupSetting - Program Southbridge C state function
 792  *
 793  *
 794  *
 795  * @param[in] pConfig   Southbridge configuration structure pointer.
 796  *
 797  */
 798 VOID
 799 c3PopupSetting (
 800   IN       AMDSBCFG* pConfig
 801   )
 802 {
 803   AMDSBCFG* Temp;
 804   UINT8  dbValue;
 805   Temp = pConfig;
 806   //RPR C-State and VID/FID Change
 807   dbValue = getNumberOfCpuCores  ();
 808   if (dbValue > 1) {
 809     //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
 810     //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
 811     //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
 812     //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
 813     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2));
 814     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
 815   }
 816   //SB800 needs to changed for RD790 support
 817   //PM 0x80 [8] = 0 for system with RS780
 818   //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
 819   //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
 820   //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
 821   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
 822   //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
 823   //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
 824   //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
 825   //link is disconnected.
 826   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10);
 827
 828   //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
 829   //delay will allow USB DMA to go on in a continuous manner
 830   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10);
 831   // Not in the RPR so far, it's hand writing from ASIC
 832   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85);
 833   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01);
 834   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5);
 835   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);
 836   // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10);
 837   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10);
 838   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B);
 839   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
 840   if (pConfig->LdtStpDisable) {
 841     RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0);
 842   }
 843 }
 844
 845 /**
 846  * FusionRelatedSetting - Program Fusion C related function
 847  *
 848  *
 849  *
 850  * @param[in] pConfig   Southbridge configuration structure pointer.
 851  *
 852  */
 853 VOID
 854 FusionRelatedSetting (
 855   IN       AMDSBCFG* pConfig
 856   )
 857 {
 858   UINT8 cimAcDcMsg;
 859   UINT8 cimTimerTickTrack;
 860   UINT8 cimClockInterruptTag;
 861   UINT8 cimOhciTrafficHanding;
 862   UINT8 cimEhciTrafficHanding;
 863   UINT8 cimFusionMsgCMultiCore;
 864   UINT8 cimFusionMsgCStage;
 865   UINT32 ddValue;
 866
 867   cimAcDcMsg = (UINT8) pConfig->AcDcMsg;
 868   cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack;
 869   cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag;
 870   cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding;
 871   cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding;
 872   cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore;
 873   cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage;
 874 #if  SB_CIMx_PARAMETER == 0
 875   cimAcDcMsg = cimAcDcMsgDefault;
 876   cimTimerTickTrack = cimTimerTickTrackDefault;
 877   cimClockInterruptTag = cimClockInterruptTagDefault;
 878   cimOhciTrafficHanding = cimOhciTrafficHandingDefault;
 879   cimEhciTrafficHanding = cimEhciTrafficHandingDefault;
 880   cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault;
 881   cimFusionMsgCStage = cimFusionMsgCStageDefault;
 882 #endif
 883   ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
 884   ddValue = ddValue & 0xC07F00A0;
 885   if ( cimAcDcMsg ) {
 886     ddValue = ddValue | BIT0;
 887   }
 888   if ( cimTimerTickTrack ) {
 889     ddValue = ddValue | BIT1;
 890   }
 891   if ( cimClockInterruptTag ) {
 892     ddValue = ddValue | BIT10;
 893   }
 894   if ( cimOhciTrafficHanding ) {
 895     ddValue = ddValue | BIT13;
 896   }
 897   if ( cimEhciTrafficHanding ) {
 898     ddValue = ddValue | BIT15;
 899   }
 900   if ( cimFusionMsgCMultiCore ) {
 901     ddValue = ddValue | BIT23;
 902   }
 903   if ( cimFusionMsgCStage ) {
 904     ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2));
 905   }
 906   WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);
 907 }
 908 #ifndef NO_EC_SUPPORT
 909 /**
 910  * validateImcFirmware - Validate IMC Firmware.
 911  *
 912  *
 913  * @param[in] pConfig Southbridge configuration structure pointer.
 914  *
 915  * @retval        TRUE   Pass
 916  * @retval        FALSE  Failed
 917  */
 918 BOOLEAN
 919 validateImcFirmware (
 920   IN       AMDSBCFG* pConfig
 921   )
 922 {
 923   UINT32  ImcSig;
 924   UINT32  ImcSigAddr;
 925   UINT32  ImcAddr;
 926   UINT32  CurAddr;
 927   UINT32  ImcBinSig0;
 928   UINT32  ImcBinSig1;
 929   UINT16  ImcBinSig2;
 930   UINT8  dbIMCChecksume;
 931   UINT8  dbIMC;
 932   ImcAddr = 0;
 933
 934   // Software IMC enable
 935   ImcSigAddr = 0x80000; // start from 512k to 64M
 936   ImcSig = 0x0; //
 937   while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
 938     CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
 939     ReadMEM (CurAddr, AccWidthUint32, &ImcSig);
 940     ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr);
 941     ImcSigAddr <<= 1;
 942   }
 943
 944   dbIMCChecksume = 0xff;
 945   if ( ImcSig == 0x55aa55aa ) {
 946     // "_AMD_IMC_C" at offset 0x2000 of the binary
 947     ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0);
 948     ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1);
 949     ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2);
 950     if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
 951       dbIMCChecksume = 0;
 952       for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
 953         ReadMEM (CurAddr, AccWidthUint8, &dbIMC);
 954         dbIMCChecksume = dbIMCChecksume + dbIMC;
 955       }
 956     }
 957   }
 958   if ( dbIMCChecksume ) {
 959     return  FALSE;
 960   } else {
 961     return  TRUE;
 962   }
 963 }
 964
 965 /**
 966  * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
 967  *
 968  *
 969  * @param[in] pConfig Southbridge configuration structure pointer.
 970  *
 971  */
 972 VOID
 973 softwareToggleImcStrapping (
 974   IN       AMDSBCFG* pConfig
 975   )
 976 {
 977   UINT8  dbValue;
 978   UINT8  dbPortStatus;
 979   UINT32  abValue;
 980   UINT32  abValue1;
 981
 982   getChipSysMode (&dbPortStatus);
 983
 984   ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
 985   //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) {  // PwrGoodOut =1, PwrGoodEnB=1
 986   //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
 987
 988   //StrapStatus                               StrapOverride
 989   //   bit4                                            bit17
 990   //   bit6                                            bit12
 991   //   bit12                                           bit15
 992   //   bit15                                           bit16
 993   //   bit16                                           bit18
 994   ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue);
 995   abValue1 = abValue;
 996   if (abValue & BIT4) {
 997     abValue1 = (abValue1 & ~BIT4) | BIT17;
 998   }
 999   if (abValue & BIT6) {
1000     abValue1 = (abValue1 & ~BIT6) | BIT12;
1001   }
1002   if (abValue & BIT12) {
1003     abValue1 = (abValue1 & ~BIT12) | BIT15;
1004   }
1005   if (abValue & BIT15) {
1006     abValue1 = (abValue1 & ~BIT15) | BIT16;
1007   }
1008   if (abValue & BIT16) {
1009     abValue1 = (abValue1 & ~BIT16) | BIT18;
1010   }
1011   abValue1 |= BIT31;             // Overwrite enable
1012   if ((dbPortStatus & ChipSysEcEnable) == 0) {
1013     abValue1 |= BIT2;            // bit2- EcEnableStrap
1014   } else {
1015     abValue1 &= ~BIT2;           // bit2=0 EcEnableStrap
1016   }
1017   WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1);
1018   dbValue |= BIT6;               // PwrGoodOut =1
1019   dbValue &= ~BIT7;              // PwrGoodEnB =0
1020   WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);
1021
1022   dbValue = 06;
1023   WriteIO (0xcf9, AccWidthUint8, &dbValue);
1024   SbStall (0xffffffff);
1025 }
1026 #endif
1027
1028 #ifndef NO_HWM_SUPPORT
1029 /**
1030  * validateImcFirmware - Validate IMC Firmware.
1031  *
1032  *
1033  * @param[in] pConfig Southbridge configuration structure pointer.
1034  *
1035  */
1036 VOID
1037 hwmInit (
1038   IN       AMDSBCFG* pConfig
1039   )
1040 {
1041   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55);
1042   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55);
1043   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55);
1044   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55);
1045
1046   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06);
1047   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06);
1048   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06);
1049   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06);
1050   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06);
1051
1052   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01);
1053   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01);
1054   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01);
1055   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01);
1056   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01);
1057
1058   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05);
1059   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06);
1060   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42);
1061   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF);
1062   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F);
1063   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04);
1064   RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00);
1065 }
1066 #endif