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mb/google/puff/var/*: Set LAN device type back to pci
[coreboot.git] / src / mainboard / google / puff / variants / noibat / overridetree.cb
blob91a193977cc073c2dfd4bf659b244e23a36afc3f
1 chip soc/intel/cannonlake
2 register "power_limits_config" = "{
3 .tdp_pl1_override = 15,
4 .tdp_pl2_override = 51,
5 }"
6
7 # Auto-switch between X4 NVMe and X2 NVMe.
8 register "TetonGlacierMode" = "1"
9
10 register "SerialIoDevMode" = "{
11 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
12 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
13 [PchSerialIoIndexI2C2] = PchSerialIoPci,
14 [PchSerialIoIndexI2C3] = PchSerialIoPci,
15 [PchSerialIoIndexI2C4] = PchSerialIoPci,
16 [PchSerialIoIndexI2C5] = PchSerialIoPci,
17 [PchSerialIoIndexSPI0] = PchSerialIoPci,
18 [PchSerialIoIndexSPI1] = PchSerialIoPci,
19 [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
20 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
21 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
22 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
23 }"
24
25 # USB configuration
26 register "usb2_ports[0]" = "{
27 .enable = 1,
28 .ocpin = OC2,
29 .tx_bias = USB2_BIAS_0MV,
30 .tx_emp_enable = USB2_PRE_EMP_ON,
31 .pre_emp_bias = USB2_BIAS_11P25MV,
32 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
33 }" # Type-A Port 2
34 register "usb2_ports[1]" = "{
35 .enable = 1,
36 .ocpin = OC1,
37 .tx_bias = USB2_BIAS_0MV,
38 .tx_emp_enable = USB2_PRE_EMP_ON,
39 .pre_emp_bias = USB2_BIAS_28P15MV,
40 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
41 }" # Type-A Port 1
42 register "usb2_ports[2]" = "{
43 .enable = 1,
44 .ocpin = OC3,
45 .tx_bias = USB2_BIAS_0MV,
46 .tx_emp_enable = USB2_PRE_EMP_ON,
47 .pre_emp_bias = USB2_BIAS_28P15MV,
48 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
49 }" # Type-A Port 3
50 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
51 register "usb2_ports[5]" = "{
52 .enable = 1,
53 .ocpin = OC0,
54 .tx_bias = USB2_BIAS_0MV,
55 .tx_emp_enable = USB2_PRE_EMP_ON,
56 .pre_emp_bias = USB2_BIAS_28P15MV,
57 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
58 }" # Type-A port 0
59 register "usb2_ports[9]" = "{
60 .enable = 1,
61 .ocpin = OC_SKIP,
62 .tx_bias = USB2_BIAS_0MV,
63 .tx_emp_enable = USB2_PRE_EMP_ON,
64 .pre_emp_bias = USB2_BIAS_28P15MV,
65 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
66 }" # BT
67
68 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
69 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
70 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
71 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
72 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
73
74 # Bitmap for Wake Enable on USB attach/detach
75 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
76 USB_PORT_WAKE_ENABLE(2) |
77 USB_PORT_WAKE_ENABLE(3) |
78 USB_PORT_WAKE_ENABLE(6)"
79 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
80 USB_PORT_WAKE_ENABLE(2) |
81 USB_PORT_WAKE_ENABLE(3) |
82 USB_PORT_WAKE_ENABLE(5)"
83
84 # Enable eMMC HS400
85 register "ScsEmmcHs400Enabled" = "1"
86
87 # EMMC Tx CMD Delay
88 # Refer to EDS-Vol2-14.3.7.
89 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
90 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
91 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
92
93 # EMMC TX DATA Delay 1
94 # Refer to EDS-Vol2-14.3.8.
95 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
96 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
97 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
98
99 # EMMC TX DATA Delay 2
100 # Refer to EDS-Vol2-14.3.9.
101 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
102 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
103 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
104 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
105 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
106
107 # EMMC RX CMD/DATA Delay 1
108 # Refer to EDS-Vol2-14.3.10.
109 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
110 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
111 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
112 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
113 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
114
115 # EMMC RX CMD/DATA Delay 2
116 # Refer to EDS-Vol2-14.3.12.
117 # [17:16] stands for Rx Clock before Output Buffer,
118 # 00: Rx clock after output buffer,
119 # 01: Rx clock before output buffer,
120 # 10: Automatic selection based on working mode.
121 # 11: Reserved
122 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
123 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
124 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
125
126 # EMMC Rx Strobe Delay
127 # Refer to EDS-Vol2-14.3.11.
128 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
129 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
130 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
131
132 # Intel HDA - disable I2S Audio SSP1 and DMIC0 as noibat variant does not have them.
133 register "PchHdaAudioLinkSsp1" = "0"
134 register "PchHdaAudioLinkDmic0" = "0"
135
136 # Intel Common SoC Config
137 #+-------------------+---------------------------+
138 #| Field | Value |
139 #+-------------------+---------------------------+
140 #| GSPI0 | cr50 TPM. Early init is |
141 #| | required to set up a BAR |
142 #| | for TPM communication |
143 #| | before memory is up |
144 #| I2C0 | RFU |
145 #| I2C2 | PS175 |
146 #| I2C3 | MST |
147 #| I2C4 | Audio |
148 #+-------------------+---------------------------+
149 register "common_soc_config" = "{
150 .gspi[0] = {
151 .speed_mhz = 1,
152 .early_init = 1,
153 },
154 .i2c[0] = {
155 .speed = I2C_SPEED_FAST,
156 .rise_time_ns = 0,
157 .fall_time_ns = 0,
158 },
159 .i2c[2] = {
160 .speed = I2C_SPEED_FAST,
161 .rise_time_ns = 60,
162 .fall_time_ns = 60,
163 },
164 .i2c[3] = {
165 .speed = I2C_SPEED_FAST,
166 .rise_time_ns = 60,
167 .fall_time_ns = 60,
168 },
169 .i2c[4] = {
170 .speed = I2C_SPEED_FAST,
171 .rise_time_ns = 60,
172 .fall_time_ns = 60,
173 },
174 }"
175
176 # PCIe port 7 for LAN
177 register "PcieRpEnable[6]" = "1"
178 register "PcieRpLtrEnable[6]" = "1"
179 # PCIe port 11 (x2) for NVMe hybrid storage devices
180 register "PcieRpEnable[10]" = "1"
181 register "PcieRpLtrEnable[10]" = "1"
182 # Uses CLK SRC 0
183 register "PcieClkSrcUsage[0]" = "6"
184 register "PcieClkSrcClkReq[0]" = "0"
185
186 # GPIO for SD card detect
187 register "sdcard_cd_gpio" = "vSD3_CD_B"
188
189 # SATA port 1 Gen3 Strength
190 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
191 register "sata_port[1].TxGen3DeEmphEnable" = "1"
192 register "sata_port[1].TxGen3DeEmph" = "0x20"
193
194 device domain 0 on
195 device pci 04.0 on
196 chip drivers/intel/dptf
197 ## Active Policy
198 register "policies.active[0]" = "{.target=DPTF_CPU,
199 .thresholds={TEMP_PCT(94, 0),}}"
200 register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
201 .thresholds={TEMP_PCT(65, 90),
202 TEMP_PCT(52, 80),
203 TEMP_PCT(50, 70),
204 TEMP_PCT(48, 60),
205 TEMP_PCT(46, 50),
206 TEMP_PCT(44, 40),
207 TEMP_PCT(42, 0),}}"
208
209 ## Passive Policy
210 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
211 register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)"
212
213 ## Critical Policy
214 register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
215 register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
216
217 ## Power Limits Control
218 # PL1 is fixed at 15W, avg over 28-32s interval
219 # 15-51W PL2 in 1000mW increments, avg over 28-32s interval
220 register "controls.power_limits.pl1" = "{
221 .min_power = 15000,
222 .max_power = 15000,
223 .time_window_min = 28 * MSECS_PER_SEC,
224 .time_window_max = 32 * MSECS_PER_SEC,
225 .granularity = 200,}"
226 register "controls.power_limits.pl2" = "{
227 .min_power = 15000,
228 .max_power = 51000,
229 .time_window_min = 28 * MSECS_PER_SEC,
230 .time_window_max = 32 * MSECS_PER_SEC,
231 .granularity = 1000,}"
232
233 ## Charger Performance Control (Control, mA)
234 register "controls.charger_perf[0]" = "{ 255, 1700 }"
235 register "controls.charger_perf[1]" = "{ 24, 1500 }"
236 register "controls.charger_perf[2]" = "{ 16, 1000 }"
237 register "controls.charger_perf[3]" = "{ 8, 500 }"
238
239 ## Fan Performance Control (Percent, Speed, Noise, Power)
240 register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
241 register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }"
242 register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }"
243 register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }"
244 register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }"
245 register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }"
246 register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }"
247 register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }"
248 register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }"
249 register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
250
251 # Fan options
252 register "options.fan.fine_grained_control" = "1"
253 register "options.fan.step_size" = "2"
254
255 device generic 0 on end
256 end
257 end # DPTF 0x1903
258 device pci 14.0 on
259 chip drivers/usb/acpi
260 device usb 0.0 on
261 chip drivers/usb/acpi
262 register "desc" = ""USB2 Type-A Front Left""
263 register "type" = "UPC_TYPE_A"
264 register "group" = "ACPI_PLD_GROUP(0, 0)"
265 device usb 2.0 on end
266 end
267 chip drivers/usb/acpi
268 register "desc" = ""USB2 Type-C Port Rear""
269 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
270 register "group" = "ACPI_PLD_GROUP(1, 3)"
271 device usb 2.1 on end
272 end
273 chip drivers/usb/acpi
274 register "desc" = ""USB2 Type-A Front Right""
275 register "type" = "UPC_TYPE_A"
276 register "group" = "ACPI_PLD_GROUP(0, 1)"
277 device usb 2.2 on end
278 end
279 chip drivers/usb/acpi
280 register "desc" = ""USB2 Type-A Rear Right""
281 register "type" = "UPC_TYPE_A"
282 register "group" = "ACPI_PLD_GROUP(1, 2)"
283 device usb 2.3 on end
284 end
285 chip drivers/usb/acpi
286 register "desc" = ""USB2 Type-A Rear Left""
287 register "type" = "UPC_TYPE_A"
288 register "group" = "ACPI_PLD_GROUP(1, 0)"
289 device usb 2.5 on end
290 end
291 chip drivers/usb/acpi
292 device usb 2.6 off end
293 end
294 chip drivers/usb/acpi
295 register "desc" = ""USB3 Type-A Front Left""
296 register "type" = "UPC_TYPE_USB3_A"
297 register "group" = "ACPI_PLD_GROUP(0, 0)"
298 device usb 3.0 on end
299 end
300 chip drivers/usb/acpi
301 register "desc" = ""USB3 Type-A Front Right""
302 register "type" = "UPC_TYPE_USB3_A"
303 register "group" = "ACPI_PLD_GROUP(0, 1)"
304 device usb 3.1 on end
305 end
306 chip drivers/usb/acpi
307 register "desc" = ""USB3 Type-A Rear Right""
308 register "type" = "UPC_TYPE_USB3_A"
309 register "group" = "ACPI_PLD_GROUP(1, 2)"
310 device usb 3.2 on end
311 end
312 chip drivers/usb/acpi
313 register "desc" = ""USB3 Type-C Rear""
314 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
315 register "group" = "ACPI_PLD_GROUP(1, 3)"
316 device usb 3.3 on end
317 end
318 chip drivers/usb/acpi
319 register "desc" = ""USB3 Type-A Rear Left""
320 register "type" = "UPC_TYPE_USB3_A"
321 register "group" = "ACPI_PLD_GROUP(1, 0)"
322 device usb 3.4 on end
323 end
324 end
325 end
326 end # USB xHCI
327 device pci 15.0 off
328 # RFU - Reserved for Future Use.
329 end # I2C #0
330 device pci 15.1 off end # I2C #1
331 device pci 15.2 on
332 chip drivers/i2c/generic
333 register "hid" = ""1AF80175""
334 register "name" = ""PS17""
335 register "desc" = ""Parade PS175""
336 device i2c 4a on end
337 end
338 end # I2C #2, PCON PS175.
339 device pci 15.3 on
340 chip drivers/i2c/generic
341 register "hid" = ""10EC2142""
342 register "name" = ""RTD2""
343 register "desc" = ""Realtek RTD2142""
344 device i2c 4a on end
345 end
346 end # I2C #3, Realtek RTD2142.
347 device pci 16.0 on end # Management Engine Interface 1
348 device pci 19.0 on
349 chip drivers/i2c/generic
350 register "hid" = ""10EC5682""
351 register "name" = ""RT58""
352 register "desc" = ""Realtek RT5682""
353 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
354 register "property_count" = "1"
355 # Set the jd_src to RT5668_JD1 for jack detection
356 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
357 register "property_list[0].name" = ""realtek,jd-src""
358 register "property_list[0].integer" = "1"
359 device i2c 1a on end
360 end
361 end #I2C #4
362 device pci 1a.0 on end # eMMC
363 device pci 1c.6 on
364 chip drivers/net
365 register "customized_leds" = "0x05af"
366 register "wake" = "GPE0_DW1_07" # GPP_C7
367 register "device_index" = "0"
368 register "enable_aspm_l1_2" = "1"
369 device pci 00.0 on end
370 end
371 register "PcieRpSlotImplemented[6]" = "1"
372 end # RTL8111H Ethernet NIC
373 device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
374 register "PcieRpSlotImplemented[10]" = "1"
375 end
376 device pci 1e.3 off end # GSPI #1
377 end
378
379 # VR Settings Configuration for 4 Domains
380 #+----------------+-------+-------+-------+-------+
381 #| Domain/Setting | SA | IA | GTUS | GTS |
382 #+----------------+-------+-------+-------+-------+
383 #| Psi1Threshold | 20A | 20A | 20A | 20A |
384 #| Psi2Threshold | 5A | 5A | 5A | 5A |
385 #| Psi3Threshold | 1A | 1A | 1A | 1A |
386 #| Psi3Enable | 1 | 1 | 1 | 1 |
387 #| Psi4Enable | 1 | 1 | 1 | 1 |
388 #| ImonSlope | 0 | 0 | 0 | 0 |
389 #| ImonOffset | 0 | 0 | 0 | 0 |
390 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
391 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
392 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
393 #+----------------+-------+-------+-------+-------+
394 #Note: IccMax settings are moved to SoC code
395 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
396 .vr_config_enable = 1,
397 .psi1threshold = VR_CFG_AMP(20),
398 .psi2threshold = VR_CFG_AMP(5),
399 .psi3threshold = VR_CFG_AMP(1),
400 .psi3enable = 1,
401 .psi4enable = 1,
402 .imon_slope = 0x0,
403 .imon_offset = 0x0,
404 .icc_max = 0,
405 .voltage_limit = 1520,
406 .ac_loadline = 1004,
407 .dc_loadline = 1004,
408 }"
409
410 register "domain_vr_config[VR_IA_CORE]" = "{
411 .vr_config_enable = 1,
412 .psi1threshold = VR_CFG_AMP(20),
413 .psi2threshold = VR_CFG_AMP(5),
414 .psi3threshold = VR_CFG_AMP(1),
415 .psi3enable = 1,
416 .psi4enable = 1,
417 .imon_slope = 0x0,
418 .imon_offset = 0x0,
419 .icc_max = 0,
420 .voltage_limit = 1520,
421 .ac_loadline = 181,
422 .dc_loadline = 181,
423 }"
424
425 register "domain_vr_config[VR_GT_UNSLICED]" = "{
426 .vr_config_enable = 1,
427 .psi1threshold = VR_CFG_AMP(20),
428 .psi2threshold = VR_CFG_AMP(5),
429 .psi3threshold = VR_CFG_AMP(1),
430 .psi3enable = 1,
431 .psi4enable = 1,
432 .imon_slope = 0x0,
433 .imon_offset = 0x0,
434 .icc_max = 0,
435 .voltage_limit = 1520,
436 .ac_loadline = 319,
437 .dc_loadline = 319,
438 }"
439
440 register "domain_vr_config[VR_GT_SLICED]" = "{
441 .vr_config_enable = 1,
442 .psi1threshold = VR_CFG_AMP(20),
443 .psi2threshold = VR_CFG_AMP(5),
444 .psi3threshold = VR_CFG_AMP(1),
445 .psi3enable = 1,
446 .psi4enable = 1,
447 .imon_slope = 0x0,
448 .imon_offset = 0x0,
449 .icc_max = 0,
450 .voltage_limit = 1520,
451 .ac_loadline = 319,
452 .dc_loadline = 319,
453 }"
454
455 end
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