src/arch/mips/include/arch/cpu.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Imagination Technologies
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 #ifndef __MIPS_ARCH_CPU_H
  21 #define __MIPS_ARCH_CPU_H
  22
  23 #define asmlinkage
  24
  25 #ifndef __PRE_RAM__
  26
  27 #include <device/device.h>
  28
  29 struct cpu_driver {
  30         struct device_operations *ops;
  31         struct cpu_device_id *id_table;
  32 };
  33
  34 struct thread;
  35
  36 struct cpu_info {
  37         device_t cpu;
  38         unsigned long index;
  39 };
  40
  41 #endif /* !__PRE_RAM__ */
  42
  43 /***************************************************************************
  44  * The following section was copied from arch/mips/include/asm/mipsregs.h in
  45  * the 3.14 kernel tree.
  46  */
  47
  48 /*
  49  * Macros to access the system control coprocessor
  50  */
  51
  52 #define __read_32bit_c0_register(source, sel)                           \
  53 ({ int __res;                                                           \
  54         if (sel == 0)                                                   \
  55                 __asm__ __volatile__(                                   \
  56                         "mfc0\t%0, " #source "\n\t"                     \
  57                         : "=r" (__res));                                \
  58         else                                                            \
  59                 __asm__ __volatile__(                                   \
  60                         ".set\tmips32\n\t"                              \
  61                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
  62                         ".set\tmips0\n\t"                               \
  63                         : "=r" (__res));                                \
  64         __res;                                                          \
  65 })
  66
  67 #define __write_32bit_c0_register(register, sel, value)                 \
  68 do {                                                                    \
  69         if (sel == 0)                                                   \
  70                 __asm__ __volatile__(                                   \
  71                         "mtc0\t%z0, " #register "\n\t"                  \
  72                         : : "Jr" ((unsigned int)(value)));              \
  73         else                                                            \
  74                 __asm__ __volatile__(                                   \
  75                         ".set\tmips32\n\t"                              \
  76                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
  77                         ".set\tmips0"                                   \
  78                         : : "Jr" ((unsigned int)(value)));              \
  79 } while (0)
  80
  81 /* Shortcuts to access various internal registers, keep adding as needed. */
  82 #define read_c0_index()         __read_32bit_c0_register($0, 0)
  83 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, (val))
  84
  85 #define read_c0_entrylo0()      __read_32bit_c0_register($2, 0)
  86 #define write_c0_entrylo0(val)  __write_32bit_c0_register($2, 0, (val))
  87
  88 #define read_c0_entrylo1()      __read_32bit_c0_register($3, 0)
  89 #define write_c0_entrylo1(val)  __write_32bit_c0_register($3, 0, (val))
  90
  91 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
  92 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, (val))
  93
  94 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
  95 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, (val))
  96
  97 #define read_c0_count()         __read_32bit_c0_register($9, 0)
  98 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, (val))
  99
 100 #define read_c0_entryhi()       __read_32bit_c0_register($10, 0)
 101 #define write_c0_entryhi(val)   __write_32bit_c0_register($10, 0, (val))
 102
 103 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
 104 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, (val))
 105
 106 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
 107 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, (val))
 108
 109 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
 110 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, (val))
 111
 112 #define read_c0_l23taglo()      __read_32bit_c0_register($28, 4)
 113 #define write_c0_l23taglo(val)  __write_32bit_c0_register($28, 4, (val))
 114
 115
 116 #define C0_ENTRYLO_PFN_SHIFT 6
 117 #define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */
 118 #define C0_ENTRYLO_D (0x1 << 2) /* Writeable */
 119 #define C0_ENTRYLO_V (0x1 << 1) /* Valid */
 120 #define C0_ENTRYLO_G (0x1 << 0) /* Global */
 121
 122 #define C0_PAGEMASK_SHIFT 13
 123 #define C0_PAGEMASK_MASK 0xffff
 124
 125 #define C0_WIRED_MASK 0x3f
 126
 127 #define C0_CAUSE_DC (1 << 27)
 128
 129 #define C0_CONFIG1_MMUSIZE_SHIFT 25
 130 #define C0_CONFIG1_MMUSIZE_MASK 0x3f
 131
 132 /* Hazard handling */
 133 static inline void __nop(void)
 134 {
 135         __asm__ __volatile__("nop");
 136 }
 137
 138 static inline void __ssnop(void)
 139 {
 140         __asm__ __volatile__("sll\t$0, $0, 1");
 141 }
 142
 143 #define mtc0_tlbw_hazard()                                              \
 144 do {                                                                    \
 145         __nop();                                                        \
 146         __nop();                                                        \
 147 } while (0)
 148
 149 #define tlbw_use_hazard()                                               \
 150 do {                                                                    \
 151         __nop();                                                        \
 152         __nop();                                                        \
 153         __nop();                                                        \
 154 } while (0)
 155
 156 #define tlb_probe_hazard()                                              \
 157 do {                                                                    \
 158         __nop();                                                        \
 159         __nop();                                                        \
 160         __nop();                                                        \
 161 } while (0)
 162
 163 #define back_to_back_c0_hazard()                                        \
 164 do {                                                                    \
 165         __ssnop();                                                      \
 166         __ssnop();                                                      \
 167         __ssnop();                                                      \
 168 } while (0)
 169 /**************************************************************************/
 170
 171 #endif /* __MIPS_ARCH_CPU_H */