src/mainboard/intel/kunimitsu/gpio.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  * Copyright (C) 2015 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef MAINBOARD_GPIO_H
  18 #define MAINBOARD_GPIO_H
  19
  20 #include <soc/gpe.h>
  21 #include <soc/gpio.h>
  22
  23 /* EC in RW */
  24 #define GPIO_EC_IN_RW           GPP_C6
  25
  26 /* BIOS Flash Write Protect */
  27 #define GPIO_PCH_WP             GPP_C23
  28
  29 /* Memory configuration board straps */
  30 #define GPIO_MEM_CONFIG_0       GPP_C12
  31 #define GPIO_MEM_CONFIG_1       GPP_C13
  32 #define GPIO_MEM_CONFIG_2       GPP_C14
  33 #define GPIO_MEM_CONFIG_3       GPP_C15
  34
  35 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
  36 #define GPE_EC_WAKE             GPE0_LAN_WAK
  37
  38 /* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
  39 #define GPE_WLAN_WAKE           GPE0_DW0_16
  40
  41 /* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
  42 #define GPE_TOUCHPAD_WAKE       GPE0_DW0_05
  43
  44 /* Input device interrupt configuration */
  45 #define TOUCHPAD_INT_L          GPP_B3_IRQ
  46 #define TOUCHSCREEN_INT_L       GPP_E7_IRQ
  47 #define MIC_INT_L               GPP_F10_IRQ
  48
  49 /* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
  50 #define EC_SCI_GPI              GPE0_DW2_16
  51 #define EC_SMI_GPI              GPP_E15
  52
  53 /*
  54  * GPP_E3 is AUDIO_DB_ID.
  55  * It is a dual purpose GPIO, used for Audio Daughter
  56  * Board Identification & to control the shutdown mode pin
  57  * of the Maxim amp.
  58  */
  59 #define AUDIO_DB_ID             GPP_E3
  60
  61 /* SD controller needs additional card detect GPIO to support RTD3 */
  62 #define GPIO_SD_CARD_DETECT     GPP_A7
  63
  64 #ifndef __ACPI__
  65 /* Pad configuration in ramstage. */
  66 static const struct pad_config gpio_table[] = {
  67 /* EC_PCH_RCIN */       PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
  68 /* LPC_LAD_0 */         PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
  69 /* LPC_LAD_1 */         PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
  70 /* LPC_LAD_2 */         PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
  71 /* LPC_LAD_3 */         PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
  72 /* LPC_FRAME */         PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
  73 /* LPC_SERIRQ */        PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
  74 /* SD_CD_WAKE */        PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP),
  75 /* LPC_CLKRUN */        PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  76 /* EC_LPC_CLK */        PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
  77 /* PCH_LPC_CLK */       PAD_CFG_NC(GPP_A10),
  78 /* EC_HID_INT */        PAD_CFG_NC(GPP_A11),
  79 /* ISH_KB_PROX_INT */   PAD_CFG_NC(GPP_A12),
  80 /* PCH_SUSPWRACB */     PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  81 /* PM_SUS_STAT */       PAD_CFG_NC(GPP_A14),
  82 /* PCH_SUSACK */        PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  83 /* SD_1P8_SEL */        PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  84 /* SD_PWR_EN */         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  85 /* ACCEL INTERRUPT */   PAD_CFG_NC(GPP_A18),
  86 /* ISH_GP1 */           PAD_CFG_NC(GPP_A19),
  87 /* GYRO_DRDY */         PAD_CFG_NC(GPP_A20),
  88 /* FLIP_ACCEL_INT */    PAD_CFG_NC(GPP_A21),
  89 /* GYRO_INT */          PAD_CFG_NC(GPP_A22),
  90 /* ISH_GP5 */           PAD_CFG_NC(GPP_A23),
  91 /* CORE_VID0 */         PAD_CFG_NC(GPP_B0),
  92 /* CORE_VID1 */         PAD_CFG_NC(GPP_B1),
  93 /* HSJ_MIC_DET */       PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP),
  94 /* TRACKPAD_INT */      PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
  95 /* BT_RF_KILL */        PAD_CFG_NC(GPP_B4),
  96 /* SRCCLKREQ0# */       PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
  97 /* WIFI_CLK_REQ */      PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  98 /* KEPLR_CLK_REQ */     PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  99 /* AUDIO_INT_WAK */     PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),
 100 /* SSD_CLK_REQ */       PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
 101 /* SRCCLKREQ5# */       PAD_CFG_NC(GPP_B10),
 102 /* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
 103 /* PM_SLP_S0 */         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 104 /* PCH_PLT_RST */       PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 105 /* PCH_BUZZER */        PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),
 106 /* GSPI0_CS# */         PAD_CFG_NC(GPP_B15),
 107 /* WLAN_PCIE_WAKE */    PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
 108 /* SSD_PCIE_WAKE */     PAD_CFG_NC(GPP_B17),
 109 /* GSPI0_MOSI */        PAD_CFG_NC(GPP_B18),
 110 /* CCODEC_SPI_CS */     PAD_CFG_NC(GPP_B19),
 111 /* CODEC_SPI_CLK */     PAD_CFG_NC(GPP_B20),
 112 /* CODEC_SPI_MISO */    PAD_CFG_NC(GPP_B21),
 113 /* CODEC_SPI_MOSI */    PAD_CFG_NC(GPP_B22),
 114 /* SM1ALERT# */         PAD_CFG_NC(GPP_B23),
 115 /* SMB_CLK */           PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 116 /* SMB_DATA */          PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 117 /* SMBALERT# */         PAD_CFG_GPO(GPP_C2, 0, DEEP),
 118 /* M2_WWAN_PWREN */     PAD_CFG_NC(GPP_C3),
 119 /* SML0DATA */          PAD_CFG_NC(GPP_C4),
 120 /* SML0ALERT# */        PAD_CFG_NC(GPP_C5),
 121 /* EC_IN_RW */          PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),
 122 /* USB_CTL */           PAD_CFG_NC(GPP_C7),
 123 /* UART0_RXD */         PAD_CFG_NC(GPP_C8),
 124 /* UART0_TXD */         PAD_CFG_NC(GPP_C9),
 125 /* NFC_RST* */          PAD_CFG_NC(GPP_C10),
 126 /* EN_PP3300_KEPLER */  PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
 127 /* PCH_MEM_CFG0 */      PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 128 /* PCH_MEM_CFG1 */      PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
 129 /* PCH_MEM_CFG2 */      PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
 130 /* PCH_MEM_CFG3 */      PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 131 /* I2C0_SDA */          PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
 132 /* I2C0_SCL */          PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
 133 /* I2C1_SDA */          PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 134 /* I2C1_SCL */          PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 135 /* GD_UART2_RXD */      PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 136 /* GD_UART2_TXD */      PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 137 /* TCH_PNL_PWREN */     PAD_CFG_GPO(GPP_C22, 1, DEEP),
 138 /* SPI_WP_STATUS */     PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 139 /* ITCH_SPI_CS */       PAD_CFG_NC(GPP_D0),
 140 /* ITCH_SPI_CLK */      PAD_CFG_NC(GPP_D1),
 141 /* ITCH_SPI_MISO_1 */   PAD_CFG_NC(GPP_D2),
 142 /* ITCH_SPI_MISO_0 */   PAD_CFG_NC(GPP_D3),
 143 /* CAM_FLASH_STROBE */  PAD_CFG_NC(GPP_D4),
 144 /* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),
 145 /* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
 146 /* SH_I2C1_SDA */       PAD_CFG_NC(GPP_D7),
 147 /* SH_I2C1_SCL */       PAD_CFG_NC(GPP_D8),
 148 /* ISH_SPI_CSB */       PAD_CFG_NC(GPP_D9),
 149 /* USB_A0_ILIM_SEL */   PAD_CFG_GPO(GPP_D10, 0, DEEP),
 150 /* USB_A1_ILIM_SEL */   PAD_CFG_GPO(GPP_D11, 0, DEEP),
 151 /* EN_PP3300_DX_CAM */  PAD_CFG_NC(GPP_D12),
 152 /* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13),
 153 /* ISH_UART0_TXD */     PAD_CFG_NC(GPP_D14),
 154 /* ISH_UART0_RTS */     PAD_CFG_NC(GPP_D15),
 155 /* ISH_UART0_CTS */     PAD_CFG_NC(GPP_D16),
 156 /* DMIC_CLK_1 */        PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 157 /* DMIC_DATA_1 */       PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 158 /* DMIC_CLK_0 */        PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 159 /* DMIC_DATA_0 */       PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 160 /* ITCH_SPI_D2 */       PAD_CFG_NC(GPP_D21),
 161 /* ITCH_SPI_D3 */       PAD_CFG_NC(GPP_D22),
 162 /* I2S_MCLK */          PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 163 /* SPI_TPM_IRQ */       PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
 164 /* SATAXPCIE1 */        PAD_CFG_NC(GPP_E1),
 165 /* SSD_PEDET */         PAD_CFG_NC(GPP_E2),
 166 /* AUDIO_DB_ID */       PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP),
 167 /* SSD_SATA_DEVSLP */   PAD_CFG_NC(GPP_E4),
 168 /* SATA_DEVSLP1 */      PAD_CFG_NC(GPP_E5),
 169 /* SATA_DEVSLP2 */      PAD_CFG_NC(GPP_E6),
 170 /* TCH_PNL_INTR* */     PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
 171 /* SATALED# */          PAD_CFG_NC(GPP_E8),
 172 /* USB2_OC_0 */         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 173 /* USB2_OC_1 */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 174 /* USB2_OC_2 */         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 175 /* USB2_OC_3 */         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 176 /* DDI1_HPD */          PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 177 /* DDI2_HPD */          PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 178 /* EC_SMI */            PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
 179 /* EC_SCI */            PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
 180 /* EDP_HPD */           PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 181 /* DDPB_CTRLCLK */      PAD_CFG_NC(GPP_E18),
 182 /* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
 183 /* DDPC_CTRLCLK */      PAD_CFG_NC(GPP_E20),
 184 /* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 185
 186 /* DDPD_CTRLCLK */      PAD_CFG_NC(GPP_E22),
 187 /* TCH_PNL_RST */       PAD_CFG_GPO(GPP_E23, 1, DEEP),
 188 /* I2S2_SCLK */         PAD_CFG_NC(GPP_F0),
 189 /* I2S2_SFRM */         PAD_CFG_NC(GPP_F1),
 190 /* I2S2_TXD */          PAD_CFG_NC(GPP_F2),
 191 /* I2S2_RXD */          PAD_CFG_NC(GPP_F3),
 192 /* I2C2_SDA */          PAD_CFG_NC(GPP_F4),
 193 /* I2C2_SCL */          PAD_CFG_NC(GPP_F5),
 194 /* I2C3_SDA */          PAD_CFG_NC(GPP_F6),
 195 /* I2C3_SCL */          PAD_CFG_NC(GPP_F7),
 196 /* I2C4_SDA */          PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
 197 /* I2C4_SDA */          PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
 198 /* AUDIO_IRQ */         PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
 199 /* AUDIO_IRQ */         PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
 200 /* EMMC_CMD */          PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 201 /* EMMC_DATA0 */        PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 202 /* EMMC_DATA1 */        PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 203 /* EMMC_DATA2 */        PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 204 /* EMMC_DATA3 */        PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 205 /* EMMC_DATA4 */        PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 206 /* EMMC_DATA5 */        PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 207 /* EMMC_DATA6 */        PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 208 /* EMMC_DATA7 */        PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 209 /* EMMC_RCLK */         PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 210 /* EMMC_CLK */          PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 211 /* BOOT_BEEP */         PAD_CFG_GPO(GPP_F23, 0, DEEP),
 212 /* SD_CMD */            PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 213 /* SD_DATA0 */          PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 214 /* SD_DATA1 */          PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 215 /* SD_DATA2 */          PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 216 /* SD_DATA3 */          PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 217 /* SD_CD# */            PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
 218 /* SD_CLK */            PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 219 /* SD_WP */             PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
 220 /* PCH_BATLOW */        PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 221 /* EC_PCH_ACPRESENT */  PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 222 /* EC_PCH_WAKE */       PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 223 /* EC_PCH_PWRBTN */     PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
 224 /* PM_SLP_S3# */        PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 225 /* PM_SLP_S4# */        PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 226 /* PM_SLP_SA# */        PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 227 /* GPD7 */              PAD_CFG_NC(GPD7),
 228 /* PM_SUSCLK */         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 229 /* PCH_SLP_WLAN# */     PAD_CFG_NC(GPD9),
 230 /* PM_SLP_S5# */        PAD_CFG_NC(GPD10),
 231 /* LANPHYC */           PAD_CFG_NC(GPD11),
 232 };
 233
 234 /* Early pad configuration in romstage. */
 235 static const struct pad_config early_gpio_table[] = {
 236 /* SRCCLKREQ2# */       PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
 237 /* SPI_WP_STATUS */     PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 238 /* UART0_CTS# */        PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
 239 };
 240
 241 #endif
 242
 243 #endif