1 chip soc
/intel
/cannonlake
3 # Enable Enhanced Intel SpeedStep
4 register
"eist_enable" = "1"
8 register
"panel_cfg" = "{
9 .up_delay_ms = 0, // T3
10 .backlight_on_delay_ms = 0, // T7
11 .backlight_off_delay_ms = 0, // T9
12 .down_delay_ms = 0, // T10
13 .cycle_delay_ms = 500, // T12
14 .backlight_pwm_hz = 200, // PWM
18 register
"enable_c6dram" = "1"
19 register
"SaGv" = "SaGv_Enabled"
23 register
"SerialIoDevMode" = "{
24 [PchSerialIoIndexI2C0] = PchSerialIoPci,
25 [PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
26 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
30 register
"PchPmSlpS3MinAssert" = "2" #
50ms
31 register
"PchPmSlpS4MinAssert" = "3" #
1s
32 register
"PchPmSlpSusMinAssert" = "3" #
500ms
33 register
"PchPmSlpAMinAssert" = "3" #
2s
37 # Note that GPE events called out in ASL code rely on this
38 # route. i.e.
If this route changes
then the affected GPE
39 # offset bits also need
to be changed.
40 # sudo devmem2
0xfe001920 (pmc_bar
+ GPIO_GPE_CFG
)
41 register
"gpe0_dw0" = "PMC_GPP_B"
42 register
"gpe0_dw1" = "PMC_GPP_C"
43 register
"gpe0_dw2" = "PMC_GPP_E"
46 register
"PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
47 register
"PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
48 register
"PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
49 register
"PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
50 register
"PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
53 device cpu_cluster
0 on
58 device pci
00.0 on
end # Host Bridge
59 device pci
02.0 on
end # Integrated Graphics Device
60 device pci
04.0 on # SA Thermal Device
61 register
"Device4Enable" = "1"
63 device pci
12.0 off
end # Thermal Subsystem
64 device pci
12.5 off
end # UFS SCS
65 device pci
12.6 off
end # GSPI #
2
66 device pci
14.0 on # USB xHCI
67 # Motherboard USB
Type C
68 register
"usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
69 register
"usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
72 register
"usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
73 register
"usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
75 # Daughterboard SD Card
76 register
"usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
78 # Daughterboard USB
3.0
79 register
"usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
80 register
"usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
83 register
"usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
86 register
"usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
88 device pci
14.1 off
end # USB xDCI
(OTG
)
89 device pci
14.3 on # CNVi
90 chip drivers
/wifi
/generic
91 register
"wake" = "GPE0_PME_B0"
92 device generic
0 on
end
95 device pci
14.5 off
end # SDCard
96 device pci
15.0 on # I2C0
98 register
"generic.hid" = ""STAR0001
""
99 register
"generic.desc" = ""Touchpad
""
100 register
"generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
101 register
"generic.probed" = "1"
102 register
"hid_desc_reg_offset" = "0x20"
106 device pci
15.1 off
end # I2C1
107 device pci
15.2 off
end # I2C2
108 device pci
15.3 off
end # I2C3
109 device pci
16.0 on
end # Management Engine Interface
1
110 device pci
16.1 off
end # Management Engine Interface
2
111 device pci
16.2 off
end # Management Engine IDE
-R
112 device pci
16.3 off
end # Management Engine KT Redirection
113 device pci
16.4 off
end # Management Engine Interface
3
114 device pci
16.5 off
end # Management Engine Interface
4
115 device pci
17.0 on # SATA
116 register
"SataSalpSupport" = "1"
118 register
"SataPortsEnable[1]" = "1"
119 register
"SataPortsDevSlp[1]" = "1"
121 device pci
19.0 on
end # I2C4
122 device pci
19.1 off
end # I2C5
123 device pci
19.2 on
end # UART #
2
124 device pci
1a
.0 off
end # eMMC
125 device pci
1c
.0 off
end # PCI Express Port
1
126 device pci
1c
.1 off
end # PCI Express Port
2
127 device pci
1c
.2 off
end # PCI Express Port
3
128 device pci
1c
.3 off
end # PCI Express Port
4
129 device pci
1c
.4 off
end # PCI Express Port
5
130 device pci
1c
.5 off
end # PCI Express Port
6
131 device pci
1c
.6 off
end # PCI Express Port
7
132 device pci
1c
.7 off
end # PCI Express Port
8
133 device pci
1d
.0 on # PCI Express Port
9 (SSD x4
)
134 register
"PcieRpSlotImplemented[8]" = "1"
135 register
"PcieRpEnable[8]" = "1"
136 register
"PcieRpLtrEnable[8]" = "1"
137 register
"PcieClkSrcUsage[1]" = "0x08"
138 register
"PcieClkSrcClkReq[1]" = "1"
139 smbios_slot_desc
"SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
141 device pci
1d
.1 off
end # PCI Express Port
10
142 device pci
1d
.2 off
end # PCI Express Port
11
143 device pci
1d
.3 off
end # PCI Express Port
12
144 device pci
1e
.0 off
end # UART #
0
145 device pci
1e
.1 off
end # UART #
1
146 device pci
1e
.2 off
end # GSPI #
0
147 device pci
1e
.3 off
end # GSPI #
1
148 device pci
1f
.0 on # LPC Interface
149 register
"gen1_dec" = "0x000c0681"
150 register
"gen2_dec" = "0x000c1641"
151 register
"gen3_dec" = "0x00fc0201"
152 register
"gen4_dec" = "0x000c0081"
154 chip ec
/starlabs
/merlin
156 device pnp
4e
.00 on
end # IO Interface
157 device pnp
4e
.01 off
end # Com
1
158 device pnp
4e
.02 off
end # Com
2
159 device pnp
4e
.04 off
end # System Wake
-Up
160 device pnp
4e
.05 off
end # PS
/2 Mouse
161 device pnp
4e
.06 on # PS
/2 Keyboard
166 device pnp
4e
.0a off
end # Consumer IR
167 device pnp
4e
.0f off
end # Shared Memory
/Flash Interface
168 device pnp
4e
.10 off
end # RTC
-like Timer
169 device pnp
4e
.11 off
end # Power Management Channel
1
170 device pnp
4e
.12 off
end # Power Management Channel
2
171 device pnp
4e
.13 off
end # Serial Peripheral Interface
172 device pnp
4e
.14 off
end # Platform EC Interface
173 device pnp
4e
.17 off
end # Power Management Channel
3
174 device pnp
4e
.18 off
end # Power Management Channel
4
175 device pnp
4e
.19 off
end # Power Management Channel
5
178 device pci
1f
.1 off
end # P2SB
179 device pci
1f
.2 hidden
end # Power Management Controller
180 device pci
1f
.3 on # Intel HDA
181 register
"PchHdaAudioLinkHda" = "1"
183 device pci
1f
.4 on
end # SMBus
184 device pci
1f
.5 on
end # PCH SPI
185 device pci
1f
.6 off
end # GbE
188 device mmio
0xfed40000 on
end
