src/soc/mediatek/mt8183/rtc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2018 MediaTek Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <delay.h>
  17 #include <halt.h>
  18 #include <soc/rtc_common.h>
  19 #include <soc/rtc.h>
  20 #include <soc/mt6358.h>
  21 #include <soc/pmic_wrap.h>
  22
  23 #define RTC_GPIO_USER_MASK        ((1 << 13) - (1 << 8))
  24
  25 /* initialize rtc setting of using dcxo clock */
  26 static int rtc_enable_dcxo(void)
  27 {
  28         u16 bbpu, con, osc32con, sec;
  29
  30         rtc_read(RTC_BBPU, &bbpu);
  31         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
  32         rtc_write_trigger();
  33
  34         mdelay(1);
  35         if (!rtc_writeif_unlock()) { /* Unlock for reload */
  36                 rtc_info("rtc_writeif_unlock() failed\n");
  37                 return 0;
  38         }
  39
  40         rtc_read(RTC_OSC32CON, &osc32con);
  41         osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
  42                       | RTC_GPS_CKOUT_EN);
  43         osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
  44                     | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
  45         if (!rtc_xosc_write(osc32con)) {
  46                 rtc_info("rtc_xosc_write() failed\n");
  47                 return 0;
  48         }
  49
  50         rtc_read(RTC_CON, &con);
  51         rtc_read(RTC_OSC32CON, &osc32con);
  52         rtc_read(RTC_AL_SEC, &sec);
  53         rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);
  54
  55         return 1;
  56 }
  57
  58 /* initialize rtc related gpio */
  59 static int rtc_gpio_init(void)
  60 {
  61         u16 con;
  62
  63         /* RTC_32K1V8 clock change from 128k div 4 source
  64          * to RTC 32k source
  65          */
  66         pwrap_write_field(PMIC_RG_TOP_CKSEL_CON0_SET, 0x1, 0x1, 3);
  67
  68         /* Export 32K clock RTC_32K1V8_1 */
  69         pwrap_write_field(PMIC_RG_TOP_CKPDN_CON1_CLR, 0x1, 0x1, 1);
  70
  71         /* Export 32K clock RTC_32K2V8 */
  72         rtc_read(RTC_CON, &con);
  73         con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
  74                 | RTC_CON_XOSC32_LPEN);
  75         con |= (RTC_CON_GPEN | RTC_CON_GOE);
  76         con &= ~(RTC_CON_F32KOB);
  77         rtc_write(RTC_CON, con);
  78
  79         return rtc_write_trigger();
  80 }
  81
  82 /* set xosc mode */
  83 void rtc_osc_init(void)
  84 {
  85         /* enable 32K export */
  86         rtc_gpio_init();
  87 }
  88
  89 /* enable lpd subroutine */
  90 static int rtc_lpen(u16 con)
  91 {
  92         con &= ~RTC_CON_LPRST;
  93         rtc_write(RTC_CON, con);
  94         if (!rtc_write_trigger())
  95                 return 0;
  96
  97         con |= RTC_CON_LPRST;
  98         rtc_write(RTC_CON, con);
  99         if (!rtc_write_trigger())
 100                 return 0;
 101
 102         con &= ~RTC_CON_LPRST;
 103         rtc_write(RTC_CON, con);
 104         if (!rtc_write_trigger())
 105                 return 0;
 106
 107         return 1;
 108 }
 109
 110 /* low power detect setting */
 111 static int rtc_lpd_init(void)
 112 {
 113         u16 con, sec;
 114
 115         /* set RTC_LPD_OPT */
 116         rtc_read(RTC_AL_SEC, &sec);
 117         sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
 118         rtc_write(RTC_AL_SEC, sec);
 119         if (!rtc_write_trigger())
 120                 return 0;
 121
 122         /* init XOSC32 to detect 32k clock stop */
 123         rtc_read(RTC_CON, &con);
 124         con |= RTC_CON_XOSC32_LPEN;
 125         if (!rtc_lpen(con))
 126                 return 0;
 127
 128         /* init EOSC32 to detect rtc low power */
 129         rtc_read(RTC_CON, &con);
 130         con |= RTC_CON_EOSC32_LPEN;
 131         if (!rtc_lpen(con))
 132                 return 0;
 133
 134         rtc_read(RTC_CON, &con);
 135         con &= ~RTC_CON_XOSC32_LPEN;
 136         rtc_write(RTC_CON, con);
 137
 138         /* set RTC_LPD_OPT */
 139         rtc_read(RTC_AL_SEC, &sec);
 140         sec &= ~RTC_LPD_OPT_MASK;
 141         sec |= RTC_LPD_OPT_EOSC_LPD;
 142         rtc_write(RTC_AL_SEC, sec);
 143         if (!rtc_write_trigger())
 144                 return 0;
 145
 146         return 1;
 147 }
 148
 149 static bool rtc_hw_init(void)
 150 {
 151         u16 bbpu;
 152
 153         rtc_read(RTC_BBPU, &bbpu);
 154         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_INIT);
 155         rtc_write_trigger();
 156
 157         udelay(500);
 158
 159         rtc_read(RTC_BBPU, &bbpu);
 160         rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
 161         rtc_write_trigger();
 162
 163         rtc_read(RTC_BBPU, &bbpu);
 164         if (bbpu & RTC_BBPU_INIT) {
 165                 rtc_info("timeout\n");
 166                 return false;
 167         }
 168
 169         return true;
 170 }
 171
 172 /* write powerkeys to enable rtc functions */
 173 static int rtc_powerkey_init(void)
 174 {
 175         rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
 176         rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
 177         return rtc_write_trigger();
 178 }
 179
 180 /* rtc init check */
 181 int rtc_init(u8 recover)
 182 {
 183         int ret;
 184
 185         rtc_info("recovery: %d\n", recover);
 186
 187         /* write powerkeys to enable rtc functions */
 188         if (!rtc_powerkey_init()) {
 189                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 190                 goto err;
 191         }
 192
 193         /* write interface unlock need to be set after powerkey match */
 194         if (!rtc_writeif_unlock()) {
 195                 ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
 196                 goto err;
 197         }
 198
 199         if (recover)
 200                 mdelay(20);
 201
 202         if (!rtc_gpio_init()) {
 203                 ret = -RTC_STATUS_GPIO_INIT_FAIL;
 204                 goto err;
 205         }
 206
 207         if (!rtc_hw_init()) {
 208                 ret = -RTC_STATUS_HW_INIT_FAIL;
 209                 goto err;
 210         }
 211
 212         if (!rtc_reg_init()) {
 213                 ret = -RTC_STATUS_REG_INIT_FAIL;
 214                 goto err;
 215         }
 216
 217         if (!rtc_lpd_init()) {
 218                 ret = -RTC_STATUS_LPD_INIT_FAIL;
 219                 goto err;
 220         }
 221
 222         /* After lpd init, powerkeys need to be written again to enable
 223          * low power detect function.
 224          */
 225         if (!rtc_powerkey_init()) {
 226                 ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
 227                 goto err;
 228         }
 229
 230         return RTC_STATUS_OK;
 231 err:
 232         rtc_info("init fail: ret=%d\n", ret);
 233         return ret;
 234 }
 235
 236 /* enable rtc bbpu */
 237 void rtc_bbpu_power_on(void)
 238 {
 239         u16 bbpu;
 240         int ret;
 241
 242         /* pull powerhold high, control by pmic */
 243         pmic_set_power_hold(true);
 244
 245         /* pull PWRBB high */
 246         bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
 247         rtc_write(RTC_BBPU, bbpu);
 248         ret = rtc_write_trigger();
 249         rtc_info("rtc_write_trigger=%d\n", ret);
 250
 251         rtc_read(RTC_BBPU, &bbpu);
 252         rtc_info("done BBPU=%#x\n", bbpu);
 253 }
 254
 255 void poweroff(void)
 256 {
 257         u16 bbpu;
 258
 259         if (!rtc_writeif_unlock())
 260                 rtc_info("rtc_writeif_unlock() failed\n");
 261         /* pull PWRBB low */
 262         bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
 263         rtc_write(RTC_BBPU, bbpu);
 264
 265         pmic_set_power_hold(false);
 266         halt();
 267 }
 268
 269 static void dcxo_init(void)
 270 {
 271         /* Buffer setting */
 272         rtc_write(PMIC_RG_DCXO_CW15, 0xA2AA);
 273         rtc_write(PMIC_RG_DCXO_CW13, 0x98E9);
 274         rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
 275
 276         /* 26M enable control */
 277         /* Enable clock buffer XO_SOC */
 278         rtc_write(PMIC_RG_DCXO_CW00, 0x4005);
 279         rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
 280         rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
 281
 282         /* Load thermal coefficient */
 283         rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
 284         rtc_write(PMIC_RG_DCXO_CW21, 0x12A7);
 285         rtc_write(PMIC_RG_DCXO_ELR0, 0xD004);
 286         rtc_write(PMIC_RG_TOP_TMA_KEY, 0x0000);
 287
 288         /* Adjust OSC FPM setting */
 289         rtc_write(PMIC_RG_DCXO_CW07, 0x8FFE);
 290
 291         /* Re-Calibrate OSC current */
 292         rtc_write(PMIC_RG_DCXO_CW09, 0x008F);
 293         udelay(100);
 294         rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
 295         mdelay(5);
 296 }
 297
 298 /* the rtc boot flow entry */
 299 void rtc_boot(void)
 300 {
 301         /* dcxo clock init settings */
 302         dcxo_init();
 303
 304         /* dcxo 32k init settings */
 305         pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
 306         pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
 307
 308         /* use dcxo 32K clock */
 309         if (!rtc_enable_dcxo())
 310                 rtc_info("rtc_enable_dcxo() failed\n");
 311
 312         rtc_boot_common();
 313         rtc_bbpu_power_on();
 314 }