src/mainboard/hp/8470p/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/io.h>
  17 #include <northbridge/intel/sandybridge/sandybridge.h>
  18 #include <northbridge/intel/sandybridge/raminit_native.h>
  19 #include <southbridge/intel/bd82x6x/pch.h>
  20 #include <superio/smsc/lpc47n217/lpc47n217.h>
  21 #include <ec/hp/kbc1126/ec.h>
  22
  23 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
  24
  25 void pch_enable_lpc(void)
  26 {
  27         /*
  28          * CNF2 and CNF1 for Super I/O
  29          * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
  30          * Enable parallel port and serial port
  31          */
  32         pci_write_config16(PCH_LPC_DEV, LPC_EN,
  33                         CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
  34                         LPT_LPC_EN | COMA_LPC_EN);
  35         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
  36         /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
  37         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
  38 }
  39
  40 void mainboard_rcba_config(void)
  41 {
  42 }
  43
  44 const struct southbridge_usb_port mainboard_usb_ports[] = {
  45         { 1, 1, 0 },
  46         { 1, 1, 0 },
  47         { 1, 1, 1 },
  48         { 1, 1, 1 },
  49         { 1, 0, 2 },
  50         { 0, 0, 2 },
  51         { 0, 0, 3 },
  52         { 1, 0, 3 },
  53         { 1, 1, 4 },
  54         { 1, 1, 4 },
  55         { 1, 0, 5 },
  56         { 1, 0, 5 },
  57         { 1, 0, 6 },
  58         { 1, 0, 6 },
  59 };
  60
  61 void mainboard_early_init(int s3resume)
  62 {
  63 }
  64
  65 void mainboard_config_superio(void)
  66 {
  67         lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  68         kbc1126_enter_conf();
  69         kbc1126_mailbox_init();
  70         kbc1126_kbc_init();
  71         kbc1126_ec_init();
  72         kbc1126_pm1_init();
  73         kbc1126_exit_conf();
  74 }
  75
  76 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
  77 {
  78         read_spd(&spd[0], 0x50, id_only);
  79         read_spd(&spd[2], 0x52, id_only);
  80 }