| blob | c172eb9f2f22cec2fb5f194273bbcbfcf342f13d |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /* DefinitionBlock Statement */
17 DefinitionBlock (
18 "DSDT.AML", /* Output filename */
19 "DSDT", /* Signature */
20 0x02, /* DSDT Revision, needs to be 2 for 64bit */
21 "GIGA ", /* OEMID */
22 "COREBOOT", /* TABLE ID */
23 0x00010001 /* OEM Revision */
24 )
25 { /* Start of ASL file */
26 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
28 /* Data to be patched by the BIOS during POST */
29 /* FIXME the patching is not done yet! */
30 /* Memory related values */
31 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
32 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
33 Name(PBLN, 0x0) /* Length of BIOS area */
35 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
36 Name(HPBA, 0xFED00000) /* Base address of HPET table */
38 /* USB overcurrent mapping pins. */
39 Name(UOM0, 0)
40 Name(UOM1, 2)
41 Name(UOM2, 0)
42 Name(UOM3, 7)
43 Name(UOM4, 2)
44 Name(UOM5, 2)
45 Name(UOM6, 6)
46 Name(UOM7, 2)
47 Name(UOM8, 6)
48 Name(UOM9, 6)
50 /* Some global data */
51 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
52 Name(OSV, Ones) /* Assume nothing */
53 Name(PMOD, One) /* Assume APIC */
55 /*
56 * Processor Object
57 *
58 */
59 Scope (\_PR) { /* define processor scope */
60 Processor(
61 CPU0, /* name space name */
62 0, /* Unique number for this processor */
63 0x808, /* PBLK system I/O address !hardcoded! */
64 0x06 /* PBLKLEN for boot processor */
65 ) {
66 #include "acpi/cpstate.asl"
67 }
69 Processor(
70 CPU1, /* name space name */
71 1, /* Unique number for this processor */
72 0x0000, /* PBLK system I/O address !hardcoded! */
73 0x00 /* PBLKLEN for boot processor */
74 ) {
75 #include "acpi/cpstate.asl"
76 }
78 Processor(
79 CPU2, /* name space name */
80 2, /* Unique number for this processor */
81 0x0000, /* PBLK system I/O address !hardcoded! */
82 0x00 /* PBLKLEN for boot processor */
83 ) {
84 #include "acpi/cpstate.asl"
85 }
87 Processor(
88 CPU3, /* name space name */
89 3, /* Unique number for this processor */
90 0x0000, /* PBLK system I/O address !hardcoded! */
91 0x00 /* PBLKLEN for boot processor */
92 ) {
93 #include "acpi/cpstate.asl"
94 }
95 } /* End _PR scope */
97 /* PIC IRQ mapping registers, C00h-C01h */
98 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
99 Field(PRQM, ByteAcc, NoLock, Preserve) {
100 PRQI, 0x00000008,
101 PRQD, 0x00000008, /* Offset: 1h */
102 }
103 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
104 PINA, 0x00000008, /* Index 0 */
105 PINB, 0x00000008, /* Index 1 */
106 PINC, 0x00000008, /* Index 2 */
107 PIND, 0x00000008, /* Index 3 */
108 AINT, 0x00000008, /* Index 4 */
109 SINT, 0x00000008, /* Index 5 */
110 , 0x00000008, /* Index 6 */
111 AAUD, 0x00000008, /* Index 7 */
112 AMOD, 0x00000008, /* Index 8 */
113 PINE, 0x00000008, /* Index 9 */
114 PINF, 0x00000008, /* Index A */
115 PING, 0x00000008, /* Index B */
116 PINH, 0x00000008, /* Index C */
117 }
119 /* PCI Error control register */
120 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
121 Field(PERC, ByteAcc, NoLock, Preserve) {
122 SENS, 0x00000001,
123 PENS, 0x00000001,
124 SENE, 0x00000001,
125 PENE, 0x00000001,
126 }
128 /* Client Management index/data registers */
129 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
130 Field(CMT, ByteAcc, NoLock, Preserve) {
131 CMTI, 8,
132 /* Client Management Data register */
133 G64E, 1,
134 G64O, 1,
135 G32O, 2,
136 , 2,
137 GPSL, 2,
138 }
140 /* GPM Port register */
141 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
142 Field(GPT, ByteAcc, NoLock, Preserve) {
143 GPB0,1,
144 GPB1,1,
145 GPB2,1,
146 GPB3,1,
147 GPB4,1,
148 GPB5,1,
149 GPB6,1,
150 GPB7,1,
151 }
153 /* Flash ROM program enable register */
154 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
155 Field(FRE, ByteAcc, NoLock, Preserve) {
156 , 0x00000006,
157 FLRE, 0x00000001,
158 }
160 /* PM2 index/data registers */
161 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
162 Field(PM2R, ByteAcc, NoLock, Preserve) {
163 PM2I, 0x00000008,
164 PM2D, 0x00000008,
165 }
167 /* Power Management I/O registers */
168 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
169 Field(PIOR, ByteAcc, NoLock, Preserve) {
170 PIOI, 0x00000008,
171 PIOD, 0x00000008,
172 }
173 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
174 Offset(0x00), /* MiscControl */
175 , 1,
176 T1EE, 1,
177 T2EE, 1,
178 Offset(0x01), /* MiscStatus */
179 , 1,
180 T1E, 1,
181 T2E, 1,
182 Offset(0x04), /* SmiWakeUpEventEnable3 */
183 , 7,
184 SSEN, 1,
185 Offset(0x07), /* SmiWakeUpEventStatus3 */
186 , 7,
187 CSSM, 1,
188 Offset(0x10), /* AcpiEnable */
189 , 6,
190 PWDE, 1,
191 Offset(0x1C), /* ProgramIoEnable */
192 , 3,
193 MKME, 1,
194 IO3E, 1,
195 IO2E, 1,
196 IO1E, 1,
197 IO0E, 1,
198 Offset(0x1D), /* IOMonitorStatus */
199 , 3,
200 MKMS, 1,
201 IO3S, 1,
202 IO2S, 1,
203 IO1S, 1,
204 IO0S,1,
205 Offset(0x20), /* AcpiPmEvtBlk */
206 APEB, 16,
207 Offset(0x36), /* GEvtLevelConfig */
208 , 6,
209 ELC6, 1,
210 ELC7, 1,
211 Offset(0x37), /* GPMLevelConfig0 */
212 , 3,
213 PLC0, 1,
214 PLC1, 1,
215 PLC2, 1,
216 PLC3, 1,
217 PLC8, 1,
218 Offset(0x38), /* GPMLevelConfig1 */
219 , 1,
220 PLC4, 1,
221 PLC5, 1,
222 , 1,
223 PLC6, 1,
224 PLC7, 1,
225 Offset(0x3B), /* PMEStatus1 */
226 GP0S, 1,
227 GM4S, 1,
228 GM5S, 1,
229 APS, 1,
230 GM6S, 1,
231 GM7S, 1,
232 GP2S, 1,
233 STSS, 1,
234 Offset(0x55), /* SoftPciRst */
235 SPRE, 1,
236 , 1,
237 , 1,
238 PNAT, 1,
239 PWMK, 1,
240 PWNS, 1,
242 /* Offset(0x61), */ /* Options_1 */
243 /* ,7, */
244 /* R617,1, */
246 Offset(0x65), /* UsbPMControl */
247 , 4,
248 URRE, 1,
249 Offset(0x68), /* MiscEnable68 */
250 , 3,
251 TMTE, 1,
252 , 1,
253 Offset(0x92), /* GEVENTIN */
254 , 7,
255 E7IS, 1,
256 Offset(0x96), /* GPM98IN */
257 G8IS, 1,
258 G9IS, 1,
259 Offset(0x9A), /* EnhanceControl */
260 ,7,
261 HPDE, 1,
262 Offset(0xA8), /* PIO7654Enable */
263 IO4E, 1,
264 IO5E, 1,
265 IO6E, 1,
266 IO7E, 1,
267 Offset(0xA9), /* PIO7654Status */
268 IO4S, 1,
269 IO5S, 1,
270 IO6S, 1,
271 IO7S, 1,
272 }
274 /* PM1 Event Block
275 * First word is PM1_Status, Second word is PM1_Enable
276 */
277 OperationRegion(P1EB, SystemIO, APEB, 0x04)
278 Field(P1EB, ByteAcc, NoLock, Preserve) {
279 TMST, 1,
280 , 3,
281 BMST, 1,
282 GBST, 1,
283 Offset(0x01),
284 PBST, 1,
285 , 1,
286 RTST, 1,
287 , 3,
288 PWST, 1,
289 SPWS, 1,
290 Offset(0x02),
291 TMEN, 1,
292 , 4,
293 GBEN, 1,
294 Offset(0x03),
295 PBEN, 1,
296 , 1,
297 RTEN, 1,
298 , 3,
299 PWDA, 1,
300 }
302 Scope(\_SB) {
303 /* PCIe Configuration Space for 16 busses */
304 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
305 Field(PCFG, ByteAcc, NoLock, Preserve) {
306 /* Byte offsets are computed using the following technique:
307 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
308 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
309 */
310 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
311 STB5, 32,
312 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
313 PT0D, 1,
314 PT1D, 1,
315 PT2D, 1,
316 PT3D, 1,
317 PT4D, 1,
318 PT5D, 1,
319 PT6D, 1,
320 PT7D, 1,
321 PT8D, 1,
322 PT9D, 1,
323 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
324 SBIE, 1,
325 SBME, 1,
326 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
327 SBRI, 8,
328 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
329 SBB1, 32,
330 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
331 ,14,
332 P92E, 1, /* Port92 decode enable */
333 }
335 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
336 Field(SB5, AnyAcc, NoLock, Preserve){
337 /* Port 0 */
338 Offset(0x120), /* Port 0 Task file status */
339 P0ER, 1,
340 , 2,
341 P0DQ, 1,
342 , 3,
343 P0BY, 1,
344 Offset(0x128), /* Port 0 Serial ATA status */
345 P0DD, 4,
346 , 4,
347 P0IS, 4,
348 Offset(0x12C), /* Port 0 Serial ATA control */
349 P0DI, 4,
350 Offset(0x130), /* Port 0 Serial ATA error */
351 , 16,
352 P0PR, 1,
354 /* Port 1 */
355 offset(0x1A0), /* Port 1 Task file status */
356 P1ER, 1,
357 , 2,
358 P1DQ, 1,
359 , 3,
360 P1BY, 1,
361 Offset(0x1A8), /* Port 1 Serial ATA status */
362 P1DD, 4,
363 , 4,
364 P1IS, 4,
365 Offset(0x1AC), /* Port 1 Serial ATA control */
366 P1DI, 4,
367 Offset(0x1B0), /* Port 1 Serial ATA error */
368 , 16,
369 P1PR, 1,
371 /* Port 2 */
372 Offset(0x220), /* Port 2 Task file status */
373 P2ER, 1,
374 , 2,
375 P2DQ, 1,
376 , 3,
377 P2BY, 1,
378 Offset(0x228), /* Port 2 Serial ATA status */
379 P2DD, 4,
380 , 4,
381 P2IS, 4,
382 Offset(0x22C), /* Port 2 Serial ATA control */
383 P2DI, 4,
384 Offset(0x230), /* Port 2 Serial ATA error */
385 , 16,
386 P2PR, 1,
388 /* Port 3 */
389 Offset(0x2A0), /* Port 3 Task file status */
390 P3ER, 1,
391 , 2,
392 P3DQ, 1,
393 , 3,
394 P3BY, 1,
395 Offset(0x2A8), /* Port 3 Serial ATA status */
396 P3DD, 4,
397 , 4,
398 P3IS, 4,
399 Offset(0x2AC), /* Port 3 Serial ATA control */
400 P3DI, 4,
401 Offset(0x2B0), /* Port 3 Serial ATA error */
402 , 16,
403 P3PR, 1,
404 }
405 }
408 #include "acpi/routing.asl"
410 Scope(\_SB) {
412 Method(OSFL, 0){
414 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
416 if(CondRefOf(\_OSI))
417 {
418 Store(1, OSVR) /* Assume some form of XP */
419 if (\_OSI("Windows 2006")) /* Vista */
420 {
421 Store(2, OSVR)
422 }
423 } else {
424 If(WCMP(\_OS,"Linux")) {
425 Store(3, OSVR) /* Linux */
426 } Else {
427 Store(4, OSVR) /* Gotta be WinCE */
428 }
429 }
430 Return(OSVR)
431 }
433 Method(_PIC, 0x01, NotSerialized)
434 {
435 If (Arg0)
436 {
437 \_SB.CIRQ()
438 }
439 Store(Arg0, PMOD)
440 }
441 Method(CIRQ, 0x00, NotSerialized){
442 Store(0, PINA)
443 Store(0, PINB)
444 Store(0, PINC)
445 Store(0, PIND)
446 Store(0, PINE)
447 Store(0, PINF)
448 Store(0, PING)
449 Store(0, PINH)
450 }
452 Name(IRQB, ResourceTemplate(){
453 IRQ(Level,ActiveLow,Shared){15}
454 })
456 Name(IRQP, ResourceTemplate(){
457 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
458 })
460 Name(PITF, ResourceTemplate(){
461 IRQ(Level,ActiveLow,Exclusive){9}
462 })
464 Device(INTA) {
465 Name(_HID, EISAID("PNP0C0F"))
466 Name(_UID, 1)
468 Method(_STA, 0) {
469 if (PINA) {
470 Return(0x0B) /* sata is invisible */
471 } else {
472 Return(0x09) /* sata is disabled */
473 }
474 } /* End Method(_SB.INTA._STA) */
476 Method(_DIS ,0) {
477 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
478 Store(0, PINA)
479 } /* End Method(_SB.INTA._DIS) */
481 Method(_PRS ,0) {
482 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
483 Return(IRQP)
484 } /* Method(_SB.INTA._PRS) */
486 Method(_CRS ,0) {
487 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
488 CreateWordField(IRQB, 0x1, IRQN)
489 ShiftLeft(1, PINA, IRQN)
490 Return(IRQB)
491 } /* Method(_SB.INTA._CRS) */
493 Method(_SRS, 1) {
494 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
495 CreateWordField(ARG0, 1, IRQM)
497 /* Use lowest available IRQ */
498 FindSetRightBit(IRQM, Local0)
499 if (Local0) {
500 Decrement(Local0)
501 }
502 Store(Local0, PINA)
503 } /* End Method(_SB.INTA._SRS) */
504 } /* End Device(INTA) */
506 Device(INTB) {
507 Name(_HID, EISAID("PNP0C0F"))
508 Name(_UID, 2)
510 Method(_STA, 0) {
511 if (PINB) {
512 Return(0x0B) /* sata is invisible */
513 } else {
514 Return(0x09) /* sata is disabled */
515 }
516 } /* End Method(_SB.INTB._STA) */
518 Method(_DIS ,0) {
519 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
520 Store(0, PINB)
521 } /* End Method(_SB.INTB._DIS) */
523 Method(_PRS ,0) {
524 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
525 Return(IRQP)
526 } /* Method(_SB.INTB._PRS) */
528 Method(_CRS ,0) {
529 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
530 CreateWordField(IRQB, 0x1, IRQN)
531 ShiftLeft(1, PINB, IRQN)
532 Return(IRQB)
533 } /* Method(_SB.INTB._CRS) */
535 Method(_SRS, 1) {
536 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
537 CreateWordField(ARG0, 1, IRQM)
539 /* Use lowest available IRQ */
540 FindSetRightBit(IRQM, Local0)
541 if (Local0) {
542 Decrement(Local0)
543 }
544 Store(Local0, PINB)
545 } /* End Method(_SB.INTB._SRS) */
546 } /* End Device(INTB) */
548 Device(INTC) {
549 Name(_HID, EISAID("PNP0C0F"))
550 Name(_UID, 3)
552 Method(_STA, 0) {
553 if (PINC) {
554 Return(0x0B) /* sata is invisible */
555 } else {
556 Return(0x09) /* sata is disabled */
557 }
558 } /* End Method(_SB.INTC._STA) */
560 Method(_DIS ,0) {
561 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
562 Store(0, PINC)
563 } /* End Method(_SB.INTC._DIS) */
565 Method(_PRS ,0) {
566 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
567 Return(IRQP)
568 } /* Method(_SB.INTC._PRS) */
570 Method(_CRS ,0) {
571 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
572 CreateWordField(IRQB, 0x1, IRQN)
573 ShiftLeft(1, PINC, IRQN)
574 Return(IRQB)
575 } /* Method(_SB.INTC._CRS) */
577 Method(_SRS, 1) {
578 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
579 CreateWordField(ARG0, 1, IRQM)
581 /* Use lowest available IRQ */
582 FindSetRightBit(IRQM, Local0)
583 if (Local0) {
584 Decrement(Local0)
585 }
586 Store(Local0, PINC)
587 } /* End Method(_SB.INTC._SRS) */
588 } /* End Device(INTC) */
590 Device(INTD) {
591 Name(_HID, EISAID("PNP0C0F"))
592 Name(_UID, 4)
594 Method(_STA, 0) {
595 if (PIND) {
596 Return(0x0B) /* sata is invisible */
597 } else {
598 Return(0x09) /* sata is disabled */
599 }
600 } /* End Method(_SB.INTD._STA) */
602 Method(_DIS ,0) {
603 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
604 Store(0, PIND)
605 } /* End Method(_SB.INTD._DIS) */
607 Method(_PRS ,0) {
608 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
609 Return(IRQP)
610 } /* Method(_SB.INTD._PRS) */
612 Method(_CRS ,0) {
613 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
614 CreateWordField(IRQB, 0x1, IRQN)
615 ShiftLeft(1, PIND, IRQN)
616 Return(IRQB)
617 } /* Method(_SB.INTD._CRS) */
619 Method(_SRS, 1) {
620 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
621 CreateWordField(ARG0, 1, IRQM)
623 /* Use lowest available IRQ */
624 FindSetRightBit(IRQM, Local0)
625 if (Local0) {
626 Decrement(Local0)
627 }
628 Store(Local0, PIND)
629 } /* End Method(_SB.INTD._SRS) */
630 } /* End Device(INTD) */
632 Device(INTE) {
633 Name(_HID, EISAID("PNP0C0F"))
634 Name(_UID, 5)
636 Method(_STA, 0) {
637 if (PINE) {
638 Return(0x0B) /* sata is invisible */
639 } else {
640 Return(0x09) /* sata is disabled */
641 }
642 } /* End Method(_SB.INTE._STA) */
644 Method(_DIS ,0) {
645 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
646 Store(0, PINE)
647 } /* End Method(_SB.INTE._DIS) */
649 Method(_PRS ,0) {
650 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
651 Return(IRQP)
652 } /* Method(_SB.INTE._PRS) */
654 Method(_CRS ,0) {
655 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
656 CreateWordField(IRQB, 0x1, IRQN)
657 ShiftLeft(1, PINE, IRQN)
658 Return(IRQB)
659 } /* Method(_SB.INTE._CRS) */
661 Method(_SRS, 1) {
662 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
663 CreateWordField(ARG0, 1, IRQM)
665 /* Use lowest available IRQ */
666 FindSetRightBit(IRQM, Local0)
667 if (Local0) {
668 Decrement(Local0)
669 }
670 Store(Local0, PINE)
671 } /* End Method(_SB.INTE._SRS) */
672 } /* End Device(INTE) */
674 Device(INTF) {
675 Name(_HID, EISAID("PNP0C0F"))
676 Name(_UID, 6)
678 Method(_STA, 0) {
679 if (PINF) {
680 Return(0x0B) /* sata is invisible */
681 } else {
682 Return(0x09) /* sata is disabled */
683 }
684 } /* End Method(_SB.INTF._STA) */
686 Method(_DIS ,0) {
687 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
688 Store(0, PINF)
689 } /* End Method(_SB.INTF._DIS) */
691 Method(_PRS ,0) {
692 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
693 Return(PITF)
694 } /* Method(_SB.INTF._PRS) */
696 Method(_CRS ,0) {
697 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
698 CreateWordField(IRQB, 0x1, IRQN)
699 ShiftLeft(1, PINF, IRQN)
700 Return(IRQB)
701 } /* Method(_SB.INTF._CRS) */
703 Method(_SRS, 1) {
704 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
705 CreateWordField(ARG0, 1, IRQM)
707 /* Use lowest available IRQ */
708 FindSetRightBit(IRQM, Local0)
709 if (Local0) {
710 Decrement(Local0)
711 }
712 Store(Local0, PINF)
713 } /* End Method(_SB.INTF._SRS) */
714 } /* End Device(INTF) */
716 Device(INTG) {
717 Name(_HID, EISAID("PNP0C0F"))
718 Name(_UID, 7)
720 Method(_STA, 0) {
721 if (PING) {
722 Return(0x0B) /* sata is invisible */
723 } else {
724 Return(0x09) /* sata is disabled */
725 }
726 } /* End Method(_SB.INTG._STA) */
728 Method(_DIS ,0) {
729 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
730 Store(0, PING)
731 } /* End Method(_SB.INTG._DIS) */
733 Method(_PRS ,0) {
734 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
735 Return(IRQP)
736 } /* Method(_SB.INTG._CRS) */
738 Method(_CRS ,0) {
739 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
740 CreateWordField(IRQB, 0x1, IRQN)
741 ShiftLeft(1, PING, IRQN)
742 Return(IRQB)
743 } /* Method(_SB.INTG._CRS) */
745 Method(_SRS, 1) {
746 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
747 CreateWordField(ARG0, 1, IRQM)
749 /* Use lowest available IRQ */
750 FindSetRightBit(IRQM, Local0)
751 if (Local0) {
752 Decrement(Local0)
753 }
754 Store(Local0, PING)
755 } /* End Method(_SB.INTG._SRS) */
756 } /* End Device(INTG) */
758 Device(INTH) {
759 Name(_HID, EISAID("PNP0C0F"))
760 Name(_UID, 8)
762 Method(_STA, 0) {
763 if (PINH) {
764 Return(0x0B) /* sata is invisible */
765 } else {
766 Return(0x09) /* sata is disabled */
767 }
768 } /* End Method(_SB.INTH._STA) */
770 Method(_DIS ,0) {
771 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
772 Store(0, PINH)
773 } /* End Method(_SB.INTH._DIS) */
775 Method(_PRS ,0) {
776 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
777 Return(IRQP)
778 } /* Method(_SB.INTH._CRS) */
780 Method(_CRS ,0) {
781 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
782 CreateWordField(IRQB, 0x1, IRQN)
783 ShiftLeft(1, PINH, IRQN)
784 Return(IRQB)
785 } /* Method(_SB.INTH._CRS) */
787 Method(_SRS, 1) {
788 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
789 CreateWordField(ARG0, 1, IRQM)
791 /* Use lowest available IRQ */
792 FindSetRightBit(IRQM, Local0)
793 if (Local0) {
794 Decrement(Local0)
795 }
796 Store(Local0, PINH)
797 } /* End Method(_SB.INTH._SRS) */
798 } /* End Device(INTH) */
800 } /* End Scope(_SB) */
802 #include <southbridge/amd/common/acpi/sleepstates.asl>
804 /* Wake status package */
805 Name(WKST,Package(){Zero, Zero})
807 /*
808 * \_PTS - Prepare to Sleep method
809 *
810 * Entry:
811 * Arg0=The value of the sleeping state S1=1, S2=2, etc
812 *
813 * Exit:
814 * -none-
815 *
816 * The _PTS control method is executed at the beginning of the sleep process
817 * for S1-S5. The sleeping value is passed to the _PTS control method. This
818 * control method may be executed a relatively long time before entering the
819 * sleep state and the OS may abort the operation without notification to
820 * the ACPI driver. This method cannot modify the configuration or power
821 * state of any device in the system.
822 */
823 Method(\_PTS, 1) {
824 /* DBGO("\\_PTS\n") */
825 /* DBGO("From S0 to S") */
826 /* DBGO(Arg0) */
827 /* DBGO("\n") */
829 /* Don't allow PCIRST# to reset USB */
830 if (LEqual(Arg0,3)){
831 Store(0,URRE)
832 }
834 /* Clear sleep SMI status flag and enable sleep SMI trap. */
835 /*Store(One, CSSM)
836 Store(One, SSEN)*/
838 /* On older chips, clear PciExpWakeDisEn */
839 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
840 * Store(0,\_SB.PWDE)
841 *}
842 */
844 /* Clear wake status structure. */
845 Store(0, Index(WKST,0))
846 Store(0, Index(WKST,1))
847 \_SB.PCI0.SIOS (Arg0)
848 } /* End Method(\_PTS) */
850 /*
851 * The following method results in a "not a valid reserved NameSeg"
852 * warning so I have commented it out for the duration. It isn't
853 * used, so it could be removed.
854 *
855 *
856 * \_GTS OEM Going To Sleep method
857 *
858 * Entry:
859 * Arg0=The value of the sleeping state S1=1, S2=2
860 *
861 * Exit:
862 * -none-
863 *
864 * Method(\_GTS, 1) {
865 * DBGO("\\_GTS\n")
866 * DBGO("From S0 to S")
867 * DBGO(Arg0)
868 * DBGO("\n")
869 * }
870 */
872 /*
873 * \_BFS OEM Back From Sleep method
874 *
875 * Entry:
876 * Arg0=The value of the sleeping state S1=1, S2=2
877 *
878 * Exit:
879 * -none-
880 */
881 Method(\_BFS, 1) {
882 /* DBGO("\\_BFS\n") */
883 /* DBGO("From S") */
884 /* DBGO(Arg0) */
885 /* DBGO(" to S0\n") */
886 }
888 /*
889 * \_WAK System Wake method
890 *
891 * Entry:
892 * Arg0=The value of the sleeping state S1=1, S2=2
893 *
894 * Exit:
895 * Return package of 2 DWords
896 * Dword 1 - Status
897 * 0x00000000 wake succeeded
898 * 0x00000001 Wake was signaled but failed due to lack of power
899 * 0x00000002 Wake was signaled but failed due to thermal condition
900 * Dword 2 - Power Supply state
901 * if non-zero the effective S-state the power supply entered
902 */
903 Method(\_WAK, 1) {
904 /* DBGO("\\_WAK\n") */
905 /* DBGO("From S") */
906 /* DBGO(Arg0) */
907 /* DBGO(" to S0\n") */
909 /* Re-enable HPET */
910 Store(1,HPDE)
912 /* Restore PCIRST# so it resets USB */
913 if (LEqual(Arg0,3)){
914 Store(1,URRE)
915 }
917 /* Arbitrarily clear PciExpWakeStatus */
918 Store(PWST, Local1)
919 Store(Local1, PWST)
921 /* if (DeRefOf(Index(WKST,0))) {
922 * Store(0, Index(WKST,1))
923 * } else {
924 * Store(Arg0, Index(WKST,1))
925 * }
926 */
927 \_SB.PCI0.SIOW ()
928 Return(WKST)
929 } /* End Method(\_WAK) */
931 Scope(\_GPE) { /* Start Scope GPE */
932 /* General event 0 */
933 /* Method(_L00) {
934 * DBGO("\\_GPE\\_L00\n")
935 * }
936 */
938 /* General event 1 */
939 /* Method(_L01) {
940 * DBGO("\\_GPE\\_L00\n")
941 * }
942 */
944 /* General event 2 */
945 /* Method(_L02) {
946 * DBGO("\\_GPE\\_L00\n")
947 * }
948 */
950 /* General event 3 */
951 Method(_L03) {
952 /* DBGO("\\_GPE\\_L00\n") */
953 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
954 }
956 /* General event 4 */
957 /* Method(_L04) {
958 * DBGO("\\_GPE\\_L00\n")
959 * }
960 */
962 /* General event 5 */
963 /* Method(_L05) {
964 * DBGO("\\_GPE\\_L00\n")
965 * }
966 */
968 /* General event 6 - Used for GPM6, moved to USB.asl */
969 /* Method(_L06) {
970 * DBGO("\\_GPE\\_L00\n")
971 * }
972 */
974 /* General event 7 - Used for GPM7, moved to USB.asl */
975 /* Method(_L07) {
976 * DBGO("\\_GPE\\_L07\n")
977 * }
978 */
980 /* Legacy PM event */
981 Method(_L08) {
982 /* DBGO("\\_GPE\\_L08\n") */
983 }
985 /* Temp warning (TWarn) event */
986 Method(_L09) {
987 /* DBGO("\\_GPE\\_L09\n") */
988 Notify (\_TZ.TZ00, 0x80)
989 }
991 /* Reserved */
992 /* Method(_L0A) {
993 * DBGO("\\_GPE\\_L0A\n")
994 * }
995 */
997 /* USB controller PME# */
998 Method(_L0B) {
999 /* DBGO("\\_GPE\\_L0B\n") */
1000 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1001 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1002 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1003 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1004 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1005 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1006 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1007 }
1009 /* AC97 controller PME# */
1010 /* Method(_L0C) {
1011 * DBGO("\\_GPE\\_L0C\n")
1012 * }
1013 */
1015 /* OtherTherm PME# */
1016 /* Method(_L0D) {
1017 * DBGO("\\_GPE\\_L0D\n")
1018 * }
1019 */
1021 /* GPM9 SCI event - Moved to USB.asl */
1022 /* Method(_L0E) {
1023 * DBGO("\\_GPE\\_L0E\n")
1024 * }
1025 */
1027 /* PCIe HotPlug event */
1028 /* Method(_L0F) {
1029 * DBGO("\\_GPE\\_L0F\n")
1030 * }
1031 */
1033 /* ExtEvent0 SCI event */
1034 Method(_L10) {
1035 /* DBGO("\\_GPE\\_L10\n") */
1036 }
1039 /* ExtEvent1 SCI event */
1040 Method(_L11) {
1041 /* DBGO("\\_GPE\\_L11\n") */
1042 }
1044 /* PCIe PME# event */
1045 /* Method(_L12) {
1046 * DBGO("\\_GPE\\_L12\n")
1047 * }
1048 */
1050 /* GPM0 SCI event - Moved to USB.asl */
1051 /* Method(_L13) {
1052 * DBGO("\\_GPE\\_L13\n")
1053 * }
1054 */
1056 /* GPM1 SCI event - Moved to USB.asl */
1057 /* Method(_L14) {
1058 * DBGO("\\_GPE\\_L14\n")
1059 * }
1060 */
1062 /* GPM2 SCI event - Moved to USB.asl */
1063 /* Method(_L15) {
1064 * DBGO("\\_GPE\\_L15\n")
1065 * }
1066 */
1068 /* GPM3 SCI event - Moved to USB.asl */
1069 /* Method(_L16) {
1070 * DBGO("\\_GPE\\_L16\n")
1071 * }
1072 */
1074 /* GPM8 SCI event - Moved to USB.asl */
1075 /* Method(_L17) {
1076 * DBGO("\\_GPE\\_L17\n")
1077 * }
1078 */
1080 /* GPIO0 or GEvent8 event */
1081 Method(_L18) {
1082 /* DBGO("\\_GPE\\_L18\n") */
1083 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1084 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1085 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1086 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1087 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1088 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1089 }
1091 /* GPM4 SCI event - Moved to USB.asl */
1092 /* Method(_L19) {
1093 * DBGO("\\_GPE\\_L19\n")
1094 * }
1095 */
1097 /* GPM5 SCI event - Moved to USB.asl */
1098 /* Method(_L1A) {
1099 * DBGO("\\_GPE\\_L1A\n")
1100 * }
1101 */
1103 /* Azalia SCI event */
1104 Method(_L1B) {
1105 /* DBGO("\\_GPE\\_L1B\n") */
1106 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1107 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1108 }
1110 /* GPM6 SCI event - Reassigned to _L06 */
1111 /* Method(_L1C) {
1112 * DBGO("\\_GPE\\_L1C\n")
1113 * }
1114 */
1116 /* GPM7 SCI event - Reassigned to _L07 */
1117 /* Method(_L1D) {
1118 * DBGO("\\_GPE\\_L1D\n")
1119 * }
1120 */
1122 /* GPIO2 or GPIO66 SCI event */
1123 /* Method(_L1E) {
1124 * DBGO("\\_GPE\\_L1E\n")
1125 * }
1126 */
1128 /* SATA SCI event - Moved to sata.asl */
1129 /* Method(_L1F) {
1130 * DBGO("\\_GPE\\_L1F\n")
1131 * }
1132 */
1134 } /* End Scope GPE */
1136 #include "acpi/usb.asl"
1138 /* System Bus */
1139 Scope(\_SB) { /* Start \_SB scope */
1140 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1142 /* _SB.PCI0 */
1143 /* Note: Only need HID on Primary Bus */
1144 Device(PCI0) {
1145 External (TOM1)
1146 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1147 Name(_HID, EISAID("PNP0A03"))
1148 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1149 Method(_BBN, 0) { /* Bus number = 0 */
1150 Return(0)
1151 }
1152 Method(_STA, 0) {
1153 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1154 Return(0x0B) /* Status is visible */
1155 }
1157 Method(_PRT,0) {
1158 If(PMOD){ Return(APR0) } /* APIC mode */
1159 Return (PR0) /* PIC Mode */
1160 } /* end _PRT */
1162 /* Describe the Northbridge devices */
1163 Device(AMRT) {
1164 Name(_ADR, 0x00000000)
1165 } /* end AMRT */
1167 /* The internal GFX bridge */
1168 Device(AGPB) {
1169 Name(_ADR, 0x00010000)
1170 Name(_PRW, Package() {0x18, 4})
1171 Method(_PRT,0) {
1172 Return (APR1)
1173 }
1174 } /* end AGPB */
1176 /* The external GFX bridge */
1177 Device(PBR2) {
1178 Name(_ADR, 0x00020000)
1179 Name(_PRW, Package() {0x18, 4})
1180 Method(_PRT,0) {
1181 If(PMOD){ Return(APS2) } /* APIC mode */
1182 Return (PS2) /* PIC Mode */
1183 } /* end _PRT */
1184 } /* end PBR2 */
1186 /* Dev3 is also an external GFX bridge, not used in Herring */
1188 Device(PBR4) {
1189 Name(_ADR, 0x00040000)
1190 Name(_PRW, Package() {0x18, 4})
1191 Method(_PRT,0) {
1192 If(PMOD){ Return(APS4) } /* APIC mode */
1193 Return (PS4) /* PIC Mode */
1194 } /* end _PRT */
1195 } /* end PBR4 */
1197 Device(PBR5) {
1198 Name(_ADR, 0x00050000)
1199 Name(_PRW, Package() {0x18, 4})
1200 Method(_PRT,0) {
1201 If(PMOD){ Return(APS5) } /* APIC mode */
1202 Return (PS5) /* PIC Mode */
1203 } /* end _PRT */
1204 } /* end PBR5 */
1206 Device(PBR6) {
1207 Name(_ADR, 0x00060000)
1208 Name(_PRW, Package() {0x18, 4})
1209 Method(_PRT,0) {
1210 If(PMOD){ Return(APS6) } /* APIC mode */
1211 Return (PS6) /* PIC Mode */
1212 } /* end _PRT */
1213 } /* end PBR6 */
1215 /* The onboard EtherNet chip */
1216 Device(PBR7) {
1217 Name(_ADR, 0x00070000)
1218 Name(_PRW, Package() {0x18, 4})
1219 Method(_PRT,0) {
1220 If(PMOD){ Return(APS7) } /* APIC mode */
1221 Return (PS7) /* PIC Mode */
1222 } /* end _PRT */
1223 } /* end PBR7 */
1225 /* GPP */
1226 Device(PBR9) {
1227 Name(_ADR, 0x00090000)
1228 Name(_PRW, Package() {0x18, 4})
1229 Method(_PRT,0) {
1230 If(PMOD){ Return(APS9) } /* APIC mode */
1231 Return (PS9) /* PIC Mode */
1232 } /* end _PRT */
1233 } /* end PBR9 */
1235 Device(PBRa) {
1236 Name(_ADR, 0x000A0000)
1237 Name(_PRW, Package() {0x18, 4})
1238 Method(_PRT,0) {
1239 If(PMOD){ Return(APSa) } /* APIC mode */
1240 Return (PSa) /* PIC Mode */
1241 } /* end _PRT */
1242 } /* end PBRa */
1245 /* PCI slot 1, 2, 3 */
1246 Device(PIBR) {
1247 Name(_ADR, 0x00140004)
1248 Name(_PRW, Package() {0x18, 4})
1250 Method(_PRT, 0) {
1251 Return (PCIB)
1252 }
1253 }
1255 /* Describe the Southbridge devices */
1256 Device(STCR) {
1257 Name(_ADR, 0x00110000)
1258 #include "acpi/sata.asl"
1259 } /* end STCR */
1261 Device(UOH1) {
1262 Name(_ADR, 0x00130000)
1263 Name(_PRW, Package() {0x0B, 3})
1264 } /* end UOH1 */
1266 Device(UOH2) {
1267 Name(_ADR, 0x00130001)
1268 Name(_PRW, Package() {0x0B, 3})
1269 } /* end UOH2 */
1271 Device(UOH3) {
1272 Name(_ADR, 0x00130002)
1273 Name(_PRW, Package() {0x0B, 3})
1274 } /* end UOH3 */
1276 Device(UOH4) {
1277 Name(_ADR, 0x00130003)
1278 Name(_PRW, Package() {0x0B, 3})
1279 } /* end UOH4 */
1281 Device(UOH5) {
1282 Name(_ADR, 0x00130004)
1283 Name(_PRW, Package() {0x0B, 3})
1284 } /* end UOH5 */
1286 Device(UEH1) {
1287 Name(_ADR, 0x00130005)
1288 Name(_PRW, Package() {0x0B, 3})
1289 } /* end UEH1 */
1291 Device(SBUS) {
1292 Name(_ADR, 0x00140000)
1293 } /* end SBUS */
1295 /* Primary (and only) IDE channel */
1296 Device(IDEC) {
1297 Name(_ADR, 0x00140001)
1298 #include "acpi/ide.asl"
1299 } /* end IDEC */
1301 Device(AZHD) {
1302 Name(_ADR, 0x00140002)
1303 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1304 Field(AZPD, AnyAcc, NoLock, Preserve) {
1305 offset (0x42),
1306 NSDI, 1,
1307 NSDO, 1,
1308 NSEN, 1,
1309 offset (0x44),
1310 IPCR, 4,
1311 offset (0x54),
1312 PWST, 2,
1313 , 6,
1314 PMEB, 1,
1315 , 6,
1316 PMST, 1,
1317 offset (0x62),
1318 MMCR, 1,
1319 offset (0x64),
1320 MMLA, 32,
1321 offset (0x68),
1322 MMHA, 32,
1323 offset (0x6C),
1324 MMDT, 16,
1325 }
1327 Method(_INI) {
1328 If(LEqual(OSVR,3)){ /* If we are running Linux */
1329 Store(zero, NSEN)
1330 Store(one, NSDO)
1331 Store(one, NSDI)
1332 }
1333 }
1334 } /* end AZHD */
1336 Device(LIBR) {
1337 Name(_ADR, 0x00140003)
1338 /* Method(_INI) {
1339 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1340 } */ /* End Method(_SB.SBRDG._INI) */
1342 /* Real Time Clock Device */
1343 Device(RTC0) {
1344 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1345 Name(_CRS, ResourceTemplate() {
1346 IRQNoFlags(){8}
1347 IO(Decode16,0x0070, 0x0070, 0, 2)
1348 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1349 })
1350 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1352 Device(TMR) { /* Timer */
1353 Name(_HID,EISAID("PNP0100")) /* System Timer */
1354 Name(_CRS, ResourceTemplate() {
1355 IRQNoFlags(){0}
1356 IO(Decode16, 0x0040, 0x0040, 0, 4)
1357 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1358 })
1359 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1361 Device(SPKR) { /* Speaker */
1362 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1363 Name(_CRS, ResourceTemplate() {
1364 IO(Decode16, 0x0061, 0x0061, 0, 1)
1365 })
1366 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1368 Device(PIC) {
1369 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1370 Name(_CRS, ResourceTemplate() {
1371 IRQNoFlags(){2}
1372 IO(Decode16,0x0020, 0x0020, 0, 2)
1373 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1374 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1375 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1376 })
1377 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1379 Device(MAD) { /* 8257 DMA */
1380 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1381 Name(_CRS, ResourceTemplate() {
1382 DMA(Compatibility,BusMaster,Transfer8){4}
1383 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1384 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1385 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1386 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1387 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1388 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1389 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1390 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1392 Device(COPR) {
1393 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1394 Name(_CRS, ResourceTemplate() {
1395 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1396 IRQNoFlags(){13}
1397 })
1398 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1400 Device(HPTM) {
1401 Name(_HID,EISAID("PNP0103"))
1402 Name(CRS,ResourceTemplate() {
1403 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1404 })
1405 Method(_STA, 0) {
1406 Return(0x0F) /* sata is visible */
1407 }
1408 Method(_CRS, 0) {
1409 CreateDwordField(CRS, ^HPT._BAS, HPBX)
1410 Store(HPBA, HPBX)
1411 Return(CRS)
1412 }
1413 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1414 } /* end LIBR */
1416 Device(HPBR) {
1417 Name(_ADR, 0x00140004)
1418 } /* end HostPciBr */
1420 Device(ACAD) {
1421 Name(_ADR, 0x00140005)
1422 } /* end Ac97audio */
1424 Device(ACMD) {
1425 Name(_ADR, 0x00140006)
1426 } /* end Ac97modem */
1428 /* ITE8718 Support */
1429 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1430 Field (IOID, ByteAcc, NoLock, Preserve)
1431 {
1432 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1433 }
1435 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1436 {
1437 Offset (0x07),
1438 LDN, 8, /* Logical Device Number */
1439 Offset (0x20),
1440 CID1, 8, /* Chip ID Byte 1, 0x87 */
1441 CID2, 8, /* Chip ID Byte 2, 0x12 */
1442 Offset (0x30),
1443 ACTR, 8, /* Function activate */
1444 Offset (0xF0),
1445 APC0, 8, /* APC/PME Event Enable Register */
1446 APC1, 8, /* APC/PME Status Register */
1447 APC2, 8, /* APC/PME Control Register 1 */
1448 APC3, 8, /* Environment Controller Special Configuration Register */
1449 APC4, 8 /* APC/PME Control Register 2 */
1450 }
1452 /* Enter the 8718 MB PnP Mode */
1453 Method (EPNP)
1454 {
1455 Store(0x87, SIOI)
1456 Store(0x01, SIOI)
1457 Store(0x55, SIOI)
1458 Store(0x55, SIOI) /* 8718 magic number */
1459 }
1460 /* Exit the 8718 MB PnP Mode */
1461 Method (XPNP)
1462 {
1463 Store (0x02, SIOI)
1464 Store (0x02, SIOD)
1465 }
1466 /*
1467 * Keyboard PME is routed to SB700 Gevent3. We can wake
1468 * up the system by pressing the key.
1469 */
1470 Method (SIOS, 1)
1471 {
1472 /* We only enable KBD PME for S5. */
1473 If (LLess (Arg0, 0x05))
1474 {
1475 EPNP()
1476 /* DBGO("8718F\n") */
1478 Store (0x4, LDN)
1479 Store (One, ACTR) /* Enable EC */
1480 /*
1481 Store (0x4, LDN)
1482 Store (0x04, APC4)
1483 */ /* falling edge. which mode? Not sure. */
1485 Store (0x4, LDN)
1486 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1487 Store (0x4, LDN)
1488 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1490 XPNP()
1491 }
1492 }
1493 Method (SIOW, 0)
1494 {
1495 EPNP()
1496 Store (0x4, LDN)
1497 Store (Zero, APC0) /* disable keyboard PME */
1498 Store (0x4, LDN)
1499 Store (0xFF, APC1) /* clear keyboard PME status */
1500 XPNP()
1501 }
1503 Name(CRES, ResourceTemplate() {
1504 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1506 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1507 0x0000, /* address granularity */
1508 0x0000, /* range minimum */
1509 0x0CF7, /* range maximum */
1510 0x0000, /* translation */
1511 0x0CF8 /* length */
1512 )
1514 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1515 0x0000, /* address granularity */
1516 0x0D00, /* range minimum */
1517 0xFFFF, /* range maximum */
1518 0x0000, /* translation */
1519 0xF300 /* length */
1520 )
1522 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1523 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1524 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1525 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1527 /* DRAM Memory from 1MB to TopMem */
1528 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1530 /* BIOS space just below 4GB */
1531 DWORDMemory(
1532 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1533 0x00, /* Granularity */
1534 0x00000000, /* Min */
1535 0x00000000, /* Max */
1536 0x00000000, /* Translation */
1537 0x00000001, /* Max-Min, RLEN */
1538 ,,
1539 PCBM
1540 )
1542 /* DRAM memory from 4GB to TopMem2 */
1543 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1544 0x00000000, /* Granularity */
1545 0x00000000, /* Min */
1546 0x00000000, /* Max */
1547 0x00000000, /* Translation */
1548 0x00000001, /* Max-Min, RLEN */
1549 ,,
1550 DMHI
1551 )
1553 /* BIOS space just below 16EB */
1554 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1555 0x00000000, /* Granularity */
1556 0x00000000, /* Min */
1557 0x00000000, /* Max */
1558 0x00000000, /* Translation */
1559 0x00000001, /* Max-Min, RLEN */
1560 ,,
1561 PEBM
1562 )
1564 }) /* End Name(_SB.PCI0.CRES) */
1566 Method(_CRS, 0) {
1567 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1569 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1570 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1571 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1572 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1573 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1574 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1576 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1577 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1578 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1579 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1581 If(LGreater(LOMH, 0xC0000)){
1582 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1583 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1584 }
1586 /* Set size of memory from 1MB to TopMem */
1587 Subtract(TOM1, 0x100000, DMLL)
1589 /*
1590 * If(LNotEqual(TOM2, 0x00000000)){
1591 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1592 * ShiftLeft(TOM2, 20, Local0)
1593 * Subtract(Local0, 0x100000000, DMHL)
1594 * }
1595 */
1597 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1598 If(LEqual(TOM2, 0x00000000)){
1599 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1600 Store(PBLN,PBML)
1601 }
1602 Else { /* Otherwise, put the BIOS just below 16EB */
1603 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1604 Store(PBLN,EBML)
1605 }
1607 Return(CRES) /* note to change the Name buffer */
1608 } /* end of Method(_SB.PCI0._CRS) */
1610 /*
1611 *
1612 * FIRST METHOD CALLED UPON BOOT
1613 *
1614 * 1. If debugging, print current OS and ACPI interpreter.
1615 * 2. Get PCI Interrupt routing from ACPI VSM, this
1616 * value is based on user choice in BIOS setup.
1617 */
1618 Method(_INI, 0) {
1619 /* DBGO("\\_SB\\_INI\n") */
1620 /* DBGO(" DSDT.ASL code from ") */
1621 /* DBGO(__DATE__) */
1622 /* DBGO(" ") */
1623 /* DBGO(__TIME__) */
1624 /* DBGO("\n Sleep states supported: ") */
1625 /* DBGO("\n") */
1626 /* DBGO(" \\_OS=") */
1627 /* DBGO(\_OS) */
1628 /* DBGO("\n \\_REV=") */
1629 /* DBGO(\_REV) */
1630 /* DBGO("\n") */
1632 /* Determine the OS we're running on */
1633 OSFL()
1635 /* On older chips, clear PciExpWakeDisEn */
1636 /*if (LLessEqual(\SBRI, 0x13)) {
1637 * Store(0,\PWDE)
1638 * }
1639 */
1640 } /* End Method(_SB._INI) */
1641 } /* End Device(PCI0) */
1643 Device(PWRB) { /* Start Power button device */
1644 Name(_HID, EISAID("PNP0C0C"))
1645 Name(_UID, 0xAA)
1646 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1647 Name(_STA, 0x0B) /* sata is invisible */
1648 }
1649 } /* End \_SB scope */
1651 Scope(\_SI) {
1652 Method(_SST, 1) {
1653 /* DBGO("\\_SI\\_SST\n") */
1654 /* DBGO(" New Indicator state: ") */
1655 /* DBGO(Arg0) */
1656 /* DBGO("\n") */
1657 }
1658 } /* End Scope SI */
1660 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
1662 /* THERMAL */
1663 Scope(\_TZ) {
1664 Name (KELV, 2732)
1665 Name (THOT, 800)
1666 Name (TCRT, 850)
1668 ThermalZone(TZ00) {
1669 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1670 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1671 Return(Add(0, 2730))
1672 }
1673 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1674 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1675 Return(Package() {\_TZ.TZ00.FAN0})
1676 }
1677 Device (FAN0) {
1678 Name(_HID, EISAID("PNP0C0B"))
1679 Name(_PR0, Package() {PFN0})
1680 }
1682 PowerResource(PFN0,0,0) {
1683 Method(_STA) {
1684 Store(0xF,Local0)
1685 Return(Local0)
1686 }
1687 Method(_ON) {
1688 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1689 }
1690 Method(_OFF) {
1691 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1692 }
1693 }
1695 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1696 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1697 Return (Add (THOT, KELV))
1698 }
1699 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1700 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1701 Return (Add (TCRT, KELV))
1702 }
1703 Method(_TMP,0) { /* return current temp of this zone */
1704 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1705 If (LGreater (Local0, 0x10)) {
1706 Store (Local0, Local1)
1707 }
1708 Else {
1709 Add (Local0, THOT, Local0)
1710 Return (Add (400, KELV))
1711 }
1713 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1714 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1715 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1716 If (LGreater (Local0, 0x10)) {
1717 If (LGreater (Local0, Local1)) {
1718 Store (Local0, Local1)
1719 }
1721 Multiply (Local1, 10, Local1)
1722 Return (Add (Local1, KELV))
1723 }
1724 Else {
1725 Add (Local0, THOT, Local0)
1726 Return (Add (400 , KELV))
1727 }
1728 } /* end of _TMP */
1729 } /* end of TZ00 */
1730 }
1731 }
1732 /* End of ASL file */