src/mainboard/asus/p8h61-m_pro/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <northbridge/intel/sandybridge/raminit_native.h>
  17 #include <northbridge/intel/sandybridge/sandybridge.h>
  18 #include <southbridge/intel/bd82x6x/pch.h>
  19 #include <superio/nuvoton/common/nuvoton.h>
  20 #include <superio/nuvoton/nct6776/nct6776.h>
  21
  22 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
  23 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
  24 #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
  25
  26 void pch_enable_lpc(void)
  27 {
  28         /* Enable the Super IO */
  29         pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN |
  30                         KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
  31 }
  32
  33 void mainboard_rcba_config(void)
  34 {
  35 }
  36
  37 const struct southbridge_usb_port mainboard_usb_ports[] = {
  38         { 1, 0, 0 },
  39         { 1, 0, 0 },
  40         { 1, 0, 1 },
  41         { 1, 0, 1 },
  42         { 1, 0, 2 },
  43         { 1, 0, 2 },
  44         { 1, 0, 3 },
  45         { 1, 0, 3 },
  46         { 1, 0, 4 },
  47         { 1, 0, 4 },
  48         { 1, 0, 6 },
  49         { 1, 0, 5 },
  50         { 1, 0, 5 },
  51         { 1, 0, 6 },
  52 };
  53
  54 void mainboard_early_init(int s3resume)
  55 {
  56 }
  57
  58 void mainboard_config_superio(void)
  59 {
  60         /* Enable UART */
  61         nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
  62
  63         /* Select SIO pin states. */
  64         pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
  65         pnp_write_config(GLOBAL_DEV, 0x24, 0x30);
  66         pnp_write_config(GLOBAL_DEV, 0x27, 0x40);
  67         pnp_write_config(GLOBAL_DEV, 0x2a, 0x20);
  68
  69         /* Power RAM in S3. */
  70         pnp_set_logical_device(ACPI_DEV);
  71         pnp_write_config(ACPI_DEV, 0xe4, 0x10);
  72
  73         pnp_set_logical_device(SERIAL_DEV);
  74
  75         nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
  76
  77         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  78 }
  79
  80 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
  81 {
  82         read_spd(&spd[0], 0x50, id_only);
  83         read_spd(&spd[2], 0x52, id_only);
  84 }