src/mainboard/asus/am1i-a/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2013 Sage Electronic Engineering, LLC
   6  * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com>
   7  * Copyright (C) 2018 Gergely Kiss <mail.gery@gmail.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 /* DefinitionBlock Statement */
  20 DefinitionBlock (
  21         "DSDT.AML",     /* Output filename */
  22         "DSDT",         /* Signature */
  23         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  24         "AMD   ",       /* OEMID */
  25         "COREBOOT",     /* TABLE ID */
  26         0x00010001      /* OEM Revision */
  27         )
  28 {       /* Start of ASL file */
  29         /* #include <arch/x86/acpi/debug.asl> */        /* Include global debug methods if needed */
  30
  31         /* Globals for the platform */
  32         #include "acpi/mainboard.asl"
  33
  34         /* PCI IRQ mapping for the Southbridge */
  35         #include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
  36
  37         /* Describe the processor tree (\_PR) */
  38         #include <cpu/amd/agesa/family16kb/acpi/cpu.asl>
  39
  40         /* Contains the supported sleep states for this chipset */
  41         #include <southbridge/amd/common/acpi/sleepstates.asl>
  42
  43         /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
  44         #include "acpi/sleep.asl"
  45
  46         /* System Bus */
  47         Scope(\_SB) { /* Start \_SB scope */
  48                 /* global utility methods expected within the \_SB scope */
  49                 #include <arch/x86/acpi/globutil.asl>
  50
  51                 /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
  52                 #include "acpi/routing.asl"
  53
  54                 Device(PWRB) {
  55                         Name(_HID, EISAID("PNP0C0C"))
  56                         Name(_UID, 0xAA)
  57                         Name(_PRW, Package () {3, 0x04})
  58                         Name(_STA, 0x0B)
  59                 }
  60
  61                 Device(PCI0) {
  62                         /* Describe the AMD Northbridge */
  63                         #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl>
  64
  65                         /* Describe the AMD Fusion Controller Hub Southbridge */
  66                         #include <southbridge/amd/agesa/hudson/acpi/fch.asl>
  67                 }
  68
  69                 /* Describe PCI INT[A-H] for the Southbridge */
  70                 #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
  71
  72         } /* End \_SB scope */
  73
  74         /* Describe SMBUS for the Southbridge */
  75         #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
  76
  77         /* Define the System Indicators for the platform */
  78         #include "acpi/si.asl"
  79 }
  80 /* End of ASL file */