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AUTHORS, util/: Drop individual copyright notices
[coreboot.git] / util / inteltool / gpio.c
blob692876445aabc8a264b992eff8008b23ace84643
1 /* inteltool - dump all registers on an Intel CPU + chipset based system */
2 /*
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; version 2 of the License.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #include <stdio.h>
14 #include "inteltool.h"
15
16 typedef struct { uint16_t addr; uint32_t def; } gpio_default_t;
17
18 static const io_register_t ich0_gpio_registers[] = {
19 { 0x00, 4, "GPIO_USE_SEL" },
20 { 0x04, 4, "GP_IO_SEL" },
21 { 0x08, 4, "RESERVED" },
22 { 0x0c, 4, "GP_LVL" },
23 { 0x10, 4, "RESERVED" },
24 { 0x14, 4, "GPO_TTL" },
25 { 0x18, 4, "GPO_BLINK" },
26 { 0x1c, 4, "RESERVED" },
27 { 0x20, 4, "RESERVED" },
28 { 0x24, 4, "RESERVED" },
29 { 0x28, 4, "RESERVED" },
30 { 0x2c, 4, "GPI_INV" },
31 { 0x30, 4, "RESERVED" },
32 { 0x34, 4, "RESERVED" },
33 { 0x38, 4, "RESERVED" },
34 { 0x3C, 4, "RESERVED" }
35 };
36
37 static const io_register_t ich2_gpio_registers[] = {
38 { 0x00, 4, "GPIO_USE_SEL" },
39 { 0x04, 4, "GP_IO_SEL" },
40 { 0x08, 4, "RESERVED" },
41 { 0x0c, 4, "GP_LVL" },
42 { 0x10, 4, "RESERVED" },
43 { 0x14, 4, "GPO_TTL" },
44 { 0x18, 4, "GPO_BLINK" },
45 { 0x1c, 4, "RESERVED" },
46 { 0x20, 4, "RESERVED" },
47 { 0x24, 4, "RESERVED" },
48 { 0x28, 4, "RESERVED" },
49 { 0x2c, 4, "GPI_INV" },
50 { 0x30, 4, "RESERVED" },
51 { 0x34, 4, "RESERVED" },
52 { 0x38, 4, "RESERVED" },
53 { 0x3C, 4, "RESERVED" }
54 };
55
56 static const io_register_t ich4_gpio_registers[] = {
57 { 0x00, 4, "GPIO_USE_SEL" },
58 { 0x04, 4, "GP_IO_SEL" },
59 { 0x08, 4, "RESERVED" },
60 { 0x0c, 4, "GP_LVL" },
61 { 0x10, 4, "RESERVED" },
62 { 0x14, 4, "GPO_TTL" },
63 { 0x18, 4, "GPO_BLINK" },
64 { 0x1c, 4, "RESERVED" },
65 { 0x20, 4, "RESERVED" },
66 { 0x24, 4, "RESERVED" },
67 { 0x28, 4, "RESERVED" },
68 { 0x2c, 4, "GPI_INV" },
69 { 0x30, 4, "GPIO_USE_SEL2" },
70 { 0x34, 4, "GP_IO_SEL2" },
71 { 0x38, 4, "GP_LVL2" },
72 { 0x3C, 4, "RESERVED" }
73 };
74
75 static const io_register_t ich5_gpio_registers[] = {
76 { 0x00, 4, "GPIO_USE_SEL" },
77 { 0x04, 4, "GP_IO_SEL" },
78 { 0x08, 4, "RESERVED" },
79 { 0x0c, 4, "GP_LVL" },
80 { 0x10, 4, "RESERVED" },
81 { 0x14, 4, "GPO_TTL"},
82 { 0x18, 4, "GPO_BLINK"},
83 { 0x1c, 4, "RESERVED" },
84 { 0x20, 4, "RESERVED" },
85 { 0x2c, 4, "GPI_INV" },
86 { 0x30, 4, "GPIO_USE_SEL2" },
87 { 0x34, 4, "GP_IO_SEL2" },
88 { 0x38, 4, "GP_LVL2" },
89 };
90
91 static const io_register_t ich6_gpio_registers[] = {
92 { 0x00, 4, "GPIO_USE_SEL" },
93 { 0x08, 4, "RESERVED" },
94 { 0x0c, 4, "GP_LVL" },
95 { 0x10, 4, "RESERVED" },
96 { 0x14, 4, "RESERVED" },
97 { 0x18, 4, "GPO_BLINK" },
98 { 0x1c, 4, "RESERVED" },
99 { 0x20, 4, "RESERVED" },
100 { 0x24, 4, "RESERVED" },
101 { 0x28, 4, "RESERVED" },
102 { 0x2c, 4, "GPI_INV" },
103 { 0x30, 4, "GPIO_USE_SEL2" },
104 { 0x34, 4, "GP_IO_SEL2" },
105 { 0x38, 4, "GP_LVL2" },
106 { 0x04, 4, "GP_IO_SEL" },
107 };
108
109 static const io_register_t ich7_gpio_registers[] = {
110 { 0x00, 4, "GPIO_USE_SEL" },
111 { 0x04, 4, "GP_IO_SEL" },
112 { 0x08, 4, "RESERVED" },
113 { 0x0c, 4, "GP_LVL" },
114 { 0x10, 4, "RESERVED" },
115 { 0x14, 4, "RESERVED" },
116 { 0x18, 4, "GPO_BLINK" },
117 { 0x1c, 4, "RESERVED" },
118 { 0x20, 4, "RESERVED" },
119 { 0x24, 4, "RESERVED" },
120 { 0x28, 4, "RESERVED" },
121 { 0x2c, 4, "GPI_INV" },
122 { 0x30, 4, "GPIO_USE_SEL2" },
123 { 0x34, 4, "GP_IO_SEL2" },
124 { 0x38, 4, "GP_LVL2" },
125 { 0x3C, 4, "RESERVED" }
126 };
127
128 static const io_register_t ich8_gpio_registers[] = {
129 { 0x00, 4, "GPIO_USE_SEL" },
130 { 0x04, 4, "GP_IO_SEL" },
131 { 0x08, 4, "RESERVED" },
132 { 0x0c, 4, "GP_LVL" },
133 { 0x10, 4, "GPIO_USE_SEL Override (LOW)" },
134 { 0x14, 4, "RESERVED" },
135 { 0x18, 4, "GPO_BLINK" },
136 { 0x1c, 4, "GP_SER_BLINK" },
137 { 0x20, 4, "GP_SB_CMDSTS" },
138 { 0x24, 4, "GP_SB_DATA" },
139 { 0x28, 4, "RESERVED" },
140 { 0x2c, 4, "GPI_INV" },
141 { 0x30, 4, "GPIO_USE_SEL2" },
142 { 0x34, 4, "GP_IO_SEL2" },
143 { 0x38, 4, "GP_LVL2" },
144 { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" }
145 };
146
147 static const io_register_t ich9_gpio_registers[] = {
148 { 0x00, 4, "GPIO_USE_SEL" },
149 { 0x04, 4, "GP_IO_SEL" },
150 { 0x08, 4, "RESERVED" },
151 { 0x0c, 4, "GP_LVL" },
152 { 0x10, 4, "RESERVED" },
153 { 0x14, 4, "RESERVED" },
154 { 0x18, 4, "GPO_BLINK" },
155 { 0x1c, 4, "GP_SER_BLINK" },
156 { 0x20, 4, "GP_SB_CMDSTS" },
157 { 0x24, 4, "GP_SB_DATA" },
158 { 0x28, 4, "RESERVED" },
159 { 0x2c, 4, "GPI_INV" },
160 { 0x30, 4, "GPIO_USE_SEL2" },
161 { 0x34, 4, "GP_IO_SEL2" },
162 { 0x38, 4, "GP_LVL2" },
163 { 0x3C, 4, "RESERVED" }
164 };
165
166 static const io_register_t ich10_gpio_registers[] = {
167 { 0x00, 4, "GPIO_USE_SEL" },
168 { 0x04, 4, "GP_IO_SEL" },
169 { 0x08, 4, "RESERVED" },
170 { 0x0c, 4, "GP_LVL" },
171 { 0x10, 4, "RESERVED" },
172 { 0x14, 4, "RESERVED" },
173 { 0x18, 4, "GPO_BLINK" },
174 { 0x1c, 4, "GP_SER_BLINK" },
175 { 0x20, 4, "GP_SB_CMDSTS" },
176 { 0x24, 4, "GP_SB_DATA" },
177 { 0x28, 4, "RESERVED" },
178 { 0x2c, 4, "GPI_INV" },
179 { 0x30, 4, "GPIO_USE_SEL2" },
180 { 0x34, 4, "GP_IO_SEL2" },
181 { 0x38, 4, "GP_LVL2" },
182 { 0x3C, 4, "RESERVED" },
183 { 0x40, 4, "GPIO_USE_SEL3" },
184 { 0x44, 4, "GP_IO_SEL3" },
185 { 0x48, 4, "GPIO_LVL3" },
186 { 0x4c, 4, "RESERVED" },
187 { 0x50, 4, "RESERVED" },
188 { 0x54, 4, "RESERVED" },
189 { 0x58, 4, "RESERVED" },
190 { 0x5c, 4, "RESERVED" },
191 { 0x60, 4, "GP_RST_SEL" },
192 { 0x64, 4, "RESERVED" },
193 { 0x68, 4, "RESERVED" },
194 { 0x6c, 4, "RESERVED" },
195 { 0x70, 4, "RESERVED" },
196 { 0x74, 4, "RESERVED" },
197 { 0x78, 4, "RESERVED" },
198 { 0x7c, 4, "RESERVED" },
199 };
200
201 static const io_register_t i631x_gpio_registers[] = {
202 { 0x00, 4, "GPIO_USE_SEL" },
203 { 0x04, 4, "GP_IO_SEL" },
204 { 0x08, 4, "RESERVED" },
205 { 0x0c, 4, "GP_LVL" },
206 { 0x10, 4, "RESERVED" },
207 { 0x14, 4, "RESERVED" },
208 { 0x18, 4, "GPO_BLINK" },
209 { 0x1c, 4, "RESERVED" },
210 { 0x20, 4, "RESERVED" },
211 { 0x24, 4, "RESERVED" },
212 { 0x28, 4, "RESERVED" },
213 { 0x2c, 4, "GPI_INV" },
214 { 0x30, 4, "GPIO_USE_SEL2" },
215 { 0x34, 4, "GP_IO_SEL2" },
216 { 0x38, 4, "GP_LVL2" },
217 };
218
219 static const io_register_t pch_gpio_registers[] = {
220 { 0x00, 4, "GPIO_USE_SEL" },
221 { 0x04, 4, "GP_IO_SEL" },
222 { 0x08, 4, "RESERVED" },
223 { 0x0c, 4, "GP_LVL" },
224 { 0x10, 4, "RESERVED" },
225 { 0x14, 4, "RESERVED" },
226 { 0x18, 4, "GPO_BLINK" },
227 { 0x1c, 4, "GP_SER_BLINK" },
228 { 0x20, 4, "GP_SB_CMDSTS" },
229 { 0x24, 4, "GP_SB_DATA" },
230 { 0x28, 2, "GPI_NMI_EN" },
231 { 0x2a, 2, "GPI_NMI_STS" },
232 { 0x2c, 4, "GPI_INV" },
233 { 0x30, 4, "GPIO_USE_SEL2" },
234 { 0x34, 4, "GP_IO_SEL2" },
235 { 0x38, 4, "GP_LVL2" },
236 { 0x3c, 4, "RESERVED" },
237 { 0x40, 4, "GPIO_USE_SEL3" },
238 { 0x44, 4, "GP_IO_SEL3" },
239 { 0x48, 4, "GPIO_LVL3" },
240 { 0x4c, 4, "RESERVED" },
241 { 0x50, 4, "RESERVED" },
242 { 0x54, 4, "RESERVED" },
243 { 0x58, 4, "RESERVED" },
244 { 0x5c, 4, "RESERVED" },
245 { 0x60, 4, "GP_RST_SEL1" },
246 { 0x64, 4, "GP_RST_SEL2" },
247 { 0x68, 4, "GP_RST_SEL3" },
248 { 0x6c, 4, "RESERVED" },
249 { 0x70, 4, "RESERVED" },
250 { 0x74, 4, "RESERVED" },
251 { 0x78, 4, "RESERVED" },
252 { 0x7c, 4, "RESERVED" },
253 };
254 /* Default values for Ibex Peak desktop chipsets */
255 static const gpio_default_t ip_pch_desktop_defaults[] = {
256 { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */
257 { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */
258 { 0x0c, 0x02fe0100 }, /* GP_LVL */
259 { 0x18, 0x00040000 }, /* GPO_BLINK */
260 { 0x1c, 0x00000000 }, /* GP_SER_BLINK */
261 { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */
262 { 0x2c, 0x00000000 }, /* GP_INV */
263 { 0x30, 0x020300ff }, /* GPIO_USE_SEL2 */
264 { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */
265 { 0x38, 0xa4aa0003 }, /* GP_LVL2 */
266 { 0x40, 0x00000100 }, /* GPIO_USE_SEL3 */
267 { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */
268 { 0x48, 0x00000000 }, /* GP_LVL3 */
269 { 0x60, 0x01000000 }, /* GP_RST_SEL1 */
270 { 0x64, 0x00000000 }, /* GP_RST_SEL2 */
271 { 0x68, 0x00000000 }, /* GP_RST_SEL3 */
272 };
273 /* Default values for Ibex Peak mobile chipsets */
274 static const gpio_default_t ip_pch_mobile_defaults[] = {
275 { 0x00, 0xf96ba1ff }, /* GPIO_USE_SEL */
276 { 0x04, 0xf6ff6eff }, /* GP_IO_SEL */
277 { 0x0c, 0x02fe0100 }, /* GP_LVL */
278 { 0x18, 0x00040000 }, /* GPO_BLINK */
279 { 0x1c, 0x00000000 }, /* GP_SER_BLINK */
280 { 0x28, 0x00000000 }, /* GP_NMI_EN + GPI_NMI_STS */
281 { 0x2c, 0x00000000 }, /* GP_INV */
282 { 0x30, 0x020300fe }, /* GPIO_USE_SEL2 */
283 { 0x34, 0x1f57fff4 }, /* GP_IO_SEL2 */
284 { 0x38, 0xa4aa0003 }, /* GP_LVL2 */
285 { 0x40, 0x00000000 }, /* GPIO_USE_SEL3 */
286 { 0x44, 0x00000f00 }, /* GP_IO_SEL3 */
287 { 0x48, 0x00000000 }, /* GP_LVL3 */
288 { 0x60, 0x01000000 }, /* GP_RST_SEL1 */
289 { 0x64, 0x00000000 }, /* GP_RST_SEL2 */
290 { 0x68, 0x00000000 }, /* GP_RST_SEL3 */
291 };
292
293 static const io_register_t lynxpoint_lp_gpio_registers[] = {
294 { 0x00, 4, "GPIO_OWN1" }, // GPIO Ownership
295 { 0x04, 4, "GPIO_OWN2" }, // GPIO Ownership
296 { 0x08, 4, "GPIO_OWN3" }, // GPIO Ownership
297 { 0x0c, 4, "RESERVED" }, // Reserved
298 { 0x10, 2, "GPIPRIOQ2IOXAPIC" }, // GPI PIRQ[X:I] to IOxAPIC[39:24] Enable
299 { 0x12, 2, "RESERVED" }, // Reserved
300 { 0x14, 4, "RESERVED" }, // Reserved
301 { 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable
302 { 0x1c, 4, "GP_SER_BLINK" }, // GP Serial Blink
303 { 0x20, 4, "GP_SB_CMDSTS" }, // GP Serial Blink Command Status
304 { 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data
305 { 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable
306 { 0x2a, 2, "GPI_NMI_STS" }, // GPI NMI Status
307 { 0x2c, 4, "RESERVED" }, // Reserved
308 { 0x30, 4, "GPI_ROUT" }, // GPI Interrupt Input Route
309 { 0x34, 4, "RESERVED" }, // Reserved
310 { 0x38, 4, "RESERVED" }, // Reserved
311 { 0x3C, 4, "RESERVED" }, // Reserved
312 { 0x40, 4, "RESERVED" }, // Reserved
313 { 0x44, 4, "RESERVED" }, // Reserved
314 { 0x48, 4, "RESERVED" }, // Reserved
315 { 0x4C, 4, "RESERVED" }, // Reserved
316 { 0x50, 4, "ALT_GPI_SMI_STS" }, // Alternate GPI SMI Status
317 { 0x54, 4, "ALT_GPI_SMI_EN" }, // Alternate GPI SMI Enable
318 { 0x58, 4, "RESERVED" }, // Reserved
319 { 0x5C, 4, "RESERVED" }, // Reserved
320 { 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1
321 { 0x64, 4, "GP_RST_SEL2" }, // GPIO Reset Select 2
322 { 0x68, 4, "GP_RST_SEL3" }, // GPIO Reset Select 3
323 { 0x6c, 4, "RESERVED" }, // Reserved
324 { 0x70, 4, "RESERVED" }, // Reserved
325 { 0x74, 4, "RESERVED" }, // Reserved
326 { 0x78, 4, "RESERVED" }, // Reserved
327 { 0x7c, 4, "GPIO_GC" }, // GPIO Global Configuration
328 { 0x80, 4, "GPI_IS[31:0]" }, // GPI Interrupt Status [31:0]
329 { 0x84, 4, "GPI_IS[63:32]" }, // GPI Interrupt Status [63:32]
330 { 0x88, 4, "GPI_IS[94:64]" }, // GPI Interrupt Status [94:64]
331 { 0x8C, 4, "RESERVED" }, // Reserved
332 { 0x90, 4, "GPI_IE[31:0]" }, // GPI Interrupt Enable [31:0]
333 { 0x94, 4, "GPI_IE[63:32]" }, // GPI Interrupt Enable [63:32]
334 { 0x98, 4, "GPI_IE[94:64]" }, // GPI Interrupt Enable [94:64]
335 { 0x9C, 4, "RESERVED" }, // Reserved
336 /* { 0x100, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 0) */
337 /* { 0x104, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 0) */
338 /* { ... } GPIO size = 95 */
339 /* { 0x3f0, 4, "GPnCONFIGA" }, // GPIO Configuration A Register (n = 94) */
340 /* { 0x3f4, 4, "GPnCONFIGB" }, // GPIO Configuration B Register (n = 94) */
341
342 };
343
344 /* Default values for Cougar Point desktop chipsets */
345 static const gpio_default_t cp_pch_desktop_defaults[] = {
346 { 0x00, 0xb96ba1ff },
347 { 0x04, 0xf6ff6eff },
348 { 0x0c, 0x02fe0100 },
349 { 0x18, 0x00040000 },
350 { 0x28, 0x00000000 },
351 { 0x2c, 0x00000000 },
352 { 0x30, 0x020300ff },
353 { 0x34, 0x1f57fff4 },
354 { 0x38, 0xa4aa0007 },
355 { 0x40, 0x00000130 },
356 { 0x44, 0x00000ff0 },
357 { 0x48, 0x000000c0 },
358 { 0x60, 0x01000000 },
359 { 0x64, 0x00000000 },
360 { 0x68, 0x00000000 },
361 };
362 /* Default values for Cougar Point mobile chipsets */
363 static const gpio_default_t cp_pch_mobile_defaults[] = {
364 { 0x00, 0xb96ba1ff },
365 { 0x04, 0xf6ff6eff },
366 { 0x0c, 0x02fe0100 },
367 { 0x18, 0x00040000 },
368 { 0x28, 0x00000000 },
369 { 0x2c, 0x00000000 },
370 { 0x30, 0x020300fe },
371 { 0x34, 0x1f57fff4 },
372 { 0x38, 0xa4aa0007 },
373 { 0x40, 0x00000030 },
374 { 0x44, 0x00000ff0 },
375 { 0x48, 0x000000c0 },
376 { 0x60, 0x01000000 },
377 { 0x64, 0x00000000 },
378 { 0x68, 0x00000000 },
379 };
380 /* Default values for Panther Point desktop chipsets */
381 static const gpio_default_t pp_pch_desktop_defaults[] = {
382 { 0x00, 0xb96ba1ff },
383 { 0x04, 0xeeff6eff },
384 { 0x0c, 0x02fe0100 },
385 { 0x18, 0x00040000 },
386 { 0x28, 0x00000000 },
387 { 0x2c, 0x00000000 },
388 { 0x30, 0x020300ff },
389 { 0x34, 0x1f57fff4 },
390 { 0x38, 0xa4aa0007 },
391 { 0x40, 0x00000130 },
392 { 0x44, 0x00000ff0 },
393 { 0x48, 0x000000c0 },
394 { 0x60, 0x01000000 },
395 { 0x64, 0x00000000 },
396 { 0x68, 0x00000000 },
397 };
398 /* Default values for Panther Point mobile chipsets */
399 static const gpio_default_t pp_pch_mobile_defaults[] = {
400 { 0x00, 0xb96ba1ff },
401 { 0x04, 0xeeff6eff },
402 { 0x0c, 0x02fe0100 },
403 { 0x18, 0x00040000 },
404 { 0x28, 0x00000000 },
405 { 0x2c, 0x00000000 },
406 { 0x30, 0x020300fe },
407 { 0x34, 0x1f57fff4 },
408 { 0x38, 0xa4aa0007 },
409 { 0x40, 0x00000030 },
410 { 0x44, 0x00000ff0 },
411 { 0x48, 0x000000c0 },
412 { 0x60, 0x01000000 },
413 { 0x64, 0x00000000 },
414 { 0x68, 0x00000000 },
415 };
416
417 /* Baytrail */
418 static const io_register_t baytrail_score_ssus_gpio_registers[] = {
419 { 0x00, 4, "SC_USE_SEL_31_0_" },
420 { 0x04, 4, "SC_IO_SEL_31_0_" },
421 { 0x08, 4, "SC_GP_LVL_31_0_)" },
422 { 0x0C, 4, "SC_TPE_31_0_" },
423 { 0x10, 4, "SC_TNE_31_0_" },
424 { 0x14, 4, "SC_TS_31_0_" },
425 { 0x20, 4, "SC_USE_SEL_63_32_" },
426 { 0x24, 4, "SC_IO_SEL_63_32_" },
427 { 0x28, 4, "SC_GP_LVL_63_32_" },
428 { 0x2C, 4, "SC_TPE_63_32_" },
429 { 0x30, 4, "SC_TNE_63_32_" },
430 { 0x34, 4, "SC_TS_63_32_" },
431 { 0x40, 4, "SC_USE_SEL_95_64_" },
432 { 0x44, 4, "SC_IO_SEL_95_64_" },
433 { 0x48, 4, "SC_GP_LVL_95_64_" },
434 { 0x4C, 4, "SC_TPE_95_64_" },
435 { 0x50, 4, "SC_TNE_95_64_" },
436 { 0x54, 4, "SC_TS_95_64_" },
437 { 0x58, 4, "SC_USE_SEL_127_96_" },
438 { 0x64, 4, "SC_IO_SEL_127_96_" },
439 { 0x68, 4, "SC_GP_LVL_127_96_" },
440 { 0x6C, 4, "SC_TPE_127_96_" },
441 { 0x70, 4, "SC_TNE_127_96_" },
442 { 0x74, 4, "SC_TS_127_96_" },
443
444 { 0x80 + 0x00, 4, "SUS_USE_SEL_31_0_" },
445 { 0x80 + 0x04, 4, "SUS_IO_SEL_31_0_" },
446 { 0x80 + 0x08, 4, "SUS_GP_LVL_31_0_" },
447 { 0x80 + 0x0c, 4, "SUS_TPE_31_0_" },
448 { 0x80 + 0x10, 4, "SUS_TNE_31_0_" },
449 { 0x80 + 0x14, 4, "SUS_TS_31_0_" },
450 { 0x80 + 0x18, 4, "SUS_WAKE_EN_31_0_" },
451 { 0x80 + 0x20, 4, "SUS_USE_SEL_43_32_" },
452 { 0x80 + 0x24, 4, "SUS_IO_SEL_43_32_" },
453 { 0x80 + 0x28, 4, "SUS_GP_LVL_43_32_" },
454 { 0x80 + 0x2c, 4, "SUS_TPE_43_32_" },
455 { 0x80 + 0x30, 4, "SUS_TNE_43_32_" },
456 { 0x80 + 0x34, 4, "SUS_TS_43_32_" },
457 { 0x80 + 0x38, 4, "SUS_WAKE_EN_43_32_" }
458 };
459
460 /* Description of GPIO 'bank' ex. {ncore, score. ssus} */
461 struct gpio_bank {
462 const uint32_t gpio_count;
463 const u8* gpio_to_pad;
464 const unsigned long pad_base_offset;
465 const char* gpio_name;
466 const char ** func_names;
467 };
468
469 /* Number of GPIOs in each bank */
470 #define BANK_COUNT 3
471 #define GPNCORE_COUNT 27
472 #define GPSCORE_COUNT 102
473 #define GPSSUS_COUNT 44
474
475 /* IO Memory offsets */
476 #define IO_BASE_OFFSET_GPNCORE 0x1000
477 #define IO_BASE_OFFSET_GPSCORE 0x0000
478 #define IO_BASE_OFFSET_GPSSUS 0x2000
479
480 static const char *ncore_func_names[GPNCORE_COUNT * 8] = {
481 "GPIO_S0_NC[00]", "RESERVED", "DDI0_HPD", "-", "-", "-", "-", "-",
482 "GPIO_S0_NC[01]", "-", "DDI0_DDCDATA", "-", "-", "-", "-", "-",
483 "GPIO_S0_NC[02]", "-", "DDI0_DDCCLK", "-", "-", "-", "-", "-",
484 "GPIO_S0_NC[03]", "-", "DDI0_VDDEN", "-", "-", "-", "-", "-",
485 "GPIO_S0_NC[04]", "-", "DDI0_BKLTEN", "-", "-", "-", "-", "-",
486 "GPIO_S0_NC[05]", "-", "DDI0_BKLTCTL", "-", "-", "-", "-", "-",
487 "GPIO_S0_NC[06]", "RESERVED", "DDI1_HPD", "-", "-", "-", "-", "-",
488 "GPIO_S0_NC[07]", "-", "DDI1_DDCDATA", "-", "-", "-", "-", "-",
489 "GPIO_S0_NC[08]", "-", "DDI1_DDCCLK", "-", "-", "-", "-", "-",
490 "GPIO_S0_NC[09]", "RESERVED", "DDI1_VDDEN", "-", "-", "-", "-", "-",
491 "GPIO_S0_NC[10]", "RESERVED", "DDI1_BKLTEN", "-", "-", "-", "-", "-",
492 "GPIO_S0_NC[11]", "RESERVED", "DDI1_BKLTCTL", "-", "-", "-", "-", "-",
493 "GPIO_S0_NC[12]", "RESERVED", "-", "-", "-", "-", "-", "-",
494 "GPIO_S0_NC[13]", "RESERVED", "-", "-", "-", "-", "-", "-",
495 "GPIO_S0_NC[14]", "RESERVED", "-", "-", "-", "-", "-", "-",
496 "GPIO_S0_NC[15]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
497 "GPIO_S0_NC[16]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
498 "GPIO_S0_NC[17]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
499 "GPIO_S0_NC[18]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
500 "GPIO_S0_NC[19]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
501 "GPIO_S0_NC[20]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
502 "GPIO_S0_NC[21]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
503 "GPIO_S0_NC[22]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
504 "GPIO_S0_NC[23]", "RESERVED", "RESERVED", "-", "-", "-", "-", "-",
505 "GPIO_S0_NC[24]", "RESERVED", "-", "-", "-", "-", "-", "-",
506 "GPIO_S0_NC[25]", "RESERVED", "-", "-", "-", "-", "-", "-",
507 "GPIO_S0_NC[26]", "RESERVED", "-", "-", "-", "-", "-", "-",
508 };
509
510 static const char *score_func_names[GPSCORE_COUNT * 8] = {
511 "GPIO_S0_SC[000]", "SATA_GP[0]", "-", "-", "-", "-", "-", "-",
512 "GPIO_S0_SC[001]", "SATA_GP[1]", "SATA_DEVSLP[0]", "-", "-", "-", "-", "-",
513 "GPIO_S0_SC[002]", "SATA_LED#", "-", "-", "-", "-", "-", "-",
514 "GPIO_S0_SC[003]", "PCIE_CLKREQ[0]#", "-", "-", "-", "-", "-", "-",
515 "GPIO_S0_SC[004]", "PCIE_CLKREQ[1]#", "-", "-", "-", "-", "-", "-",
516 "GPIO_S0_SC[005]", "PCIE_CLKREQ[2]#", "-", "-", "-", "-", "-", "-",
517 "GPIO_S0_SC[006]", "PCIE_CLKREQ[3]#", "-", "-", "-", "-", "-", "-",
518 "GPIO_S0_SC[007]", "RESERVED", "SD3_WP", "-", "-", "-", "-", "-",
519 "GPIO_S0_SC[008]", "I2S0_CLK", "HDA_RST#", "-", "-", "-", "-", "-",
520 "GPIO_S0_SC[009]", "I2S0_FRM", "HDA_SYNC", "-", "-", "-", "-", "-",
521 "GPIO_S0_SC[010]", "I2S0_DATAOUT", "HDA_CLK", "-", "-", "-", "-", "-",
522 "GPIO_S0_SC[011]", "I2S0_DATAIN", "HDA_SDO", "-", "-", "-", "-", "-",
523 "GPIO_S0_SC[012]", "I2S1_CLK", "HDA_SDI[0]", "-", "-", "-", "-", "-",
524 "GPIO_S0_SC[013]", "I2S1_FRM", "HDA_SDI[1]", "-", "-", "-", "-", "-",
525 "GPIO_S0_SC[014]", "I2S1_DATAOUT", "RESERVED", "-", "-", "-", "-", "-",
526 "GPIO_S0_SC[015]", "I2S1_DATAIN", "RESERVED", "-", "-", "-", "-", "-",
527 "GPIO_S0_SC[016]", "MMC1_CLK", "-", "MMC1_45_CLK", "-", "-", "-", "-",
528 "GPIO_S0_SC[017]", "MMC1_D[0]", "-", "MMC1_45_D[0]", "-", "-", "-", "-",
529 "GPIO_S0_SC[018]", "MMC1_D[1]", "-", "MMC1_45_D[1]", "-", "-", "-", "-",
530 "GPIO_S0_SC[019]", "MMC1_D[2]", "-", "MMC1_45_D[2]", "-", "-", "-", "-",
531 "GPIO_S0_SC[020]", "MMC1_D[3]", "-", "MMC1_45_D[3]", "-", "-", "-", "-",
532 "GPIO_S0_SC[021]", "MMC1_D[4]", "-", "MMC1_45_D[4]", "-", "-", "-", "-",
533 "GPIO_S0_SC[022]", "MMC1_D[5]", "-", "MMC1_45_D[5]", "-", "-", "-", "-",
534 "GPIO_S0_SC[023]", "MMC1_D[6]", "-", "MMC1_45_D[6]", "-", "-", "-", "-",
535 "GPIO_S0_SC[024]", "MMC1_D[7]", "-", "MMC1_45_D[7]", "-", "-", "-", "-",
536 "GPIO_S0_SC[025]", "MMC1_CMD", "-", "MMC1_45_CMD", "-", "-", "-", "-",
537 "GPIO_S0_SC[026]", "MMC1_RST#", "SATA_DEVSLP[0]", "MMC1_45_RST#", "-", "-", "-", "-",
538 "GPIO_S0_SC[027]", "SD2_CLK", "-", "-", "-", "-", "-", "-",
539 "GPIO_S0_SC[028]", "SD2_D[0]", "-", "-", "-", "-", "-", "-",
540 "GPIO_S0_SC[029]", "SD2_D[1]", "-", "-", "-", "-", "-", "-",
541 "GPIO_S0_SC[030]", "SD2_D[2]", "-", "-", "-", "-", "-", "-",
542 "GPIO_S0_SC[031]", "SD2_D[3]_CD#", "-", "-", "-", "-", "-", "-",
543 "GPIO_S0_SC[032]", "SD2_CMD", "-", "-", "-", "-", "-", "-",
544 "GPIO_S0_SC[033]", "SD3_CLK", "-", "-", "-", "-", "-", "-",
545 "GPIO_S0_SC[034]", "SD3_D[0]", "-", "-", "-", "-", "-", "-",
546 "GPIO_S0_SC[035]", "SD3_D[1]", "-", "-", "-", "-", "-", "-",
547 "GPIO_S0_SC[036]", "SD3_D[2]", "-", "-", "-", "-", "-", "-",
548 "GPIO_S0_SC[037]", "SD3_D[3]", "-", "-", "-", "-", "-", "-",
549 "GPIO_S0_SC[038]", "SD3_CD#", "-", "-", "-", "-", "-", "-",
550 "GPIO_S0_SC[039]", "SD3_CMD", "-", "-", "-", "-", "-", "-",
551 "GPIO_S0_SC[040]", "SD3_1P8EN", "-", "-", "-", "-", "-", "-",
552 "GPIO_S0_SC[041]", "SD3_PWREN#", "-", "-", "-", "-", "-", "-",
553 "GPIO_S0_SC[042]", "ILB_LPC_AD[0]", "-", "-", "-", "-", "-", "-",
554 "GPIO_S0_SC[043]", "ILB_LPC_AD[1]", "-", "-", "-", "-", "-", "-",
555 "GPIO_S0_SC[044]", "ILB_LPC_AD[2]", "-", "-", "-", "-", "-", "-",
556 "GPIO_S0_SC[045]", "ILB_LPC_AD[3]", "-", "-", "-", "-", "-", "-",
557 "GPIO_S0_SC[046]", "ILB_LPC_FRAME#", "-", "-", "-", "-", "-", "-",
558 "GPIO_S0_SC[047]", "ILB_LPC_CLK[0]", "-", "-", "-", "-", "-", "-",
559 "GPIO_S0_SC[048]", "ILB_LPC_CLK[1]", "-", "-", "-", "-", "-", "-",
560 "GPIO_S0_SC[049]", "ILB_LPC_CLKRUN#", "-", "-", "-", "-", "-", "-",
561 "GPIO_S0_SC[050]", "ILB_LPC_SERIRQ", "-", "-", "-", "-", "-", "-",
562 "GPIO_S0_SC[051]", "PCU_SMB_DATA", "-", "-", "-", "-", "-", "-",
563 "GPIO_S0_SC[052]", "PCU_SMB_CLK", "-", "-", "-", "-", "-", "-",
564 "GPIO_S0_SC[053]", "PCU_SMB_ALERT#", "-", "-", "-", "-", "-", "-",
565 "GPIO_S0_SC[054]", "ILB_8254_SPKR", "RESERVED", "-", "-", "-", "-", "-",
566 "GPIO_S0_SC[055]", "RESERVED", "-", "-", "-", "-", "-", "-",
567 "GPIO_S0_SC[056]", "RESERVED", "-", "-", "-", "-", "-", "-",
568 "GPIO_S0_SC[057]", "PCU_UART_TXD", "-", "-", "-", "-", "-", "-",
569 "GPIO_S0_SC[058]", "RESERVED", "-", "-", "-", "-", "-", "-",
570 "GPIO_S0_SC[059]", "RESERVED", "-", "-", "-", "-", "-", "-",
571 "GPIO_S0_SC[060]", "RESERVED", "-", "-", "-", "-", "-", "-",
572 "GPIO_S0_SC[061]", "PCU_UART_RXD", "-", "-", "-", "-", "-", "-",
573 "GPIO_S0_SC[062]", "LPE_I2S2_CLK", "SATA_DEVSLP[1]", "RESERVED", "-", "-", "-", "-",
574 "GPIO_S0_SC[063]", "LPE_I2S2_FRM", "RESERVED", "-", "-", "-", "-", "-",
575 "GPIO_S0_SC[064]", "LPE_I2S2_DATAIN", "-", "-", "-", "-", "-", "-",
576 "GPIO_S0_SC[065]", "LPE_I2S2_DATAOUT", "-", "-", "-", "-", "-", "-",
577 "GPIO_S0_SC[066]", "SIO_SPI_CS#", "-", "-", "-", "-", "-", "-",
578 "GPIO_S0_SC[067]", "SIO_SPI_MISO", "-", "-", "-", "-", "-", "-",
579 "GPIO_S0_SC[068]", "SIO_SPI_MOSI", "-", "-", "-", "-", "-", "-",
580 "GPIO_S0_SC[069]", "SIO_SPI_CLK", "-", "-", "-", "-", "-", "-",
581 "GPIO_S0_SC[070]", "SIO_UART1_RXD", "RESERVED", "-", "-", "-", "-", "-",
582 "GPIO_S0_SC[071]", "SIO_UART1_TXD", "RESERVED", "-", "-", "-", "-", "-",
583 "GPIO_S0_SC[072]", "SIO_UART1_RTS#", "-", "-", "-", "-", "-", "-",
584 "GPIO_S0_SC[073]", "SIO_UART1_CTS#", "-", "-", "-", "-", "-", "-",
585 "GPIO_S0_SC[074]", "SIO_UART2_RXD", "-", "-", "-", "-", "-", "-",
586 "GPIO_S0_SC[075]", "SIO_UART2_TXD", "-", "-", "-", "-", "-", "-",
587 "GPIO_S0_SC[076]", "SIO_UART2_RTS#", "-", "-", "-", "-", "-", "-",
588 "GPIO_S0_SC[077]", "SIO_UART2_CTS#", "-", "-", "-", "-", "-", "-",
589 "GPIO_S0_SC[078]", "SIO_I2C0_DATA", "-", "-", "-", "-", "-", "-",
590 "GPIO_S0_SC[079]", "SIO_I2C0_CLK", "-", "-", "-", "-", "-", "-",
591 "GPIO_S0_SC[080]", "SIO_I2C1_DATA", "-", "-", "-", "-", "-", "-",
592 "GPIO_S0_SC[081]", "SIO_I2C1_CLK", "RESERVED", "-", "-", "-", "-", "-",
593 "GPIO_S0_SC[082]", "SIO_I2C2_DATA", "-", "-", "-", "-", "-", "-",
594 "GPIO_S0_SC[083]", "SIO_I2C2_CLK", "-", "-", "-", "-", "-", "-",
595 "GPIO_S0_SC[084]", "SIO_I2C3_DATA", "-", "-", "-", "-", "-", "-",
596 "GPIO_S0_SC[085]", "SIO_I2C3_CLK", "-", "-", "-", "-", "-", "-",
597 "GPIO_S0_SC[086]", "SIO_I2C4_DATA", "-", "-", "-", "-", "-", "-",
598 "GPIO_S0_SC[087]", "SIO_I2C4_CLK", "-", "-", "-", "-", "-", "-",
599 "GPIO_S0_SC[088]", "SIO_I2C5_DATA", "-", "-", "-", "-", "-", "-",
600 "GPIO_S0_SC[089]", "SIO_I2C5_CLK", "-", "-", "-", "-", "-", "-",
601 "GPIO_S0_SC[090]", "SIO_I2C6_DATA", "ILB_NMI", "-", "-", "-", "-", "-",
602 "GPIO_S0_SC[091]", "SIO_I2C6_CLK", "SD3_WP", "-", "-", "-", "-", "-",
603 "RESERVED", "GPIO_S0_SC[092]", "-", "-", "-", "-", "-", "-",
604 "RESERVED", "GPIO_S0_SC[093]", "-", "-", "-", "-", "-", "-",
605 "GPIO_S0_SC[094]", "SIO_PWM[0]", "-", "-", "-", "-", "-", "-",
606 "GPIO_S0_SC[095]", "SIO_PWM[1]", "-", "-", "-", "-", "-", "-",
607 "GPIO_S0_SC[096]", "PMC_PLT_CLK[0]", "-", "-", "-", "-", "-", "-",
608 "GPIO_S0_SC[097]", "PMC_PLT_CLK[1]", "-", "-", "-", "-", "-", "-",
609 "GPIO_S0_SC[098]", "PMC_PLT_CLK[2]", "-", "-", "-", "-", "-", "-",
610 "GPIO_S0_SC[099]", "PMC_PLT_CLK[3]", "-", "-", "-", "-", "-", "-",
611 "GPIO_S0_SC[100]", "PMC_PLT_CLK[4]", "-", "-", "-", "-", "-", "-",
612 "GPIO_S0_SC[101]", "PMC_PLT_CLK[5]", "-", "-", "-", "-", "-", "-",
613 };
614
615 static const char *ssus_func_names[GPSSUS_COUNT * 8] = {
616 "GPIO_S5[00]", "RESERVED", "-", "-", "-", "-", "-", "-",
617 "GPIO_S5[01]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[1]#", "-",
618 "GPIO_S5[02]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[2]#", "-",
619 "GPIO_S5[03]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[3]#", "-",
620 "GPIO_S5[04]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
621 "GPIO_S5[05]", "PMC_SUSCLK[1]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
622 "GPIO_S5[06]", "PMC_SUSCLK[2]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
623 "GPIO_S5[07]", "PMC_SUSCLK[3]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
624 "GPIO_S5[08]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
625 "GPIO_S5[09]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
626 "GPIO_S5[10]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "-", "-",
627 "PMC_SUSPWRDNACK", "GPIO_S5[11]", "-", "-", "-", "-", "-", "-",
628 "PMC_SUSCLK[0]", "GPIO_S5[12]", "-", "-", "-", "-", "-", "-",
629 "RESERVED", "GPIO_S5[13]", "-", "-", "-", "-", "-", "-",
630 "RESERVED", "GPIO_S5[14]", "USB_ULPI_RST#","-", "-", "-", "-", "-",
631 "PMC_WAKE_PCIE[0]#", "GPIO_S5[15]", "-", "-", "-", "-", "-", "-",
632 "PMC_PWRBTN#", "GPIO_S5[16]", "-", "-", "-", "-", "-", "-",
633 "RESERVED", "GPIO_S5[17]", "-", "-", "-", "-", "-", "-",
634 "PMC_SUS_STAT#", "GPIO_S5[18]", "-", "-", "-", "-", "-", "-",
635 "USB_OC[0]#", "GPIO_S5[19]", "-", "-", "-", "-", "-", "-",
636 "USB_OC[1]#", "GPIO_S5[20]", "-", "-", "-", "-", "-", "-",
637 "PCU_SPI_CS[1]#", "GPIO_S5[21]", "-", "-", "-", "-", "-", "-",
638 "GPIO_S5[22]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
639 "GPIO_S5[23]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
640 "GPIO_S5[24]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
641 "GPIO_S5[25]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
642 "GPIO_S5[26]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
643 "GPIO_S5[27]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
644 "GPIO_S5[28]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
645 "GPIO_S5[29]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
646 "GPIO_S5[30]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-",
647 "GPIO_S5[31]", "USB_ULPI_CLK", "RESERVED", "RESERVED", "-", "-", "-", "-",
648 "GPIO_S5[32]", "USB_ULPI_DATA[0]", "RESERVED", "RESERVED", "-", "-", "-", "-",
649 "GPIO_S5[33]", "USB_ULPI_DATA[1]", "RESERVED", "RESERVED", "-", "-", "-", "-",
650 "GPIO_S5[34]", "USB_ULPI_DATA[2]", "RESERVED", "RESERVED", "-", "-", "-", "-",
651 "GPIO_S5[35]", "USB_ULPI_DATA[3]", "RESERVED", "RESERVED", "-", "-", "-", "-",
652 "GPIO_S5[36]", "USB_ULPI_DATA[4]", "RESERVED", "RESERVED", "-", "-", "-", "-",
653 "GPIO_S5[37]", "USB_ULPI_DATA[5]", "RESERVED", "RESERVED", "-", "-", "-", "-",
654 "GPIO_S5[38]", "USB_ULPI_DATA[6]", "RESERVED", "RESERVED", "-", "-", "-", "-",
655 "GPIO_S5[39]", "USB_ULPI_DATA[7]", "RESERVED", "RESERVED", "-", "-", "-", "-",
656 "GPIO_S5[40]", "USB_ULPI_DIR", "RESERVED", "RESERVED", "-", "-", "-", "-",
657 "GPIO_S5[41]", "USB_ULPI_NXT", "RESERVED", "RESERVED", "-", "-", "-", "-",
658 "GPIO_S5[42]", "USB_ULPI_STP", "RESERVED", "RESERVED", "-", "-", "-", "-",
659 "GPIO_S5[43]", "USB_ULPI_REFCLK", "RESERVED", "RESERVED", "-", "-", "-", "-",
660 };
661
662 /* GPIO-to-Pad LUTs - Translate the GPIO number to the pad register */
663 static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] =
664 { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
665 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
666 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
667 2, 5, 9 }; /* [24:26] */
668
669 static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =
670 { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
671 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
672 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
673 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
674 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
675 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
676 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
677 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
678 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
679 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
680 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
681 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
682 106, 87, 91, 104, 97, 100 }; /* [96:101] */
683
684 static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] =
685 { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
686 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
687 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
688 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
689 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
690 52, 53, 59, 40 }; /* [40:43] */
691
692 static const struct gpio_bank gpio_banks[] = {
693 {
694 .gpio_count = GPNCORE_COUNT,
695 .gpio_to_pad = gpncore_gpio_to_pad,
696 .pad_base_offset = IO_BASE_OFFSET_GPNCORE,
697 .gpio_name = "NCORE GPIOs",
698 .func_names = ncore_func_names,
699 },
700 {
701 .gpio_count = GPSCORE_COUNT,
702 .gpio_to_pad = gpscore_gpio_to_pad,
703 .pad_base_offset = IO_BASE_OFFSET_GPSCORE,
704 .gpio_name = "SCORE GPIOs (GPIO_S0_SC_XX)",
705 .func_names = score_func_names,
706 },
707 {
708 .gpio_count = GPSSUS_COUNT,
709 .gpio_to_pad = gpssus_gpio_to_pad,
710 .pad_base_offset = IO_BASE_OFFSET_GPSSUS,
711 .gpio_name = "SSUS GPIOs (GPIO_S5)",
712 .func_names = ssus_func_names,
713 },
714 };
715
716 const char *pull_assignment[] = {"None","Up ","Down","Res "};
717 const char *pull_strength[] = {"2k", "10k", "20k", "40k"};
718
719 static int show_baytrail_pad_reg(struct pci_dev *sb){
720
721 uint64_t iobase = (uint64_t)pci_read_long(sb, 0x4c) & 0xffffc000;
722 uint32_t val, bank, gpio, offset, size = 0x3000;
723 volatile uint32_t *reg;
724
725 reg = map_physical(iobase, size);
726
727 if (reg == NULL) {
728 perror("Error mapping IOBASE");
729 return 1;
730 }
731
732 printf("\nIOBASE: 0x%08lx\n",(long int)iobase);
733
734 /* Display function values */
735 for (bank = 0; bank < BANK_COUNT; bank++) {
736 printf("\n========== Bay Trail %s ===========\n\n",
737 gpio_banks[bank].gpio_name);
738
739 printf("Address | GPIO # | reg value | "
740 "Pull Dir & Str | Func #: Func Name |"
741 " I/O | Current Val\n");
742
743 for (gpio=0; gpio < gpio_banks[bank].gpio_count; gpio++) {
744 offset = gpio_banks[bank].pad_base_offset +
745 (16 * gpio_banks[bank].gpio_to_pad[gpio]);
746
747 /* Read Pad Configuration 0 Register */
748 val = *(reg + offset / 4);
749 printf("iobase + 0x%04x | GPIO %3d | ",offset, gpio);
750 printf("0x%08x | ", val);
751 printf("Pull: %4s %3s | ",pull_assignment[(val >> 7) & 3],
752 ((val >> 7) & 3) ?
753 pull_strength[(val >> 9) & 3] :
754 "");
755 printf("Func %d",val & 0x07);
756 if (gpio_banks[bank].func_names != NULL)
757 printf(": %-20s | ", gpio_banks[bank].func_names[(gpio * 8) + (val & 0x07)] );
758
759 /* Read the Pad Value Register */
760 val = *(reg + offset / 4 + 2);
761 printf("%6s%3s%5s | %-4s",
762 (val & 0x02) ? "" : "Output",
763 (val & 0x06) ? "" : " / ",
764 (val & 0x04) ? "" : "Input",
765 (val & 0x01) ? "High" : "Low");
766 printf("\n");
767 }
768 }
769
770 unmap_physical((void *)reg, size);
771 return 0;
772 }
773
774 static uint16_t gpiobase;
775
776 static void print_reg(const io_register_t *const reg)
777 {
778 switch (reg->size) {
779 case 4:
780 printf("gpiobase+0x%04x: 0x%08x (%s)\n",
781 reg->addr, inl(gpiobase+reg->addr), reg->name);
782 break;
783 case 2:
784 printf("gpiobase+0x%04x: 0x%04x (%s)\n",
785 reg->addr, inw(gpiobase+reg->addr), reg->name);
786 break;
787 case 1:
788 printf("gpiobase+0x%04x: 0x%02x (%s)\n",
789 reg->addr, inb(gpiobase+reg->addr), reg->name);
790 break;
791 }
792 }
793
794 static uint32_t get_diff(const io_register_t *const reg, const uint32_t def)
795 {
796 uint32_t gpio_diff = 0;
797 switch (reg->size) {
798 case 4:
799 gpio_diff = def ^ inl(gpiobase+reg->addr);
800 break;
801 case 2:
802 gpio_diff = (uint16_t)def ^ inw(gpiobase+reg->addr);
803 break;
804 case 1:
805 gpio_diff = (uint8_t)def ^ inb(gpiobase+reg->addr);
806 break;
807 }
808 return gpio_diff;
809 }
810
811 static void print_diff(const io_register_t *const reg,
812 const uint32_t def, const uint32_t diff)
813 {
814 switch (reg->size) {
815 case 4:
816 printf("gpiobase+0x%04x: 0x%08x (%s) DEFAULT\n",
817 reg->addr, def, reg->name);
818 printf("gpiobase+0x%04x: 0x%08x (%s) DIFF\n",
819 reg->addr, diff, reg->name);
820 break;
821 case 2:
822 printf("gpiobase+0x%04x: 0x%04x (%s) DEFAULT\n",
823 reg->addr, def, reg->name);
824 printf("gpiobase+0x%04x: 0x%04x (%s) DIFF\n",
825 reg->addr, diff, reg->name);
826 break;
827 case 1:
828 printf("gpiobase+0x%04x: 0x%02x (%s) DEFAULT\n",
829 reg->addr, def, reg->name);
830 printf("gpiobase+0x%04x: 0x%02x (%s) DIFF\n",
831 reg->addr, diff, reg->name);
832 break;
833 }
834 }
835
836 int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
837 {
838 int i, j, size, defaults_size = 0;
839 const io_register_t *gpio_registers;
840 const gpio_default_t *gpio_defaults = NULL;
841 uint32_t gpio_diff;
842
843 switch (sb->device_id) {
844 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
845 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
846 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
847 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
848 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
849 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
850 gpio_registers = lynxpoint_lp_gpio_registers;
851 size = ARRAY_SIZE(lynxpoint_lp_gpio_registers);
852 break;
853 case PCI_DEVICE_ID_INTEL_C8_MOBILE:
854 case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
855 case PCI_DEVICE_ID_INTEL_Z87:
856 case PCI_DEVICE_ID_INTEL_Z85:
857 case PCI_DEVICE_ID_INTEL_HM86:
858 case PCI_DEVICE_ID_INTEL_H87:
859 case PCI_DEVICE_ID_INTEL_HM87:
860 case PCI_DEVICE_ID_INTEL_Q85:
861 case PCI_DEVICE_ID_INTEL_Q87:
862 case PCI_DEVICE_ID_INTEL_QM87:
863 case PCI_DEVICE_ID_INTEL_B85:
864 case PCI_DEVICE_ID_INTEL_C222:
865 case PCI_DEVICE_ID_INTEL_C224:
866 case PCI_DEVICE_ID_INTEL_C226:
867 case PCI_DEVICE_ID_INTEL_H81:
868 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
869 gpio_registers = pch_gpio_registers;
870 size = ARRAY_SIZE(pch_gpio_registers);
871 break;
872 case PCI_DEVICE_ID_INTEL_3400:
873 case PCI_DEVICE_ID_INTEL_3420:
874 case PCI_DEVICE_ID_INTEL_3450:
875 case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
876 case PCI_DEVICE_ID_INTEL_B55_A:
877 case PCI_DEVICE_ID_INTEL_B55_B:
878 case PCI_DEVICE_ID_INTEL_H55:
879 case PCI_DEVICE_ID_INTEL_H57:
880 case PCI_DEVICE_ID_INTEL_P55:
881 case PCI_DEVICE_ID_INTEL_Q57:
882 gpiobase = pci_read_word(sb, 0x48) & 0xff80;
883 gpio_registers = pch_gpio_registers;
884 size = ARRAY_SIZE(pch_gpio_registers);
885 gpio_defaults = ip_pch_desktop_defaults;
886 defaults_size = ARRAY_SIZE(ip_pch_desktop_defaults);
887 break;
888 case PCI_DEVICE_ID_INTEL_3400_MOBILE:
889 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
890 case PCI_DEVICE_ID_INTEL_HM55:
891 case PCI_DEVICE_ID_INTEL_HM57:
892 case PCI_DEVICE_ID_INTEL_PM55:
893 case PCI_DEVICE_ID_INTEL_QM57:
894 case PCI_DEVICE_ID_INTEL_QS57:
895 gpiobase = pci_read_word(sb, 0x48) & 0xff80;
896 gpio_registers = pch_gpio_registers;
897 size = ARRAY_SIZE(pch_gpio_registers);
898 gpio_defaults = ip_pch_mobile_defaults;
899 defaults_size = ARRAY_SIZE(ip_pch_mobile_defaults);
900 break;
901 case PCI_DEVICE_ID_INTEL_Z68:
902 case PCI_DEVICE_ID_INTEL_P67:
903 case PCI_DEVICE_ID_INTEL_H67:
904 case PCI_DEVICE_ID_INTEL_Q65:
905 case PCI_DEVICE_ID_INTEL_QS67:
906 case PCI_DEVICE_ID_INTEL_Q67:
907 case PCI_DEVICE_ID_INTEL_B65:
908 case PCI_DEVICE_ID_INTEL_C202:
909 case PCI_DEVICE_ID_INTEL_C204:
910 case PCI_DEVICE_ID_INTEL_C206:
911 case PCI_DEVICE_ID_INTEL_H61:
912 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
913 gpio_registers = pch_gpio_registers;
914 size = ARRAY_SIZE(pch_gpio_registers);
915 gpio_defaults = cp_pch_desktop_defaults;
916 defaults_size = ARRAY_SIZE(cp_pch_desktop_defaults);
917 break;
918 case PCI_DEVICE_ID_INTEL_UM67:
919 case PCI_DEVICE_ID_INTEL_HM65:
920 case PCI_DEVICE_ID_INTEL_HM67:
921 case PCI_DEVICE_ID_INTEL_QM67:
922 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
923 gpio_registers = pch_gpio_registers;
924 size = ARRAY_SIZE(pch_gpio_registers);
925 gpio_defaults = cp_pch_mobile_defaults;
926 defaults_size = ARRAY_SIZE(cp_pch_mobile_defaults);
927 break;
928 case PCI_DEVICE_ID_INTEL_Z77:
929 case PCI_DEVICE_ID_INTEL_Z75:
930 case PCI_DEVICE_ID_INTEL_Q77:
931 case PCI_DEVICE_ID_INTEL_Q75:
932 case PCI_DEVICE_ID_INTEL_B75:
933 case PCI_DEVICE_ID_INTEL_H77:
934 case PCI_DEVICE_ID_INTEL_C216:
935 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
936 gpio_registers = pch_gpio_registers;
937 size = ARRAY_SIZE(pch_gpio_registers);
938 gpio_defaults = pp_pch_desktop_defaults;
939 defaults_size = ARRAY_SIZE(pp_pch_desktop_defaults);
940 break;
941 case PCI_DEVICE_ID_INTEL_QM77:
942 case PCI_DEVICE_ID_INTEL_QS77:
943 case PCI_DEVICE_ID_INTEL_HM77:
944 case PCI_DEVICE_ID_INTEL_UM77:
945 case PCI_DEVICE_ID_INTEL_HM76:
946 case PCI_DEVICE_ID_INTEL_HM75:
947 case PCI_DEVICE_ID_INTEL_HM70:
948 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
949 gpio_registers = pch_gpio_registers;
950 size = ARRAY_SIZE(pch_gpio_registers);
951 gpio_defaults = pp_pch_mobile_defaults;
952 defaults_size = ARRAY_SIZE(pp_pch_mobile_defaults);
953 break;
954 case PCI_DEVICE_ID_INTEL_ICH10:
955 case PCI_DEVICE_ID_INTEL_ICH10R:
956 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
957 gpio_registers = ich10_gpio_registers;
958 size = ARRAY_SIZE(ich10_gpio_registers);
959 break;
960 case PCI_DEVICE_ID_INTEL_ICH9DH:
961 case PCI_DEVICE_ID_INTEL_ICH9DO:
962 case PCI_DEVICE_ID_INTEL_ICH9R:
963 case PCI_DEVICE_ID_INTEL_ICH9:
964 case PCI_DEVICE_ID_INTEL_ICH9M:
965 case PCI_DEVICE_ID_INTEL_ICH9ME:
966 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
967 gpio_registers = ich9_gpio_registers;
968 size = ARRAY_SIZE(ich9_gpio_registers);
969 break;
970 case PCI_DEVICE_ID_INTEL_ICH8:
971 case PCI_DEVICE_ID_INTEL_ICH8M:
972 case PCI_DEVICE_ID_INTEL_ICH8ME:
973 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
974 gpio_registers = ich8_gpio_registers;
975 size = ARRAY_SIZE(ich8_gpio_registers);
976 break;
977 case PCI_DEVICE_ID_INTEL_ICH7:
978 case PCI_DEVICE_ID_INTEL_ICH7M:
979 case PCI_DEVICE_ID_INTEL_ICH7DH:
980 case PCI_DEVICE_ID_INTEL_ICH7MDH:
981 case PCI_DEVICE_ID_INTEL_NM10:
982 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
983 gpio_registers = ich7_gpio_registers;
984 size = ARRAY_SIZE(ich7_gpio_registers);
985 break;
986 case PCI_DEVICE_ID_INTEL_ICH6:
987 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
988 gpio_registers = ich6_gpio_registers;
989 size = ARRAY_SIZE(ich6_gpio_registers);
990 break;
991 case PCI_DEVICE_ID_INTEL_ICH5:
992 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
993 gpio_registers = ich5_gpio_registers;
994 size = ARRAY_SIZE(ich5_gpio_registers);
995 break;
996 case PCI_DEVICE_ID_INTEL_ICH4:
997 case PCI_DEVICE_ID_INTEL_ICH4M:
998 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
999 gpio_registers = ich4_gpio_registers;
1000 size = ARRAY_SIZE(ich4_gpio_registers);
1001 break;
1002 case PCI_DEVICE_ID_INTEL_ICH2:
1003 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
1004 gpio_registers = ich2_gpio_registers;
1005 size = ARRAY_SIZE(ich2_gpio_registers);
1006 break;
1007 case PCI_DEVICE_ID_INTEL_ICH:
1008 case PCI_DEVICE_ID_INTEL_ICH0:
1009 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
1010 gpio_registers = ich0_gpio_registers;
1011 size = ARRAY_SIZE(ich0_gpio_registers);
1012 break;
1013
1014 case PCI_DEVICE_ID_INTEL_I63XX:
1015 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
1016 gpio_registers = i631x_gpio_registers;
1017 size = ARRAY_SIZE(i631x_gpio_registers);
1018 break;
1019 case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
1020 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
1021 gpio_registers = baytrail_score_ssus_gpio_registers;
1022 size = ARRAY_SIZE(baytrail_score_ssus_gpio_registers);
1023 break;
1024 case PCI_DEVICE_ID_INTEL_H110:
1025 case PCI_DEVICE_ID_INTEL_H170:
1026 case PCI_DEVICE_ID_INTEL_Z170:
1027 case PCI_DEVICE_ID_INTEL_Q170:
1028 case PCI_DEVICE_ID_INTEL_Q150:
1029 case PCI_DEVICE_ID_INTEL_B150:
1030 case PCI_DEVICE_ID_INTEL_C236:
1031 case PCI_DEVICE_ID_INTEL_C232:
1032 case PCI_DEVICE_ID_INTEL_QM170:
1033 case PCI_DEVICE_ID_INTEL_HM170:
1034 case PCI_DEVICE_ID_INTEL_CM236:
1035 case PCI_DEVICE_ID_INTEL_APL_LPC:
1036 case PCI_DEVICE_ID_INTEL_DNV_LPC:
1037 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
1038 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
1039 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
1040 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
1041 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
1042 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
1043 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
1044 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
1045 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
1046 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
1047 case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
1048 case PCI_DEVICE_ID_INTEL_C621:
1049 case PCI_DEVICE_ID_INTEL_C622:
1050 case PCI_DEVICE_ID_INTEL_C624:
1051 case PCI_DEVICE_ID_INTEL_C625:
1052 case PCI_DEVICE_ID_INTEL_C626:
1053 case PCI_DEVICE_ID_INTEL_C627:
1054 case PCI_DEVICE_ID_INTEL_C628:
1055 case PCI_DEVICE_ID_INTEL_C629:
1056 case PCI_DEVICE_ID_INTEL_C624_SUPER:
1057 case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
1058 case PCI_DEVICE_ID_INTEL_C621_SUPER:
1059 case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
1060 case PCI_DEVICE_ID_INTEL_C628_SUPER:
1061 case PCI_DEVICE_ID_INTEL_H310:
1062 case PCI_DEVICE_ID_INTEL_H370:
1063 case PCI_DEVICE_ID_INTEL_Z390:
1064 case PCI_DEVICE_ID_INTEL_Q370:
1065 case PCI_DEVICE_ID_INTEL_B360:
1066 case PCI_DEVICE_ID_INTEL_C246:
1067 case PCI_DEVICE_ID_INTEL_C242:
1068 case PCI_DEVICE_ID_INTEL_QM370:
1069 case PCI_DEVICE_ID_INTEL_HM370:
1070 case PCI_DEVICE_ID_INTEL_CM246:
1071 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
1072 print_gpio_groups(sb);
1073 return 0;
1074 case PCI_DEVICE_ID_INTEL_82371XX:
1075 printf("This southbridge has GPIOs in the PM unit.\n");
1076 return 1;
1077 default:
1078 printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
1079 return 1;
1080 }
1081
1082 if (show_diffs && !show_all)
1083 printf("\n========== GPIO DIFFS ===========\n\n");
1084 else
1085 printf("\n============= GPIOS =============\n\n");
1086
1087 printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
1088
1089 j = 0;
1090 for (i = 0; i < size; i++) {
1091 if (show_all)
1092 print_reg(&gpio_registers[i]);
1093
1094 if (show_diffs &&
1095 (j < defaults_size) &&
1096 (gpio_defaults[j].addr == gpio_registers[i].addr)) {
1097 gpio_diff = get_diff(&gpio_registers[i],
1098 gpio_defaults[j].def);
1099 if (gpio_diff) {
1100 if (!show_all)
1101 print_reg(&gpio_registers[i]);
1102 print_diff(&gpio_registers[i],
1103 gpio_defaults[j].def, gpio_diff);
1104 if (!show_all)
1105 printf("\n");
1106 }
1107 j++;
1108 }
1109 }
1110
1111 switch (sb->device_id) {
1112 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
1113 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
1114 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
1115 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
1116 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
1117 for (i = 0; i < 95; i++) {
1118 io_register_t tmp_gpio;
1119 char gpio_name[32];
1120 uint16_t tmp_addr = 0x100 + (4 * i * 2);
1121
1122 snprintf(gpio_name, sizeof(gpio_name), "GP%dCONFIGA", i);
1123 tmp_gpio.addr = tmp_addr;
1124 tmp_gpio.name = gpio_name;
1125 tmp_gpio.size = 4;
1126
1127 if (show_all)
1128 print_reg(&tmp_gpio);
1129
1130 snprintf(gpio_name, 32, "GP%dCONFIGB", i);
1131 tmp_gpio.addr = tmp_addr + 4;
1132 tmp_gpio.name = gpio_name;
1133 tmp_gpio.size = 4;
1134
1135 if (show_all)
1136 print_reg(&tmp_gpio);
1137 }
1138 break;
1139 case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
1140 show_baytrail_pad_reg(sb);
1141 break;
1142 default:
1143 break;
1144 }
1145
1146 return 0;
1147 }
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