mb/google/brya/var/agah: Update FBVDD power-down delay
[coreboot.git] / src / device / pcix_device.c
blob8bf5225703263efd23d87fea66648abf1c194961
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ops.h>
7 #include <device/pcix.h>
9 static void pcix_tune_dev(struct device *dev)
11 u32 status;
12 u16 orig_cmd, cmd;
13 unsigned int cap, max_read, max_tran;
15 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
16 return;
18 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
19 if (!cap)
20 return;
22 printk(BIOS_DEBUG, "%s PCI-X tuning\n", dev_path(dev));
24 status = pci_read_config32(dev, cap + PCI_X_STATUS);
25 orig_cmd = cmd = pci_read_config16(dev, cap + PCI_X_CMD);
27 max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
28 max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
29 if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
30 cmd &= ~PCI_X_CMD_MAX_READ;
31 cmd |= max_read << 2;
33 if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
34 cmd &= ~PCI_X_CMD_MAX_SPLIT;
35 cmd |= max_tran << 4;
38 /* Don't attempt to handle PCI-X errors. */
39 cmd &= ~PCI_X_CMD_DPERR_E;
41 /* Enable relaxed ordering. */
42 cmd |= PCI_X_CMD_ERO;
44 if (orig_cmd != cmd)
45 pci_write_config16(dev, cap + PCI_X_CMD, cmd);
48 static void pcix_tune_bus(struct bus *bus)
50 struct device *child;
52 for (child = bus->children; child; child = child->sibling)
53 pcix_tune_dev(child);
56 const char *pcix_speed(u16 sstatus)
58 static const char conventional[] = "Conventional PCI";
59 static const char pcix_66mhz[] = "66MHz PCI-X";
60 static const char pcix_100mhz[] = "100MHz PCI-X";
61 static const char pcix_133mhz[] = "133MHz PCI-X";
62 static const char pcix_266mhz[] = "266MHz PCI-X";
63 static const char pcix_533mhz[] = "533MHZ PCI-X";
64 static const char unknown[] = "Unknown";
65 const char *result;
67 result = unknown;
69 switch (PCI_X_SSTATUS_MFREQ(sstatus)) {
70 case PCI_X_SSTATUS_CONVENTIONAL_PCI:
71 result = conventional;
72 break;
73 case PCI_X_SSTATUS_MODE1_66MHZ:
74 result = pcix_66mhz;
75 break;
76 case PCI_X_SSTATUS_MODE1_100MHZ:
77 result = pcix_100mhz;
78 break;
79 case PCI_X_SSTATUS_MODE1_133MHZ:
80 result = pcix_133mhz;
81 break;
82 case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ:
83 case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ:
84 case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ:
85 result = pcix_266mhz;
86 break;
87 case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ:
88 case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ:
89 case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ:
90 result = pcix_533mhz;
91 break;
94 return result;
97 void pcix_scan_bridge(struct device *dev)
99 unsigned int pos;
100 u16 sstatus;
102 do_pci_scan_bridge(dev, pci_scan_bus);
104 /* Find the PCI-X capability. */
105 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
106 sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
108 if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI)
109 pcix_tune_bus(dev->link_list);
111 /* Print the PCI-X bus speed. */
112 printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary,
113 pcix_speed(sstatus));
116 /** Default device operations for PCI-X bridges */
117 static struct pci_operations pcix_bus_ops_pci = {
118 .set_subsystem = 0,
121 struct device_operations default_pcix_ops_bus = {
122 .read_resources = pci_bus_read_resources,
123 .set_resources = pci_dev_set_resources,
124 .enable_resources = pci_bus_enable_resources,
125 .scan_bus = pcix_scan_bridge,
126 .reset_bus = pci_bus_reset,
127 .ops_pci = &pcix_bus_ops_pci,