1 ## SPDX-License-Identifier: GPL-2.0-only
3 if SOC_INTEL_SKYLAKE_SP
5 config MAINBOARD_USES_FSP2_0
10 string "Location of FSP headers"
11 depends on MAINBOARD_USES_FSP2_0
12 default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp"
22 # For 2S config, the number of cpus could be as high as
23 # 2 threads * 20 cores * 2 sockets
28 config PCR_BASE_ADDRESS
32 This option allows you to select MMIO Base Address of sideband bus.
34 config DCACHE_RAM_BASE
38 config DCACHE_RAM_SIZE
42 config DCACHE_BSP_STACK_SIZE
46 config CPU_MICROCODE_CBFS_LOC
50 config CPU_MICROCODE_CBFS_LEN
58 config IED_REGION_SIZE