src/soc/intel/skylake/Kconfig

   1 config SOC_INTEL_COMMON_SKYLAKE_BASE
   2         bool
   3
   4 config SOC_INTEL_SKYLAKE
   5         bool
   6         select SOC_INTEL_COMMON_SKYLAKE_BASE
   7         help
   8           Intel Skylake support
   9
  10 config SOC_INTEL_KABYLAKE
  11         bool
  12         select SOC_INTEL_COMMON_SKYLAKE_BASE
  13         help
  14           Intel Kabylake support
  15
  16 if SOC_INTEL_COMMON_SKYLAKE_BASE
  17
  18 config CPU_SPECIFIC_OPTIONS
  19         def_bool y
  20         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
  21         select ACPI_NHLT
  22         select ARCH_ALL_STAGES_X86_32
  23         select BOOT_DEVICE_SUPPORTS_WRITES
  24         select CACHE_MRC_SETTINGS
  25         select CPU_INTEL_COMMON
  26         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  27         select CPU_SUPPORTS_PM_TIMER_EMULATION
  28         select FSP_M_XIP
  29         select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
  30         select GENERIC_GPIO_LIB
  31         select HAVE_FSP_GOP
  32         select HAVE_FSP_LOGO_SUPPORT
  33         select HAVE_INTEL_FSP_REPO
  34         select INTEL_CAR_NEM_ENHANCED
  35         select INTEL_DESCRIPTOR_MODE_CAPABLE
  36         select HAVE_SMI_HANDLER
  37         select INTEL_DESCRIPTOR_MODE_CAPABLE
  38         select INTEL_GMA_ACPI
  39         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  40         select IOAPIC
  41         select MRC_SETTINGS_PROTECT
  42         select PARALLEL_MP
  43         select PARALLEL_MP_AP_WORK
  44         select PLATFORM_USES_FSP2_0
  45         select PM_ACPI_TIMER_OPTIONAL
  46         select PMC_GLOBAL_RESET_ENABLE_LOCK
  47         select REG_SCRIPT
  48         select SA_ENABLE_DPR
  49         select SOC_INTEL_COMMON
  50         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  51         select SOC_INTEL_COMMON_BLOCK
  52         select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
  53         select SOC_INTEL_COMMON_BLOCK_CAR
  54         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  55         select SOC_INTEL_COMMON_BLOCK_CPU
  56         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  57         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  58         select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
  59         select SOC_INTEL_COMMON_BLOCK_GSPI
  60         select SOC_INTEL_COMMON_BLOCK_HDA
  61         select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
  62         select SOC_INTEL_COMMON_BLOCK_SA
  63         select SOC_INTEL_COMMON_BLOCK_SCS
  64         select SOC_INTEL_COMMON_BLOCK_SGX
  65         select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY
  66         select SOC_INTEL_COMMON_BLOCK_SMM
  67         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  68         select SOC_INTEL_COMMON_BLOCK_THERMAL
  69         select SOC_INTEL_COMMON_BLOCK_UART
  70         select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
  71         select SOC_INTEL_COMMON_FSP_RESET
  72         select SOC_INTEL_COMMON_PCH_BASE
  73         select SOC_INTEL_COMMON_NHLT
  74         select SOC_INTEL_COMMON_RESET
  75         select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
  76         select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
  77         select SSE2
  78         select SUPPORT_CPU_UCODE_IN_CBFS
  79         select TSC_MONOTONIC_TIMER
  80         select TSC_SYNC_MFENCE
  81         select UDELAY_TSC
  82         select UDK_2015_BINDING
  83
  84 config MAX_CPUS
  85         int
  86         default 8
  87
  88 config FSP_HYPERTHREADING
  89         bool "Enable Hyper-Threading"
  90         default y
  91
  92 config CPU_INTEL_NUM_FIT_ENTRIES
  93         int
  94         default 10
  95
  96 config CHROMEOS
  97         select CHROMEOS_RAMOOPS_DYNAMIC
  98
  99 config VBOOT
 100         select VBOOT_SEPARATE_VERSTAGE
 101         select VBOOT_MUST_REQUEST_DISPLAY
 102         select VBOOT_STARTS_IN_BOOTBLOCK
 103         select VBOOT_VBNV_CMOS
 104         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 105
 106 config CBFS_SIZE
 107         hex
 108         default 0x200000
 109
 110 config DCACHE_RAM_BASE
 111         hex
 112         default 0xfef00000
 113
 114 config DCACHE_RAM_SIZE
 115         hex
 116         default 0x40000
 117         help
 118           The size of the cache-as-ram region required during bootblock
 119           and/or romstage.
 120
 121 config DCACHE_BSP_STACK_SIZE
 122         hex
 123         default 0x4000
 124         help
 125           The amount of anticipated stack usage in CAR by bootblock and
 126           other stages.
 127
 128 config EXCLUDE_NATIVE_SD_INTERFACE
 129         bool
 130         default n
 131         help
 132           If you set this option to n, will not use native SD controller.
 133
 134 config HEAP_SIZE
 135         hex
 136         default 0x80000
 137
 138 config IED_REGION_SIZE
 139         hex
 140         default 0x400000
 141
 142 config PCR_BASE_ADDRESS
 143         hex
 144         default 0xfd000000
 145         help
 146           This option allows you to select MMIO Base Address of sideband bus.
 147
 148 config SMM_RESERVED_SIZE
 149         hex
 150         default 0x200000
 151
 152 config SMM_TSEG_SIZE
 153         hex
 154         default 0x800000
 155
 156 config VGA_BIOS_ID
 157         string
 158         default "8086,0406"
 159
 160 config SKYLAKE_SOC_PCH_H
 161         bool
 162         default n
 163         help
 164           Choose this option if you have a PCH-H chipset.
 165
 166 config NHLT_DMIC_1CH
 167         bool
 168         default n
 169         help
 170           Include DSP firmware settings for 1 channel DMIC array.
 171
 172 config NHLT_DMIC_2CH
 173         bool
 174         default n
 175         help
 176           Include DSP firmware settings for 2 channel DMIC array.
 177
 178 config NHLT_DMIC_4CH
 179         bool
 180         default n
 181         help
 182           Include DSP firmware settings for 4 channel DMIC array.
 183
 184 config NHLT_NAU88L25
 185         bool
 186         default n
 187         help
 188           Include DSP firmware settings for nau88l25 headset codec.
 189
 190 config NHLT_MAX98357
 191         bool
 192         default n
 193         help
 194           Include DSP firmware settings for max98357 amplifier.
 195
 196 config NHLT_MAX98373
 197         bool
 198         default n
 199         help
 200           Include DSP firmware settings for max98373 amplifier.
 201
 202 config NHLT_SSM4567
 203         bool
 204         default n
 205         help
 206           Include DSP firmware settings for ssm4567 smart amplifier.
 207
 208 config NHLT_RT5514
 209         bool
 210         default n
 211         help
 212           Include DSP firmware settings for rt5514 DSP.
 213
 214 config NHLT_RT5663
 215         bool
 216         default n
 217         help
 218           Include DSP firmware settings for rt5663 headset codec.
 219
 220 config NHLT_MAX98927
 221         bool
 222         default n
 223         help
 224           Include DSP firmware settings for max98927 amplifier.
 225
 226 config NHLT_DA7219
 227         bool
 228         default n
 229         help
 230           Include DSP firmware settings for DA7219 headset codec.
 231
 232 config FSP_HEADER_PATH
 233         # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
 234         # SkylakeFsp is FSP 1.1 and therefore incompatible.
 235         default "3rdparty/fsp/KabylakeFspBinPkg/Include/"
 236
 237 config FSP_FD_PATH
 238         default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
 239
 240 config MAX_ROOT_PORTS
 241         int
 242         default 24
 243
 244 config NO_FADT_8042
 245         bool
 246         default n
 247         help
 248           Choose this option if you want to disable 8042 Keyboard
 249
 250 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 251         int
 252         default 120
 253
 254 config CPU_XTAL_HZ
 255         default 24000000
 256
 257 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 258         int
 259         default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 260
 261 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 262         int
 263         default 2
 264
 265 config SOC_INTEL_I2C_DEV_MAX
 266         int
 267         default 6
 268
 269 config CPU_BCLK_MHZ
 270         int
 271         default 100
 272
 273 config CONSOLE_UART_BASE_ADDRESS
 274         hex
 275         default 0xfe030000
 276         depends on INTEL_LPSS_UART_FOR_CONSOLE
 277
 278 # Clock divider parameters for 115200 baud rate
 279 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 280         hex
 281         default 0x30
 282
 283 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 284         hex
 285         default 0xc35
 286
 287 config CHIPSET_DEVICETREE
 288         string
 289         default "soc/intel/skylake/chipset.cb"
 290
 291 config IFD_CHIPSET
 292         string
 293         default "sklkbl"
 294
 295 config INTEL_TXT_BIOSACM_ALIGNMENT
 296         hex
 297         default 0x40000 # 256KB
 298
 299 config MAINBOARD_SUPPORTS_SKYLAKE_CPU
 300         bool "Board can contain Skylake CPU"
 301         default y
 302
 303 if SKYLAKE_SOC_PCH_H
 304
 305 config MAINBOARD_SUPPORTS_KABYLAKE_CPU
 306         bool "Board can contain Kaby Lake CPU"
 307         default y if SOC_INTEL_KABYLAKE
 308
 309 endif
 310
 311 if !SKYLAKE_SOC_PCH_H
 312
 313 config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
 314         bool "Board can contain Kaby Lake DUAL core"
 315         default y
 316
 317 config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
 318         bool "Board can contain Kaby Lake QUAD core"
 319         default y
 320
 321 endif
 322
 323 endif