src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h

   1 /** @file
   2
   3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
   4
   5 Redistribution and use in source and binary forms, with or without modification,
   6 are permitted provided that the following conditions are met:
   7
   8 * Redistributions of source code must retain the above copyright notice, this
   9   list of conditions and the following disclaimer.
  10 * Redistributions in binary form must reproduce the above copyright notice, this
  11   list of conditions and the following disclaimer in the documentation and/or
  12   other materials provided with the distribution.
  13 * Neither the name of Intel Corporation nor the names of its contributors may
  14   be used to endorse or promote products derived from this software without
  15   specific prior written permission.
  16
  17   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  18   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  21   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27   THE POSSIBILITY OF SUCH DAMAGE.
  28
  29   This file is automatically generated. Please do NOT modify !!!
  30
  31 **/
  32
  33 #ifndef __FSPSUPD_H__
  34 #define __FSPSUPD_H__
  35
  36 #include <FspUpd.h>
  37
  38 #pragma pack(push, 1)
  39
  40
  41 /** Fsp S Configuration
  42 **/
  43 typedef struct {
  44
  45 /** Offset 0x0020 - ActiveProcessorCores
  46   Number of active cores. 0:Disable(Default), 1:Enable.
  47 **/
  48   UINT8                       ActiveProcessorCores;
  49
  50 /** Offset 0x0021 - Disable Core1
  51   Disable/Enable Core1. 0:Disable, 1:Enable(Default).
  52   $EN_DIS
  53 **/
  54   UINT8                       DisableCore1;
  55
  56 /** Offset 0x0022 - Disable Core2
  57   Disable/Enable Core2. 0:Disable, 1:Enable(Default).
  58   $EN_DIS
  59 **/
  60   UINT8                       DisableCore2;
  61
  62 /** Offset 0x0023 - Disable Core3
  63   Disable/Enable Core3. 0:Disable, 1:Enable(Default).
  64   $EN_DIS
  65 **/
  66   UINT8                       DisableCore3;
  67
  68 /** Offset 0x0024 - VMX Enable
  69   Enable or Disable VMX. 0:Disable, 1:Enable(Default).
  70   $EN_DIS
  71 **/
  72   UINT8                       VmxEnable;
  73
  74 /** Offset 0x0025 - Depricated UPD
  75    Depricated UPD
  76 **/
  77   UINT8                       Reserved;
  78
  79 /** Offset 0x0026 - Enable Processor Trace
  80   Enable or Disable Processor Trace feature.  0:Disable(Default), 1:Enable.
  81   $EN_DIS
  82 **/
  83   UINT8                       ProcessorTraceEnable;
  84
  85 /** Offset 0x0027 - Eist
  86   Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).
  87   $EN_DIS
  88 **/
  89   UINT8                       Eist;
  90
  91 /** Offset 0x0028 - Boot PState
  92   Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.
  93 **/
  94   UINT8                       BootPState;
  95
  96 /** Offset 0x0029 - CPU power states (C-states)
  97   Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).
  98   $EN_DIS
  99 **/
 100   UINT8                       EnableCx;
 101
 102 /** Offset 0x002A - Enhanced C-states
 103   Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.
 104   $EN_DIS
 105 **/
 106   UINT8                       C1e;
 107
 108 /** Offset 0x002B - Bi-Directional PROCHOT#
 109   Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).
 110   $EN_DIS
 111 **/
 112   UINT8                       BiProcHot;
 113
 114 /** Offset 0x002C - Max Pkg Cstate
 115   Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,
 116   6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.
 117 **/
 118   UINT8                       PkgCStateLimit;
 119
 120 /** Offset 0x002D - C-State auto-demotion
 121   C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7
 122   Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion
 123   to C1 and C3.
 124 **/
 125   UINT8                       CStateAutoDemotion;
 126
 127 /** Offset 0x002E - C-State un-demotion
 128   C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,
 129   2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.
 130 **/
 131   UINT8                       CStateUnDemotion;
 132
 133 /** Offset 0x002F - Max Core C-State
 134   Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).
 135 **/
 136   UINT8                       MaxCoreCState;
 137
 138 /** Offset 0x0030 - Package C-State Demotion
 139   Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.
 140   $EN_DIS
 141 **/
 142   UINT8                       PkgCStateDemotion;
 143
 144 /** Offset 0x0031 - Package C-State Un-demotion
 145   Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.
 146   $EN_DIS
 147 **/
 148   UINT8                       PkgCStateUnDemotion;
 149
 150 /** Offset 0x0032 - Turbo Mode
 151   Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).
 152   $EN_DIS
 153 **/
 154   UINT8                       TurboMode;
 155
 156 /** Offset 0x0033 - SC HDA Verb Table Entry Number
 157   Number of Entries in Verb Table. 0(Default).
 158 **/
 159   UINT8                       HdaVerbTableEntryNum;
 160
 161 /** Offset 0x0034 - SC HDA Verb Table Pointer
 162   Pointer to Array of pointers to Verb Table. 0x00000000(Default).
 163 **/
 164   UINT32                      HdaVerbTablePtr;
 165
 166 /** Offset 0x0038 - Enable/Disable P2SB device hidden.
 167   Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.
 168   $EN_DIS
 169 **/
 170   UINT8                       P2sbUnhide;
 171
 172 /** Offset 0x0039 - IPU Enable/Disable
 173   Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
 174   $EN_DIS
 175 **/
 176   UINT8                       IpuEnReserved;
 177
 178 /** Offset 0x003A - IMGU ACPI mode selection
 179   0:Auto, 1:IGFX Child device(Default), 2:ACPI device.
 180   0:Disable, 1:IGFX Child device, 2:ACPI device
 181 **/
 182   UINT8                       IpuAcpiModeReserved;
 183
 184 /** Offset 0x003B - Enable ForceWake
 185   Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.
 186   $EN_DIS
 187 **/
 188   UINT8                       ForceWake;
 189
 190 /** Offset 0x003C - GttMmAdr
 191   GttMmAdr structure for initialization. 0xBF000000(Default).
 192 **/
 193   UINT32                      GttMmAdr;
 194
 195 /** Offset 0x0040 - GmAdr
 196   GmAdr structure for initialization. 0xA0000000(Default).
 197 **/
 198   UINT32                      GmAdr;
 199
 200 /** Offset 0x0044 - Enable PavpLock
 201   Enable/disable PavpLock. 0:Disable(Default), 1:Enable.
 202   $EN_DIS
 203 **/
 204   UINT8                       PavpLock;
 205
 206 /** Offset 0x0045 - Enable GraphicsFreqModify
 207   Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.
 208   $EN_DIS
 209 **/
 210   UINT8                       GraphicsFreqModify;
 211
 212 /** Offset 0x0046 - Enable GraphicsFreqReq
 213   Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.
 214   $EN_DIS
 215 **/
 216   UINT8                       GraphicsFreqReq;
 217
 218 /** Offset 0x0047 - Enable GraphicsVideoFreq
 219   Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.
 220   $EN_DIS
 221 **/
 222   UINT8                       GraphicsVideoFreq;
 223
 224 /** Offset 0x0048 - Enable PmLock
 225   Enable/disable PmLock. 0:Disable(Default), 1:Enable.
 226   $EN_DIS
 227 **/
 228   UINT8                       PmLock;
 229
 230 /** Offset 0x0049 - Enable DopClockGating
 231   Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.
 232   $EN_DIS
 233 **/
 234   UINT8                       DopClockGating;
 235
 236 /** Offset 0x004A - Enable UnsolicitedAttackOverride
 237   Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.
 238   $EN_DIS
 239 **/
 240   UINT8                       UnsolicitedAttackOverride;
 241
 242 /** Offset 0x004B - Enable WOPCMSupport
 243   Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.
 244   $EN_DIS
 245 **/
 246   UINT8                       WOPCMSupport;
 247
 248 /** Offset 0x004C - Enable WOPCMSize
 249   Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.
 250   $EN_DIS
 251 **/
 252   UINT8                       WOPCMSize;
 253
 254 /** Offset 0x004D - Enable PowerGating
 255   Enable/disable PowerGating. 0:Disable(Default), 1:Enable.
 256   $EN_DIS
 257 **/
 258   UINT8                       PowerGating;
 259
 260 /** Offset 0x004E - Enable UnitLevelClockGating
 261   Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.
 262   $EN_DIS
 263 **/
 264   UINT8                       UnitLevelClockGating;
 265
 266 /** Offset 0x004F - Enable FastBoot
 267   Enable/disable FastBoot. 0:Disable(Default), 1:Enable.
 268   $EN_DIS
 269 **/
 270   UINT8                       FastBoot;
 271
 272 /** Offset 0x0050 - Enable DynSR
 273   Enable/disable DynSR. 0:Disable(Default), 1:Enable.
 274   $EN_DIS
 275 **/
 276   UINT8                       DynSR;
 277
 278 /** Offset 0x0051 - Enable SaIpuEnable
 279   Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.
 280   $EN_DIS
 281 **/
 282   UINT8                       SaIpuEnableReserved;
 283
 284 /** Offset 0x0052 - GT PM Support
 285   Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).
 286   $EN_DIS
 287 **/
 288   UINT8                       PmSupport;
 289
 290 /** Offset 0x0053 - RC6(Render Standby)
 291   Enable/Disable render standby support. 0:Disable, 1:Enable(Default).
 292   $EN_DIS
 293 **/
 294   UINT8                       EnableRenderStandby;
 295
 296 /** Offset 0x0054 - BMP Logo Data Size
 297   BMP logo data buffer size. 0x00000000(Default).
 298 **/
 299   UINT32                      LogoSize;
 300
 301 /** Offset 0x0058 - BMP Logo Data Pointer
 302   BMP logo data pointer to a BMP format buffer. 0x00000000(Default).
 303 **/
 304   UINT32                      LogoPtr;
 305
 306 /** Offset 0x005C - Graphics Configuration Data Pointer
 307   Graphics configuration data used for initialization. 0x00000000(Default).
 308 **/
 309   UINT32                      GraphicsConfigPtr;
 310
 311 /** Offset 0x0060 - PAVP Enable
 312   Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).
 313   $EN_DIS
 314 **/
 315   UINT8                       PavpEnable;
 316
 317 /** Offset 0x0061 - PAVP PR3
 318   Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).
 319   $EN_DIS
 320 **/
 321   UINT8                       PavpPr3;
 322
 323 /** Offset 0x0062 - CdClock Frequency selection
 324   0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).
 325   0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
 326 **/
 327   UINT8                       CdClock;
 328
 329 /** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit
 330   Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).
 331   $EN_DIS
 332 **/
 333   UINT8                       PeiGraphicsPeimInit;
 334
 335 /** Offset 0x0064 - Write Protection Support
 336   Enable/disable Write Protection. 0:Disable, 1:Enable(Default).
 337 **/
 338   UINT8                       WriteProtectionEnable[5];
 339
 340 /** Offset 0x0069 - Read Protection Support
 341   Enable/disable Read Protection. 0:Disable, 1:Enable(Default).
 342 **/
 343   UINT8                       ReadProtectionEnable[5];
 344
 345 /** Offset 0x006E - Protected Range Limitation
 346   The address of the upper limit of protection, 0x0FFFh(Default).
 347 **/
 348   UINT16                      ProtectedRangeLimit[5];
 349
 350 /** Offset 0x0078 - Protected Range Base
 351   The base address of the upper limit of protection. 0x0000(Default).
 352 **/
 353   UINT16                      ProtectedRangeBase[5];
 354
 355 /** Offset 0x0082 - Enable SC Gaussian Mixture Models
 356   Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).
 357   $EN_DIS
 358 **/
 359   UINT8                       Gmm;
 360
 361 /** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk
 362   Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).
 363   $EN_DIS
 364 **/
 365   UINT8                       ClkGatingPgcbClkTrunk;
 366
 367 /** Offset 0x0084 - GMM Clock Gating  - Sideband
 368   Enable/disable Sideband. 0:Disable, 1:Enable(Default).
 369   $EN_DIS
 370 **/
 371   UINT8                       ClkGatingSb;
 372
 373 /** Offset 0x0085 - GMM Clock Gating  - Sideband
 374   Enable/disable Sideband. 0:Disable, 1:Enable(Default).
 375   $EN_DIS
 376 **/
 377   UINT8                       ClkGatingSbClkTrunk;
 378
 379 /** Offset 0x0086 - GMM Clock Gating  - Sideband Clock Partition
 380   Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).
 381   $EN_DIS
 382 **/
 383   UINT8                       ClkGatingSbClkPartition;
 384
 385 /** Offset 0x0087 - GMM Clock Gating  - Core
 386   Enable/disable Core. 0:Disable, 1:Enable(Default).
 387   $EN_DIS
 388 **/
 389   UINT8                       ClkGatingCore;
 390
 391 /** Offset 0x0088 - GMM Clock Gating  - DMA
 392   Enable/disable DMA. 0:Disable, 1:Enable(Default).
 393   $EN_DIS
 394 **/
 395   UINT8                       ClkGatingDma;
 396
 397 /** Offset 0x0089 - GMM Clock Gating  - Register Access
 398   Enable/disable Register Access. 0:Disable, 1:Enable(Default).
 399   $EN_DIS
 400 **/
 401   UINT8                       ClkGatingRegAccess;
 402
 403 /** Offset 0x008A - GMM Clock Gating  - Host
 404   Enable/disable Host. 0:Disable, 1:Enable(Default).
 405   $EN_DIS
 406 **/
 407   UINT8                       ClkGatingHost;
 408
 409 /** Offset 0x008B - GMM Clock Gating  - Partition
 410   Enable/disable Partition. 0:Disable, 1:Enable(Default).
 411   $EN_DIS
 412 **/
 413   UINT8                       ClkGatingPartition;
 414
 415 /** Offset 0x008C - Clock Gating  - Trunk
 416   Enable/disable Trunk. 0:Disable, 1:Enable(Default).
 417   $EN_DIS
 418 **/
 419   UINT8                       ClkGatingTrunk;
 420
 421 /** Offset 0x008D - HD Audio Support
 422   Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).
 423   $EN_DIS
 424 **/
 425   UINT8                       HdaEnable;
 426
 427 /** Offset 0x008E - HD Audio DSP Support
 428   Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).
 429   $EN_DIS
 430 **/
 431   UINT8                       DspEnable;
 432
 433 /** Offset 0x008F - Azalia wake-on-ring
 434   Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.
 435   $EN_DIS
 436 **/
 437   UINT8                       Pme;
 438
 439 /** Offset 0x0090 - HD-Audio I/O Buffer Ownership
 440   Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)
 441   0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and
 442   I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
 443 **/
 444   UINT8                       HdAudioIoBufferOwnership;
 445
 446 /** Offset 0x0091 - HD-Audio I/O Buffer Voltage
 447   HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.
 448   0: 3.3V, 1: 1.8V
 449 **/
 450   UINT8                       HdAudioIoBufferVoltage;
 451
 452 /** Offset 0x0092 - HD-Audio Virtual Channel Type
 453   HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.
 454   0: VC0, 1: VC1
 455 **/
 456   UINT8                       HdAudioVcType;
 457
 458 /** Offset 0x0093 - HD-Audio Link Frequency
 459   HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
 460   4:96MHz, 5:Invalid.
 461   0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
 462 **/
 463   UINT8                       HdAudioLinkFrequency;
 464
 465 /** Offset 0x0094 - HD-Audio iDisp-Link Frequency
 466   HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
 467   4:96MHz, 5:Invalid.
 468   0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
 469 **/
 470   UINT8                       HdAudioIDispLinkFrequency;
 471
 472 /** Offset 0x0095 - HD-Audio iDisp-Link T-Mode
 473   HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.
 474   0: 2T, 1: 1T
 475 **/
 476   UINT8                       HdAudioIDispLinkTmode;
 477
 478 /** Offset 0x0096 - HD-Audio Disp DMIC
 479   HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.
 480   0: Disable, 1: 2ch array, 2: 4ch array
 481 **/
 482   UINT8                       DspEndpointDmic;
 483
 484 /** Offset 0x0097 - HD-Audio Bluetooth
 485   Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).
 486   $EN_DIS
 487 **/
 488   UINT8                       DspEndpointBluetooth;
 489
 490 /** Offset 0x0098 - HD-Audio I2S SHK
 491   Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.
 492   $EN_DIS
 493 **/
 494   UINT8                       DspEndpointI2sSkp;
 495
 496 /** Offset 0x0099 - HD-Audio I2S HP
 497   Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.
 498   $EN_DIS
 499 **/
 500   UINT8                       DspEndpointI2sHp;
 501
 502 /** Offset 0x009A - HD-Audio Controller Power Gating
 503   Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.
 504   $EN_DIS
 505 **/
 506   UINT8                       AudioCtlPwrGate;
 507
 508 /** Offset 0x009B - HD-Audio ADSP Power Gating
 509   Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.
 510   $EN_DIS
 511 **/
 512   UINT8                       AudioDspPwrGate;
 513
 514 /** Offset 0x009C - HD-Audio CSME Memory Transfers
 515   Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.
 516   0: VC0, 1: VC2
 517 **/
 518   UINT8                       Mmt;
 519
 520 /** Offset 0x009D - HD-Audio Host Memory Transfers
 521   Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.
 522   0: VC0, 1: VC2
 523 **/
 524   UINT8                       Hmt;
 525
 526 /** Offset 0x009E - HD-Audio Power Gating
 527   Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
 528   $EN_DIS
 529 **/
 530   UINT8                       HDAudioPwrGate;
 531
 532 /** Offset 0x009F - HD-Audio Clock Gatingn
 533   Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.
 534   $EN_DIS
 535 **/
 536   UINT8                       HDAudioClkGate;
 537
 538 /** Offset 0x00A0 - Bitmask of DSP Feature
 539   Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).
 540   [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
 541   - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
 542   Intel WoV, 1: Windows Voice Activation
 543 **/
 544   UINT32                      DspFeatureMask;
 545
 546 /** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules
 547   Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).
 548   [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
 549   - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
 550   Intel WoV, 1: Windows Voice Activation
 551 **/
 552   UINT32                      DspPpModuleMask;
 553
 554 /** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down
 555   Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
 556   This option is deprecated
 557   $EN_DIS
 558 **/
 559   UINT8                       BiosCfgLockDown;
 560
 561 /** Offset 0x00A9 - Enable High Precision Timer
 562   Enable/Disable Hpet. 0:Disable, 1:Enable(Default).
 563   $EN_DIS
 564 **/
 565   UINT8                       Hpet;
 566
 567 /** Offset 0x00AA - Hpet Valid BDF Value
 568   Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.
 569   $EN_DIS
 570 **/
 571   UINT8                       HpetBdfValid;
 572
 573 /** Offset 0x00AB - Bus Number of Hpet
 574   Completer ID of Bus Number of Hpet. Default = 0xFA(Default).
 575 **/
 576   UINT8                       HpetBusNumber;
 577
 578 /** Offset 0x00AC - Device Number of Hpet
 579   Completer ID of Device Number of Hpet. 0x1F(Default).
 580 **/
 581   UINT8                       HpetDeviceNumber;
 582
 583 /** Offset 0x00AD - Function Number of Hpet
 584   Completer ID of Function Number of Hpet. 0x00(Default).
 585 **/
 586   UINT8                       HpetFunctionNumber;
 587
 588 /** Offset 0x00AE - IoApic Valid BDF Value
 589   Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.
 590   $EN_DIS
 591 **/
 592   UINT8                       IoApicBdfValid;
 593
 594 /** Offset 0x00AF - Bus Number of IoApic
 595   Completer ID of Bus Number of IoApic. 0xFA(Default).
 596 **/
 597   UINT8                       IoApicBusNumber;
 598
 599 /** Offset 0x00B0 - Device Number of IoApic
 600   Completer ID of Device Number of IoApic. 0x0F(Default).
 601 **/
 602   UINT8                       IoApicDeviceNumber;
 603
 604 /** Offset 0x00B1 - Function Number of IoApic
 605   Completer ID of Function Number of IoApic. 0x00(Default).
 606 **/
 607   UINT8                       IoApicFunctionNumber;
 608
 609 /** Offset 0x00B2 - IOAPIC Entry 24-119
 610   Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).
 611   $EN_DIS
 612 **/
 613   UINT8                       IoApicEntry24_119;
 614
 615 /** Offset 0x00B3 - IO APIC ID
 616   This member determines IOAPIC ID. 0x01(Default).
 617 **/
 618   UINT8                       IoApicId;
 619
 620 /** Offset 0x00B4 - IoApic Range
 621   Define address bits 19:12 for the IOxAPIC range. 0x00(Default).
 622 **/
 623   UINT8                       IoApicRangeSelect;
 624
 625 /** Offset 0x00B5 - ISH Controller
 626   Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).
 627   $EN_DIS
 628 **/
 629   UINT8                       IshEnable;
 630
 631 /** Offset 0x00B6 - BIOS Interface Lock Down
 632   Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control
 633   Register. 0:Disable, 1:Enable(Default).
 634   $EN_DIS
 635 **/
 636   UINT8                       BiosInterface;
 637
 638 /** Offset 0x00B7 - Bios LockDown Enable
 639   Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.
 640   $EN_DIS
 641 **/
 642   UINT8                       BiosLock;
 643
 644 /** Offset 0x00B8 - SPI EISS Status
 645   Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).
 646   $EN_DIS
 647 **/
 648   UINT8                       SpiEiss;
 649
 650 /** Offset 0x00B9 - BiosLock SWSMI Number
 651   This member describes the SwSmi value for Bios Lock. 0xA9(Default).
 652 **/
 653   UINT8                       BiosLockSwSmiNumber;
 654
 655 /** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable
 656   Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.
 657   $EN_DIS
 658 **/
 659   UINT8                       LPSS_S0ixEnable;
 660
 661 /** Offset 0x00BB
 662 **/
 663   UINT8                       UnusedUpdSpace0[1];
 664
 665 /** Offset 0x00BC - LPSS I2C Clock Gating Configuration
 666   Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).
 667 **/
 668   UINT8                       I2cClkGateCfg[8];
 669
 670 /** Offset 0x00C4 - PSS HSUART Clock Gating Configuration
 671   Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).
 672 **/
 673   UINT8                       HsuartClkGateCfg[4];
 674
 675 /** Offset 0x00C8 - LPSS SPI Clock Gating Configuration
 676   Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).
 677 **/
 678   UINT8                       SpiClkGateCfg[3];
 679
 680 /** Offset 0x00CB - I2C Device 0
 681   Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 682   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 683 **/
 684   UINT8                       I2c0Enable;
 685
 686 /** Offset 0x00CC - I2C Device 1
 687   Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 688   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 689 **/
 690   UINT8                       I2c1Enable;
 691
 692 /** Offset 0x00CD - I2C Device 2
 693   Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 694   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 695 **/
 696   UINT8                       I2c2Enable;
 697
 698 /** Offset 0x00CE - I2C Device 3
 699   Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 700   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 701 **/
 702   UINT8                       I2c3Enable;
 703
 704 /** Offset 0x00CF - I2C Device 4
 705   Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 706   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 707 **/
 708   UINT8                       I2c4Enable;
 709
 710 /** Offset 0x00D0 - I2C Device 5
 711   Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 712   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 713 **/
 714   UINT8                       I2c5Enable;
 715
 716 /** Offset 0x00D1 - I2C Device 6
 717   Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 718   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 719 **/
 720   UINT8                       I2c6Enable;
 721
 722 /** Offset 0x00D2 - I2C Device 7
 723   Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 724   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 725 **/
 726   UINT8                       I2c7Enable;
 727
 728 /** Offset 0x00D3 - UART Device 0
 729   Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 730   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 731 **/
 732   UINT8                       Hsuart0Enable;
 733
 734 /** Offset 0x00D4 - UART Device 1
 735   Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 736   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 737 **/
 738   UINT8                       Hsuart1Enable;
 739
 740 /** Offset 0x00D5 - UART Device 2
 741   Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 742   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 743 **/
 744   UINT8                       Hsuart2Enable;
 745
 746 /** Offset 0x00D6 - UART Device 3
 747   Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 748   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 749 **/
 750   UINT8                       Hsuart3Enable;
 751
 752 /** Offset 0x00D7 - SPI UART Device 0
 753   Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 754   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 755 **/
 756   UINT8                       Spi0Enable;
 757
 758 /** Offset 0x00D8 - SPI UART Device 1
 759   Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 760   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 761 **/
 762   UINT8                       Spi1Enable;
 763
 764 /** Offset 0x00D9 - SPI UART Device 2
 765   Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
 766   0: Disabled, 1: PCI Mode, 2: ACPI Mode
 767 **/
 768   UINT8                       Spi2Enable;
 769
 770 /** Offset 0x00DA - OS Debug Feature
 771   Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.
 772   $EN_DIS
 773 **/
 774   UINT8                       OsDbgEnable;
 775
 776 /** Offset 0x00DB - DCI Feature
 777   Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.
 778   $EN_DIS
 779 **/
 780   UINT8                       DciEn;
 781
 782 /** Offset 0x00DC - UART Debug Base Address
 783   UART Debug Base Address. 0x00000000(Default).
 784 **/
 785   UINT32                      Uart2KernelDebugBaseAddress;
 786
 787 /** Offset 0x00E0 - Enable PCIE Clock Gating
 788   Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).
 789   0:Enable, 1:Disable
 790 **/
 791   UINT8                       PcieClockGatingDisabled;
 792
 793 /** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode
 794   Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).
 795   $EN_DIS
 796 **/
 797   UINT8                       PcieRootPort8xhDecode;
 798
 799 /** Offset 0x00E2 - PCIE 8xh Decode Port Index
 800   PCIE 8xh Decode Port Index. 0x00(Default).
 801 **/
 802   UINT8                       Pcie8xhDecodePortIndex;
 803
 804 /** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write
 805   Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.
 806   $EN_DIS
 807 **/
 808   UINT8                       PcieRootPortPeerMemoryWriteEnable;
 809
 810 /** Offset 0x00E4 - PCIE SWSMI Number
 811   This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).
 812 **/
 813   UINT8                       PcieAspmSwSmiNumber;
 814
 815 /** Offset 0x00E5
 816 **/
 817   UINT8                       UnusedUpdSpace1[1];
 818
 819 /** Offset 0x00E6 - PCI Express Root Port
 820   Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).
 821 **/
 822   UINT8                       PcieRootPortEn[6];
 823
 824 /** Offset 0x00EC - Hide PCIE Root Port Configuration Space
 825   Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.
 826 **/
 827   UINT8                       PcieRpHide[6];
 828
 829 /** Offset 0x00F2 - PCIE Root Port Slot Implement
 830   Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).
 831 **/
 832   UINT8                       PcieRpSlotImplemented[6];
 833
 834 /** Offset 0x00F8 - Hot Plug
 835   PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).
 836 **/
 837   UINT8                       PcieRpHotPlug[6];
 838
 839 /** Offset 0x00FE - PCIE PM SCI
 840   Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.
 841 **/
 842   UINT8                       PcieRpPmSci[6];
 843
 844 /** Offset 0x0104 - PCIE Root Port Extended Sync
 845   Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).
 846 **/
 847   UINT8                       PcieRpExtSync[6];
 848
 849 /** Offset 0x010A - Transmitter Half Swing
 850   Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).
 851 **/
 852   UINT8                       PcieRpTransmitterHalfSwing[6];
 853
 854 /** Offset 0x0110 - ACS
 855   Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).
 856 **/
 857   UINT8                       PcieRpAcsEnabled[6];
 858
 859 /** Offset 0x0116 - Clock Request Support
 860   Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).
 861 **/
 862   UINT8                       PcieRpClkReqSupported[6];
 863
 864 /** Offset 0x011C - Configure CLKREQ Number
 865   Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,
 866   0x01, 0x02, 0x03.
 867 **/
 868   UINT8                       PcieRpClkReqNumber[6];
 869
 870 /** Offset 0x0122 - CLKREQ# Detection
 871   Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.
 872 **/
 873   UINT8                       PcieRpClkReqDetect[6];
 874
 875 /** Offset 0x0128 - Advanced Error Reporting
 876   Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.
 877 **/
 878   UINT8                       AdvancedErrorReporting[6];
 879
 880 /** Offset 0x012E - PME Interrupt
 881   Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.
 882 **/
 883   UINT8                       PmeInterrupt[6];
 884
 885 /** Offset 0x0134 -   URR
 886   PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
 887 **/
 888   UINT8                       UnsupportedRequestReport[6];
 889
 890 /** Offset 0x013A -   FER
 891   PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
 892 **/
 893   UINT8                       FatalErrorReport[6];
 894
 895 /** Offset 0x0140 -   NFER
 896   PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
 897 **/
 898   UINT8                       NoFatalErrorReport[6];
 899
 900 /** Offset 0x0146 -   CER
 901   PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
 902 **/
 903   UINT8                       CorrectableErrorReport[6];
 904
 905 /** Offset 0x014C -   SEFE
 906   Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
 907 **/
 908   UINT8                       SystemErrorOnFatalError[6];
 909
 910 /** Offset 0x0152 -   SENFE
 911   Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
 912 **/
 913   UINT8                       SystemErrorOnNonFatalError[6];
 914
 915 /** Offset 0x0158 -   SECE
 916   Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.
 917 **/
 918   UINT8                       SystemErrorOnCorrectableError[6];
 919
 920 /** Offset 0x015E - PCIe Speed
 921   Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.
 922 **/
 923   UINT8                       PcieRpSpeed[6];
 924
 925 /** Offset 0x0164 - Physical Slot Number
 926   Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.
 927 **/
 928   UINT8                       PhysicalSlotNumber[6];
 929
 930 /** Offset 0x016A - CTO
 931   Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.
 932 **/
 933   UINT8                       PcieRpCompletionTimeout[6];
 934
 935 /** Offset 0x0170 - PTM Support
 936   Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.
 937 **/
 938   UINT8                       PtmEnable[6];
 939
 940 /** Offset 0x0176 - ASPM
 941   PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,
 942   4:Auto(Default).
 943 **/
 944   UINT8                       PcieRpAspm[6];
 945
 946 /** Offset 0x017C - L1 Substates
 947   PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).
 948 **/
 949   UINT8                       PcieRpL1Substates[6];
 950
 951 /** Offset 0x0182 - PCH PCIe LTR
 952   PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).
 953 **/
 954   UINT8                       PcieRpLtrEnable[6];
 955
 956 /** Offset 0x0188 - PCIE LTR Lock
 957   PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.
 958 **/
 959   UINT8                       PcieRpLtrConfigLock[6];
 960
 961 /** Offset 0x018E - PME_B0_S5 Disable bit
 962   PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.
 963   $EN_DIS
 964 **/
 965   UINT8                       PmeB0S5Dis;
 966
 967 /** Offset 0x018F - PCI Clock Run
 968   This member describes whether or not the PCI ClockRun feature of SC should be enabled.
 969   0:Disable(Default), 1:Enable.
 970   $EN_DIS
 971 **/
 972   UINT8                       PciClockRun;
 973
 974 /** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting
 975   Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.
 976   $EN_DIS
 977 **/
 978   UINT8                       Timer8254ClkSetting;
 979
 980 /** Offset 0x0191 - Chipset SATA
 981   Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports
 982   the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).
 983   $EN_DIS
 984 **/
 985   UINT8                       EnableSata;
 986
 987 /** Offset 0x0192 - SATA Mode Selection
 988   Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.
 989   0:AHCI, 1:RAID
 990 **/
 991   UINT8                       SataMode;
 992
 993 /** Offset 0x0193 - Aggressive LPM Support
 994   Enable PCH to aggressively enter link power state.  0:Disable, 1:Enable(Default).
 995   $EN_DIS
 996 **/
 997   UINT8                       SataSalpSupport;
 998
 999 /** Offset 0x0194 - SATA Power Optimization
1000   Enable SATA Power Optimizer on SC side.  0:Disable(Default), 1:Enable.
1001   $EN_DIS
1002 **/
1003   UINT8                       SataPwrOptEnable;
1004
1005 /** Offset 0x0195 - eSATA Speed Limit
1006   Enable/Disable eSATA Speed Limit.  0:Disable(Default), 1:Enable.
1007   $EN_DIS
1008 **/
1009   UINT8                       eSATASpeedLimit;
1010
1011 /** Offset 0x0196 - SATA Speed Limit
1012   SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).
1013   0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)
1014 **/
1015   UINT8                       SpeedLimit;
1016
1017 /** Offset 0x0197
1018 **/
1019   UINT8                       UnusedUpdSpace2[1];
1020
1021 /** Offset 0x0198 - SATA Port
1022   Enable or Disable SATA Port.  0:Disable, 1:Enable(Default).
1023 **/
1024   UINT8                       SataPortsEnable[2];
1025
1026 /** Offset 0x019A - SATA Port DevSlp
1027   Enable/Disable SATA Port  DevSlp. Board rework for LP needed before enable.  0:Disable(Default), 1:Enable.
1028 **/
1029   UINT8                       SataPortsDevSlp[2];
1030
1031 /** Offset 0x019C - SATA Port HotPlug
1032   Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.
1033 **/
1034   UINT8                       SataPortsHotPlug[2];
1035
1036 /** Offset 0x019E - Mechanical Presence Switch
1037   Controls reporting if this port has an Mechanical Presence Switch.\n
1038   Note:Requires hardware support.  0:Disable, 1:Enable(Default).
1039 **/
1040   UINT8                       SataPortsInterlockSw[2];
1041
1042 /** Offset 0x01A0 - External SATA Ports
1043   Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.
1044 **/
1045   UINT8                       SataPortsExternal[2];
1046
1047 /** Offset 0x01A2 - Spin Up Device
1048   Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.
1049 **/
1050   UINT8                       SataPortsSpinUp[2];
1051
1052 /** Offset 0x01A4 - SATA Solid State
1053   Identify the SATA port is connected to Solid State Drive or Hard Disk Drive.  0:Hard
1054   Disk Drive(Default), 1:Solid State Drive.
1055 **/
1056   UINT8                       SataPortsSolidStateDrive[2];
1057
1058 /** Offset 0x01A6 -   DITO Configuration
1059   Enable/Disable DITO Configuration.  0:Disable(Default), 1:Enable.
1060 **/
1061   UINT8                       SataPortsEnableDitoConfig[2];
1062
1063 /** Offset 0x01A8 - DM Value
1064   DM Value.  0:Minimum, 0x0F:Maximum(Default).
1065 **/
1066   UINT8                       SataPortsDmVal[2];
1067
1068 /** Offset 0x01AA
1069 **/
1070   UINT8                       UnusedUpdSpace3[2];
1071
1072 /** Offset 0x01AC - DITO Value
1073   DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).
1074 **/
1075   UINT16                      SataPortsDitoVal[2];
1076
1077 /** Offset 0x01B0 - Subsystem Vendor ID
1078   Subsystem Vendor ID. 0x8086(Default).
1079 **/
1080   UINT16                      SubSystemVendorId;
1081
1082 /** Offset 0x01B2 - Subsystem ID
1083   Subsystem ID. 0x7270(Default).
1084 **/
1085   UINT16                      SubSystemId;
1086
1087 /** Offset 0x01B4 - CRIDSettings
1088   PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.
1089 **/
1090   UINT8                       CRIDSettings;
1091
1092 /** Offset 0x01B5 - ResetSelect
1093   ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.
1094 **/
1095   UINT8                       ResetSelect;
1096
1097 /** Offset 0x01B6 - SD Card Support (D27:F0)
1098   Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).
1099   $EN_DIS
1100 **/
1101   UINT8                       SdcardEnabled;
1102
1103 /** Offset 0x01B7 - SeMMC Support (D28:F0)
1104   Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).
1105   $EN_DIS
1106 **/
1107   UINT8                       eMMCEnabled;
1108
1109 /** Offset 0x01B8 - eMMC Max Speed
1110   Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.
1111   0:HS400, 1: HS200, 2:DDR50
1112 **/
1113   UINT8                       eMMCHostMaxSpeed;
1114
1115 /** Offset 0x01B9 - UFS Support (D29:F0)
1116   Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
1117   $EN_DIS
1118 **/
1119   UINT8                       UfsEnabled;
1120
1121 /** Offset 0x01BA - SDIO Support (D30:F0)
1122   Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
1123   $EN_DIS
1124 **/
1125   UINT8                       SdioEnabled;
1126
1127 /** Offset 0x01BB - GPP Lock Feature
1128   Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.
1129   $EN_DIS
1130 **/
1131   UINT8                       GppLock;
1132
1133 /** Offset 0x01BC - Serial IRQ
1134   Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).
1135   $EN_DIS
1136 **/
1137   UINT8                       SirqEnable;
1138
1139 /** Offset 0x01BD - Serial IRQ Mode
1140   Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.
1141   $EN_DIS
1142 **/
1143   UINT8                       SirqMode;
1144
1145 /** Offset 0x01BE - Start Frame Pulse Width
1146   Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.
1147   0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk
1148 **/
1149   UINT8                       StartFramePulse;
1150
1151 /** Offset 0x01BF - Enable SMBus
1152   Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).
1153   $EN_DIS
1154 **/
1155   UINT8                       SmbusEnable;
1156
1157 /** Offset 0x01C0 - SMBus ARP Support
1158   Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).
1159   $EN_DIS
1160 **/
1161   UINT8                       ArpEnable;
1162
1163 /** Offset 0x01C1
1164 **/
1165   UINT8                       UnusedUpdSpace4;
1166
1167 /** Offset 0x01C2 - SMBus Table Elements
1168   The number of elements in the Reserved SMBus Address Table. 0x0080(Default).
1169 **/
1170   UINT16                      NumRsvdSmbusAddresses;
1171
1172 /** Offset 0x01C4 - Reserved SMBus Address Table
1173   Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).
1174 **/
1175   UINT8                       RsvdSmbusAddressTable[128];
1176
1177 /** Offset 0x0244 - XHCI Disable Compliance Mode
1178   Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance
1179   Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.
1180   $EN_DIS
1181 **/
1182   UINT8                       DisableComplianceMode;
1183
1184 /** Offset 0x0245 - USB Per-Port Control
1185   Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.
1186   $EN_DIS
1187 **/
1188   UINT8                       UsbPerPortCtl;
1189
1190 /** Offset 0x0246 - xHCI Mode
1191   Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)
1192   0:Disable, 1:Enable, 2:Auto
1193 **/
1194   UINT8                       Usb30Mode;
1195
1196 /** Offset 0x0247
1197 **/
1198   UINT8                       UnusedUpdSpace5[1];
1199
1200 /** Offset 0x0248 - Enable USB2 ports
1201   Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
1202   port1, and so on. 0x01(Default).
1203 **/
1204   UINT8                       PortUsb20Enable[8];
1205
1206 /** Offset 0x0250 - USB20 Over Current Pin
1207   Over Current Pin number of USB 2.0 Port. 0x00(Default).
1208 **/
1209   UINT8                       PortUs20bOverCurrentPin[8];
1210
1211 /** Offset 0x0258 - XDCI Support
1212   Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.
1213   0:Disable, 1:PCI_Mode, 2:ACPI_mode
1214 **/
1215   UINT8                       UsbOtg;
1216
1217 /** Offset 0x0259 - Enable XHCI HSIC Support
1218   Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.
1219   $EN_DIS
1220 **/
1221   UINT8                       HsicSupportEnable;
1222
1223 /** Offset 0x025A - Enable USB3 ports
1224   Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
1225   port1, and so on. 0x01(Default).
1226 **/
1227   UINT8                       PortUsb30Enable[6];
1228
1229 /** Offset 0x0260 - USB20 Over Current Pin
1230   Over Current Pin number of USB 3.0 Port. 0x01(Default).
1231 **/
1232   UINT8                       PortUs30bOverCurrentPin[6];
1233
1234 /** Offset 0x0266 - Enable XHCI SSIC Support
1235   Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for
1236   port1. 0x00(Default).
1237 **/
1238   UINT8                       SsicPortEnable[2];
1239
1240 /** Offset 0x0268 - SSIC Dlane PowerGating
1241   Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).
1242   $EN_DIS
1243 **/
1244   UINT16                      DlanePwrGating;
1245
1246 /** Offset 0x026A - VT-d
1247   Enable/Disable VT-d. 0:Disable(Default), 1:Enable.
1248   $EN_DIS
1249 **/
1250   UINT8                       VtdEnable;
1251
1252 /** Offset 0x026B - SMI Lock bit
1253   Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,
1254   1:Enable(Default).
1255   $EN_DIS
1256 **/
1257   UINT8                       LockDownGlobalSmi;
1258
1259 /** Offset 0x026C - HDAudio Delay Timer
1260   The delay timer after Azalia reset. 0x012C(Default).
1261 **/
1262   UINT16                      ResetWaitTimer;
1263
1264 /** Offset 0x026E - RTC Lock Bits
1265   Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).
1266   $EN_DIS
1267 **/
1268   UINT8                       RtcLock;
1269
1270 /** Offset 0x026F - SATA Test Mode Selection
1271   Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.
1272   $EN_DIS
1273 **/
1274   UINT8                       SataTestMode;
1275
1276 /** Offset 0x0270 - XHCI SSIC RATE
1277   Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.
1278 **/
1279   UINT8                       SsicRate[2];
1280
1281 /** Offset 0x0272 - SMBus Dynamic Power Gating
1282   Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.
1283   $EN_DIS
1284 **/
1285   UINT16                      DynamicPowerGating;
1286
1287 /** Offset 0x0274 - Max Snoop Latency
1288   Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).
1289 **/
1290   UINT16                      PcieRpLtrMaxSnoopLatency[6];
1291
1292 /** Offset 0x0280 -   Snoop Latency Override
1293   Snoop Latency Override for PCH PCIE. \n
1294   Disabled:Disable override.\n
1295   Manual:Manually enter override values.\n
1296   Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
1297 **/
1298   UINT8                       PcieRpSnoopLatencyOverrideMode[6];
1299
1300 /** Offset 0x0286
1301 **/
1302   UINT8                       UnusedUpdSpace6[2];
1303
1304 /** Offset 0x0288 -   Snoop Latency Value
1305   LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
1306 **/
1307   UINT16                      PcieRpSnoopLatencyOverrideValue[6];
1308
1309 /** Offset 0x0294 -   Snoop Latency Multiplier
1310   LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,
1311   4:1048576ns, 5:33554432ns.
1312 **/
1313   UINT8                       PcieRpSnoopLatencyOverrideMultiplier[6];
1314
1315 /** Offset 0x029A - Skip Multi-Processor Initialization
1316   When this is skipped, boot loader must initialize processors before SilicionInit
1317   API. 0: Initialize(Default), <b>1: Skip
1318   $EN_DIS
1319 **/
1320   UINT8                       SkipMpInit;
1321
1322 /** Offset 0x029B - DCI Auto Detect
1323   Enable/disable DCI AUTO mode. Enabled(Default).
1324   $EN_DIS
1325 **/
1326   UINT8                       DciAutoDetect;
1327
1328 /** Offset 0x029C - Max Non-Snoop Latency
1329   Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).
1330 **/
1331   UINT16                      PcieRpLtrMaxNonSnoopLatency[6];
1332
1333 /** Offset 0x02A8 -   Non Snoop Latency Override
1334   Non Snoop Latency Override for PCH PCIE. \n
1335   Disabled:Disable override.\n
1336   Manual:Manually enter override values.\n
1337   Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
1338 **/
1339   UINT8                       PcieRpNonSnoopLatencyOverrideMode[6];
1340
1341 /** Offset 0x02AE - Halt and Lock TCO Timer
1342   Halt and Lock the TCO Timer (Watchdog).
1343   0:No, 1:Yes (default)
1344 **/
1345   UINT8                       TcoTimerHaltLock;
1346
1347 /** Offset 0x02AF - Power Button Override Period
1348   specifies how long will PMC wait before initiating a global reset. 000b-4s(default),
1349   001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)
1350   0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s
1351 **/
1352   UINT8                       PwrBtnOverridePeriod;
1353
1354 /** Offset 0x02B0 -   Non Snoop Latency Value
1355   LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
1356 **/
1357   UINT16                      PcieRpNonSnoopLatencyOverrideValue[6];
1358
1359 /** Offset 0x02BC -   Non Snoop Latency Multiplier
1360   LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),
1361   3:32768ns, 4:1048576ns, 5:33554432ns.
1362 **/
1363   UINT8                       PcieRpNonSnoopLatencyOverrideMultiplier[6];
1364
1365 /** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale
1366   Specifies scale used for slot power limit value. 0x00(Default).
1367 **/
1368   UINT8                       PcieRpSlotPowerLimitScale[6];
1369
1370 /** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value
1371   Specifies upper limit on power supplie by slot. 0x00(Default).
1372 **/
1373   UINT8                       PcieRpSlotPowerLimitValue[6];
1374
1375 /** Offset 0x02CE - Power Button Native Mode Disable
1376   Disable power button native mode, when 1, this will result in the PMC logic constantly
1377   seeing the power button as de-asserted. 0 (default))
1378   $EN_DIS
1379 **/
1380   UINT8                       DisableNativePowerButton;
1381
1382 /** Offset 0x02CF - Power Button Debounce Mode
1383   Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)
1384   $EN_DIS
1385 **/
1386   UINT8                       PowerButterDebounceMode;
1387
1388 /** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL
1389   SDIO_TX_CMD_DLL_CNTL. 0x505(Default).
1390 **/
1391   UINT32                      SdioTxCmdCntl;
1392
1393 /** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1
1394   SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).
1395 **/
1396   UINT32                      SdioTxDataCntl1;
1397
1398 /** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2
1399   SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).
1400 **/
1401   UINT32                      SdioTxDataCntl2;
1402
1403 /** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1
1404   SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).
1405 **/
1406   UINT32                      SdioRxCmdDataCntl1;
1407
1408 /** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2
1409   SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
1410 **/
1411   UINT32                      SdioRxCmdDataCntl2;
1412
1413 /** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL
1414   SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).
1415 **/
1416   UINT32                      SdcardTxCmdCntl;
1417
1418 /** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1
1419   SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).
1420 **/
1421   UINT32                      SdcardTxDataCntl1;
1422
1423 /** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2
1424   SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).
1425 **/
1426   UINT32                      SdcardTxDataCntl2;
1427
1428 /** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1
1429   SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).
1430 **/
1431   UINT32                      SdcardRxCmdDataCntl1;
1432
1433 /** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL
1434   SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).
1435 **/
1436   UINT32                      SdcardRxStrobeCntl;
1437
1438 /** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2
1439   SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
1440 **/
1441   UINT32                      SdcardRxCmdDataCntl2;
1442
1443 /** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL
1444   EMMC_TX_CMD_DLL_CNTL. 0x505(Default).
1445 **/
1446   UINT32                      EmmcTxCmdCntl;
1447
1448 /** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1
1449   EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).
1450 **/
1451   UINT32                      EmmcTxDataCntl1;
1452
1453 /** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2
1454   EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).
1455 **/
1456   UINT32                      EmmcTxDataCntl2;
1457
1458 /** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1
1459   EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).
1460 **/
1461   UINT32                      EmmcRxCmdDataCntl1;
1462
1463 /** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL
1464   EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).
1465 **/
1466   UINT32                      EmmcRxStrobeCntl;
1467
1468 /** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2
1469   EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).
1470 **/
1471   UINT32                      EmmcRxCmdDataCntl2;
1472
1473 /** Offset 0x0314 - EMMC_MASTER_DLL_CNTL
1474   EMMC_MASTER_DLL_CNTL. 0x001(Default).
1475 **/
1476   UINT32                      EmmcMasterSwCntl;
1477
1478 /** Offset 0x0318 - SGX Epoch 0
1479   SGX Epoch 0. 0x0(Default).
1480 **/
1481   UINT64                      SgxEpoch0;
1482
1483 /** Offset 0x0320 - SGX Epoch 1
1484   SGX Epoch 1. 0x0(Default).
1485 **/
1486   UINT64                      SgxEpoch1;
1487
1488 /** Offset 0x0328 - MicrocodePatchAddress
1489   MicrocodePatchAddress. 0x0(Default).
1490 **/
1491   UINT64                      MicrocodePatchAddress;
1492
1493 /** Offset 0x0330 - PCIe Selectable De-emphasis
1494   When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis
1495   for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).
1496 **/
1497   UINT8                       PcieRpSelectableDeemphasis[6];
1498
1499 /** Offset 0x0336 - Monitor Mwait Enable
1500   Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux
1501   based OS, this should be Disabled. 0:Disable, 1:Enable(Default).
1502   $EN_DIS
1503 **/
1504   UINT8                       MonitorMwaitEnable;
1505
1506 /** Offset 0x0337 - Universal Audio Architecture compliance for DSP enabled system
1507   0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
1508   driver or SST driver supported).
1509   $EN_DIS
1510 **/
1511   UINT8                       HdAudioDspUaaCompliance;
1512
1513 /** Offset 0x0338 - IRQ Interrupt Polarity Control
1514   Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low
1515 **/
1516   UINT32                      IPC[4];
1517
1518 /** Offset 0x0348 - Disable ModPHY dynamic power gate
1519   Disable ModPHY dynamic power gate for the specific SATA port.
1520 **/
1521   UINT8                       SataPortsDisableDynamicPg[2];
1522
1523 /** Offset 0x034A - Init CPU during S3 resume
1524   0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume.
1525   $EN_DIS
1526 **/
1527   UINT8                       InitS3Cpu;
1528
1529 /** Offset 0x034B - CNVi Mode
1530   Selects CNVi Mode. 0:Disable, 1:Auto(Default).
1531   $EN_DIS
1532 **/
1533   UINT8                       CnviMode;
1534
1535 /** Offset 0x034C - BT Interface
1536   CNVi BT interface. 0:UART, 1:USB(Default).
1537   $EN_DIS
1538 **/
1539   UINT8                       CnviBtInterface;
1540
1541 /** Offset 0x034D - Disable Sx Wake
1542   Enables/Disables wake from Sx . 0:No(Default), 1:Yes.
1543   $EN_DIS
1544 **/
1545   UINT8                       DisableSxWake;
1546
1547 /** Offset 0x034E - ModifyCrfGpios
1548   Feature to Configure CRF Gpios Conditionally upon platform requirement, configuration
1549   of GNSS and BtOnUart gpios will/will not be done based on this policy
1550   $EN_DIS
1551 **/
1552   UINT8                       ModifyCrfGpios;
1553
1554 /** Offset 0x034F -  dGPU Hold Reset
1555   dGPU Hold Reset GPIO information from GPIO community, Pin and Active
1556 **/
1557   UINT8                       HgDgpuHoldRst[8];
1558
1559 /** Offset 0x0357 - dGPU Power Enable
1560   dGPU power enable GPIO information from GPIO community, Pin and Active
1561 **/
1562   UINT8                       HgDgpuPwrEnable[8];
1563
1564 /** Offset 0x035F - HG Enable
1565   Enables/Disables Hybrid Graphics . 0 : Disable(Default), 1 : Enable
1566   0x1:Enabled, 0x0:Disabled
1567 **/
1568   UINT8                       HgEnabled;
1569
1570 /** Offset 0x0360 - dGPU Delay after power enable
1571   Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,
1572   300 : Default
1573   0 : Minimum , 1000 : Maximum , 300 : Default
1574 **/
1575   UINT16                      HgDelayAfterPwrEn;
1576
1577 /** Offset 0x0362 -  dGPU Delay after hold reset
1578   Delay for DGPU after Hold Reset if HG is enable : 0 : Minimum , 1000 : Maximum ,
1579   100 : Default
1580   0 : Minimum , 1000 : Maximum , 100 : Default
1581 **/
1582   UINT16                      HgDelayAfterHoldReset;
1583
1584 /** Offset 0x0364 - CpuS3ResumeMtrrDataSize
1585   Size of S3 resume MTRR data.
1586 **/
1587   UINT16                      CpuS3ResumeMtrrDataSize;
1588
1589 /** Offset 0x0366 - PAVP ASMF
1590   Enable/Disable PAVP ASMF  0:Disable, 1:Enable(Default).
1591   $EN_DIS
1592 **/
1593   UINT8                       PavpAsmf;
1594
1595 /** Offset 0x0367 - PAVP Auto TearDown Grace Period Enable
1596   Enable/Disable PAVP Auto TearDown Grace Period 0:Disable, 1:Enable(Default).
1597   $EN_DIS
1598 **/
1599   UINT8                       AutoTearDownGracePeriod;
1600
1601 /** Offset 0x0368 - CpuS3ResumeMtrrData
1602   Pointer CPU S3 Resume MTRR Data
1603 **/
1604   UINT32                      CpuS3ResumeMtrrData;
1605
1606 /** Offset 0x036C - SeC EndOfPost EnableDisable
1607   Enable/Disable SeC EOPEnable  0:Disable, 1:Enable(Default).
1608   $EN_DIS
1609 **/
1610   UINT8                       EndOfPostEnabled;
1611
1612 /** Offset 0x036D - EnableDigitalThermalSensor EnableDisable
1613   Enable/Disable EnableDigitalThermalSensor  0:Disable(Default), 1:Enable.
1614   $EN_DIS
1615 **/
1616   UINT8                       EnableDigitalThermalSensor;
1617
1618 /** Offset 0x036E - PNP Mode
1619   Select PNP Mode. 0:Disable,1:Power,2:Performance,3:Power&Performance
1620   0:Disable,1:Power,2:Performance,3:Power&Performance(default)
1621 **/
1622   UINT8                       PnpSettings;
1623
1624 /** Offset 0x036F - OsBoot EnableDisable
1625   Select OsBoot. 1:EMMC boot, 0:HardDisk boot
1626   1:EMMC boot, 1:HardDisk boot
1627 **/
1628   UINT8                       OsBoot;
1629
1630 /** Offset 0x0370 - System Vendor ID
1631   Upd for vendor ID for assigning to devices
1632 **/
1633   UINT16                      SiSVID;
1634
1635 /** Offset 0x0372 - Sub system Vendor ID
1636   Upd for subsystem ID for assigning to devices
1637 **/
1638   UINT16                      SiSSID;
1639
1640 /** Offset 0x0374 - CpuBistData
1641   Pointer CPU BIST Data
1642 **/
1643   UINT32                      CpuBistData;
1644
1645 /** Offset 0x0378 - Base of memory region allocated for Processor Trace
1646   Base address of memory region allocated for Processor Trace. Processor Trace requires
1647   2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
1648 **/
1649   UINT64                      ProcessorTraceMemBase;
1650
1651 /** Offset 0x0380 - Memory region allocation for Processor Trace
1652   Length in bytes of memory region allocated for Processor Trace. Processor Trace
1653   requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
1654 **/
1655   UINT32                      ProcessorTraceMemLength;
1656
1657 /** Offset 0x0384 - AP threads Idle Manner
1658   AP threads Idle Manner for waiting signal to run 1:HALT loop 2:MWAIT loop 3:RUN lOOP
1659   $EN_DIS
1660 **/
1661   UINT8                       ApIdleManner;
1662
1663 /** Offset 0x0385 - Skip P-unit Initialization
1664   When this is skipped, boot loader must initialize P-unit before SilicionInit API.
1665   0: Initialize(Default), 1: Skip
1666   $EN_DIS
1667 **/
1668   UINT8                       SkipPunitInit;
1669
1670 /** Offset 0x0386 - Sub system Vendor ID VGA
1671   Graphics PCI subsystem HgSubSystemId
1672 **/
1673   UINT16                      HgSubSystemId;
1674
1675 /** Offset 0x0388 - USB Per Port HS Preemphasis Bias
1676   USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
1677   100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
1678 **/
1679   UINT8                       Usb2AfePetxiset[8];
1680
1681 /** Offset 0x0390 - USB Per Port HS Transmitter Bias
1682   USB Per Port HS Transmitter Bias. 000b-0mV, 001b-40.5mV, 010b-60.5mV, 011b-102mV,
1683   100b-102mV, 101b-142mV, 110b-162.5mV, 111b-202.5mV. One byte for each port.
1684 **/
1685   UINT8                       Usb2AfeTxiset[8];
1686
1687 /** Offset 0x0398 - USB Per Port HS Transmitter Emphasis
1688   USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
1689   10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
1690 **/
1691   UINT8                       Usb2AfePredeemp[8];
1692
1693 /** Offset 0x03A0 - USB Per Port Half Bit Pre-emphasis
1694   USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
1695   One byte for each port.
1696 **/
1697   UINT8                       Usb2AfePehalfbit[8];
1698
1699 /** Offset 0x03A8 - Intel Processor Trace output Scheme method
1700   Intel Processor Trace output Scheme method 0:Single Range Output (Default) 1. ToPA Output
1701 **/
1702   UINT8                       ProcessorTraceOutputScheme;
1703
1704 /** Offset 0x03A9 - USB PDO Programming
1705   Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
1706   during later phase. 1: enable, 0: disable
1707   1: enable, 0: disable
1708 **/
1709   UINT8                       UsbPdoProgramming;
1710
1711 /** Offset 0x03AA - Skip LPSS SPI Private Clock Parameter Programming
1712   When this is skipped, boot loader must program LPSS SPI PCP. 0: Initialize(Default),
1713   <b>1: Skip
1714   $EN_DIS
1715 **/
1716   UINT8                       SkipSpiPCP;
1717
1718 /** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration
1719   Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
1720   (23:16) + OR Value (15:8) + AND Value (7:0)
1721 **/
1722   UINT32                      PmicPmcIpcCtrl;
1723
1724 /** Offset 0x03AF
1725 **/
1726   UINT8                       ReservedFspsUpd[1];
1727 } FSP_S_CONFIG;
1728
1729 /** Fsp S SGX Configuration
1730 **/
1731 typedef struct {
1732
1733 /** Offset 0x03C0
1734 **/
1735   UINT32                      Signature;
1736
1737 /** Offset 0x03C4 - Selective enable SGX
1738   Selective enable SGX. 0xFFFF(Default).
1739 **/
1740   UINT16                      SelectiveEnableSgx;
1741
1742 /** Offset 0x03C6 - SGX debug mode
1743   Select SGX mode. 0:Disable(default), 1:Enable
1744   0:Disable(default), 1:Enable
1745 **/
1746   UINT8                       SgxDebugMode;
1747
1748 /** Offset 0x03C7 - SGX Launch Control Policy Mode
1749   Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
1750   0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode
1751 **/
1752   UINT8                       SgxLcp;
1753
1754 /** Offset 0x03C8 - LE KeyHash0
1755   LE KeyHash0. 0x0(Default).
1756 **/
1757   UINT64                      SgxLePubKeyHash0;
1758
1759 /** Offset 0x03D0 - LE KeyHash1
1760   LE KeyHash1. 0x0(Default).
1761 **/
1762   UINT64                      SgxLePubKeyHash1;
1763
1764 /** Offset 0x03D8 - LE KeyHash2
1765   LE KeyHash2. 0x0(Default).
1766 **/
1767   UINT64                      SgxLePubKeyHash2;
1768
1769 /** Offset 0x03E0
1770 **/
1771   UINT8                       UnusedUpdSpace8[16];
1772
1773 /** Offset 0x03F0 - LE KeyHash3
1774   LE KeyHash3. 0x0(Default).
1775 **/
1776   UINT64                      SgxLePubKeyHash3;
1777
1778 /** Offset 0x03F8
1779 **/
1780   UINT8                       ReservedFspsSgxUpd[8];
1781 } FSP_S_SGX_CONFIG;
1782
1783 /** Fsp S UPD Configuration
1784 **/
1785 typedef struct {
1786
1787 /** Offset 0x0000
1788 **/
1789   FSP_UPD_HEADER              FspUpdHeader;
1790
1791 /** Offset 0x0020
1792 **/
1793   FSP_S_CONFIG                FspsConfig;
1794
1795 /** Offset 0x03B0
1796 **/
1797   UINT8                       UnusedUpdSpace7[16];
1798
1799 /** Offset 0x03C0
1800 **/
1801   FSP_S_SGX_CONFIG            FspsSgxConfig;
1802
1803 /** Offset 0x0400
1804 **/
1805   UINT8                       UnusedUpdSpace9[6];
1806
1807 /** Offset 0x0406
1808 **/
1809   UINT16                      UpdTerminator;
1810 } FSPS_UPD;
1811
1812 #pragma pack(pop)
1813
1814 #endif