2 * This file is part of the coreboot project.
4 * Copyright (C) 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
19 #include <arch/early_variables.h>
21 #include <commonlib/region.h>
23 #define SPD_PAGE_LEN 256
24 #define SPD_PAGE_LEN_DDR4 512
25 #define SPD_PAGE_0 (0x6C >> 1)
26 #define SPD_PAGE_1 (0x6E >> 1)
27 #define SPD_DRAM_TYPE 2
28 #define SPD_DRAM_DDR3 0x0B
29 #define SPD_DRAM_LPDDR3_INTEL 0xF1
30 #define SPD_DRAM_LPDDR3_JEDEC 0x0F
31 #define SPD_DRAM_DDR4 0x0C
32 #define SPD_DENSITY_BANKS 4
33 #define SPD_ADDRESSING 5
34 #define SPD_ORGANIZATION 7
35 #define SPD_BUS_DEV_WIDTH 8
36 #define DDR3_SPD_PART_OFF 128
37 #define DDR3_SPD_PART_LEN 18
38 #define LPDDR3_SPD_PART_OFF 128
39 #define LPDDR3_SPD_PART_LEN 18
40 #define DDR4_SPD_PART_OFF 329
41 #define DDR4_SPD_PART_LEN 20
42 #define LPDDR4_SPD_PART_OFF 329
43 #define LPDDR4_SPD_PART_LEN 20
46 u8 addr_map
[CONFIG_DIMM_MAX
]; /* 7 bit I2C addresses */
47 u8
*spd_array
[CONFIG_DIMM_MAX
];
48 /* Length of each dimm */
52 void print_spd_info(uint8_t spd
[]);
53 /* Return 0 on success & -1 on failure */
54 int get_spd_cbfs_rdev(struct region_device
*spd_rdev
, u8 spd_index
);
55 void dump_spd_info(struct spd_block
*blk
);
56 void get_spd_smbus(struct spd_block
*blk
);
58 /* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
59 verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
60 int read_ddr3_spd_from_cbfs(u8
*buf
, int idx
);