src/include/spd.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Digital Design Corporation
   5  * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 /*
  19  * Serial Presence Detect (SPD) data stored on SDRAM modules.
  20  *
  21  * Datasheet:
  22  *   - Name: PC SDRAM Serial Presence Detect (SPD) Specification
  23  *           Revision 1.2A, December, 1997
  24  *   - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf
  25  *
  26  * Datasheet (alternative):
  27  *   - Name: SERIAL PRESENCE DETECT STANDARD, General Standard
  28  *           JEDEC Standard No. 21-C
  29  *   - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF
  30  */
  31
  32 #ifndef _SPD_H_
  33 #define _SPD_H_
  34
  35 /* Byte numbers. */
  36 #define SPD_NUM_MANUFACTURER_BYTES          0  /* Number of bytes used by module manufacturer */
  37 #define SPD_TOTAL_SPD_MEMORY_SIZE           1  /* Total SPD memory size */
  38 #define SPD_MEMORY_TYPE                     2  /* (Fundamental) memory type */
  39 #define SPD_NUM_ROWS                        3  /* Number of row address bits */
  40 #define SPD_NUM_COLUMNS                     4  /* Number of column address bits */
  41 #define SPD_NUM_DIMM_BANKS                  5  /* Number of module rows (banks) */
  42 #define SPD_MODULE_DATA_WIDTH_LSB           6  /* Module data width (LSB) */
  43 #define SPD_MODULE_DATA_WIDTH_MSB           7  /* Module data width (MSB) */
  44 #define SPD_MODULE_VOLTAGE                  8  /* Module interface signal levels */
  45 #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX       9  /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
  46 #define SPD_ACCESS_TIME_FROM_CLOCK          10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
  47 #define SPD_DIMM_CONFIG_TYPE                11 /* Module configuration type */
  48 #define SPD_REFRESH                         12 /* Refresh rate/type */
  49 #define SPD_PRIMARY_SDRAM_WIDTH             13 /* SDRAM width (primary SDRAM) */
  50 #define SPD_ERROR_CHECKING_SDRAM_WIDTH      14 /* Error checking SDRAM (data) width */
  51 #define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */
  52 #define SPD_SUPPORTED_BURST_LENGTHS         16 /* SDRAM device attributes, burst lengths supported */
  53 #define SPD_NUM_BANKS_PER_SDRAM             17 /* SDRAM device attributes, number of banks on SDRAM device */
  54 #define SPD_ACCEPTABLE_CAS_LATENCIES        18 /* SDRAM device attributes, CAS latency */
  55 #define SPD_CS_LATENCY                      19 /* SDRAM device attributes, CS latency */
  56 #define SPD_WE_LATENCY                      20 /* SDRAM device attributes, WE latency */
  57 #define SPD_MODULE_ATTRIBUTES               21 /* SDRAM module attributes */
  58 #define SPD_DEVICE_ATTRIBUTES_GENERAL       22 /* SDRAM device attributes, general */
  59 #define SPD_SDRAM_CYCLE_TIME_2ND            23 /* SDRAM cycle time (2nd highest CAS latency) */
  60 #define SPD_ACCESS_TIME_FROM_CLOCK_2ND      24 /* SDRAM access from clock (2nd highest CAS latency) */
  61 #define SPD_SDRAM_CYCLE_TIME_3RD            25 /* SDRAM cycle time (3rd highest CAS latency) */
  62 #define SPD_ACCESS_TIME_FROM_CLOCK_3RD      26 /* SDRAM access from clock (3rd highest CAS latency) */
  63 #define SPD_MIN_ROW_PRECHARGE_TIME          27 /* Minimum row precharge time (Trp) */
  64 #define SPD_MIN_ROWACTIVE_TO_ROWACTIVE      28 /* Minimum row active to row active (Trrd) */
  65 #define SPD_MIN_RAS_TO_CAS_DELAY            29 /* Minimum RAS to CAS delay (Trcd) */
  66 #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY   30 /* Minimum RAS pulse width (Tras) */
  67 #define SPD_DENSITY_OF_EACH_ROW_ON_MODULE   31 /* Density of each row on module */
  68 #define SPD_CMD_SIGNAL_INPUT_SETUP_TIME     32 /* Command and address signal input setup time */
  69 #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME      33 /* Command and address signal input hold time */
  70 #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME    34 /* Data signal input setup time */
  71 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME     35 /* Data signal input hold time */
  72 #define SPD_WRITE_RECOVERY_TIME             36 /* Write recovery time (tWR) */
  73 #define SPD_INT_WRITE_TO_READ_DELAY         37 /* Internal write to read command delay (tWTR) */
  74 #define SPD_INT_READ_TO_PRECHARGE_DELAY     38 /* Internal read to precharge command delay (tRTP) */
  75 #define SPD_MEM_ANALYSIS_PROBE_PARAMS       39 /* Memory analysis probe characteristics */
  76 #define SPD_BYTE_41_42_EXTENSION            40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
  77 #define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH     41 /* Minimum active to active auto refresh (tRCmin) */
  78 #define SPD_MIN_AUTO_REFRESH_TO_ACT         42 /* Minimum auto refresh to active/auto refresh (tRFC) */
  79 #define SPD_MAX_DEVICE_CYCLE_TIME           43 /* Maximum device cycle time (tCKmax) */
  80 #define SPD_MAX_DQS_DQ_SKEW                 44 /* Maximum skew between DQS and DQ (tDQSQ) */
  81 #define SPD_MAX_READ_DATAHOLD_SKEW          45 /* Maximum read data-hold skew factor (tQHS) */
  82 #define SPD_PLL_RELOCK_TIME                 46 /* PLL relock time */
  83 #define SPD_SPD_DATA_REVISION_CODE          62 /* SPD data revision code */
  84 #define SPD_CHECKSUM_FOR_BYTES_0_TO_62      63 /* Checksum for bytes 0-62 */
  85 #define SPD_MANUFACTURER_JEDEC_ID_CODE      64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
  86 #define SPD_MANUFACTURING_LOCATION          72 /* Manufacturing location */
  87 #define SPD_MANUFACTURER_PART_NUMBER        73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
  88 #define SPD_REVISION_CODE                   91 /* Revision code (bytes 91-92) */
  89 #define SPD_MANUFACTURING_DATE              93 /* Manufacturing date (byte 93: year, byte 94: week) */
  90 #define SPD_ASSEMBLY_SERIAL_NUMBER          95 /* Assembly serial number (bytes 95-98) */
  91 #define SPD_MANUFACTURER_SPECIFIC_DATA      99 /* Manufacturer specific data (bytes 99-125) */
  92 #define SPD_INTEL_SPEC_FOR_FREQUENCY       126 /* Intel specification for frequency */
  93 #define SPD_INTEL_SPEC_100_MHZ             127 /* Intel specification details for 100MHz support */
  94
  95 /* DRAM specifications use the following naming conventions for SPD locations */
  96 #define SPD_tRP                             SPD_MIN_ROW_PRECHARGE_TIME
  97 #define SPD_tRRD                            SPD_MIN_ROWACTIVE_TO_ROWACTIVE
  98 #define SPD_tRCD                            SPD_MIN_RAS_TO_CAS_DELAY
  99 #define SPD_tRAS                            SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
 100 #define SPD_BANK_DENSITY                    SPD_DENSITY_OF_EACH_ROW_ON_MODULE
 101 #define SPD_ADDRESS_CMD_HOLD                SPD_CMD_SIGNAL_INPUT_HOLD_TIME
 102 #define SPD_tRC                             41  /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
 103 #define SPD_tRFC                            42  /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
 104
 105
 106 /* SPD_MEMORY_TYPE values. */
 107 enum spd_memory_type {
 108         SPD_MEMORY_TYPE_UNDEFINED               = 0x00,
 109         SPD_MEMORY_TYPE_FPM_DRAM                = 0x01,
 110         SPD_MEMORY_TYPE_EDO                     = 0x02,
 111         SPD_MEMORY_TYPE_PIPELINED_NIBBLE        = 0x03,
 112         SPD_MEMORY_TYPE_SDRAM                   = 0x04,
 113         SPD_MEMORY_TYPE_MULTIPLEXED_ROM         = 0x05,
 114         SPD_MEMORY_TYPE_SGRAM_DDR               = 0x06,
 115         SPD_MEMORY_TYPE_SDRAM_DDR               = 0x07,
 116         SPD_MEMORY_TYPE_SDRAM_DDR2              = 0x08,
 117         SPD_MEMORY_TYPE_FBDIMM_DDR2             = 0x09,
 118         SPD_MEMORY_TYPE_FB_PROBE_DDR2           = 0x0a,
 119         SPD_MEMORY_TYPE_SDRAM_DDR3              = 0x0b,
 120 };
 121
 122 /* SPD_MODULE_VOLTAGE values. */
 123 #define SPD_VOLTAGE_TTL                  0 /* 5.0 Volt/TTL */
 124 #define SPD_VOLTAGE_LVTTL                1 /* LVTTL */
 125 #define SPD_VOLTAGE_HSTL                 2 /* HSTL 1.5 */
 126 #define SPD_VOLTAGE_SSTL3                3 /* SSTL 3.3 */
 127 #define SPD_VOLTAGE_SSTL2                4 /* SSTL 2.5 */
 128
 129 /* SPD_DIMM_CONFIG_TYPE values. */
 130 #define ERROR_SCHEME_NONE                0
 131 #define ERROR_SCHEME_PARITY              1
 132 #define ERROR_SCHEME_ECC                 2
 133
 134 /* SPD_ACCEPTABLE_CAS_LATENCIES values. */
 135 // TODO: Check values.
 136 #define SPD_CAS_LATENCY_1_0              0x01
 137 #define SPD_CAS_LATENCY_1_5              0x02
 138 #define SPD_CAS_LATENCY_2_0              0x04
 139 #define SPD_CAS_LATENCY_2_5              0x08
 140 #define SPD_CAS_LATENCY_3_0              0x10
 141 #define SPD_CAS_LATENCY_3_5              0x20
 142 #define SPD_CAS_LATENCY_4_0              0x40
 143
 144 #define SPD_CAS_LATENCY_DDR2_3          (1 << 3)
 145 #define SPD_CAS_LATENCY_DDR2_4          (1 << 4)
 146 #define SPD_CAS_LATENCY_DDR2_5          (1 << 5)
 147 #define SPD_CAS_LATENCY_DDR2_6          (1 << 6)
 148
 149 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 150 #define SPD_BURST_LENGTH_1               1
 151 #define SPD_BURST_LENGTH_2               2
 152 #define SPD_BURST_LENGTH_4               4
 153 #define SPD_BURST_LENGTH_8               8
 154 #define SPD_BURST_LENGTH_PAGE            (1 << 7)
 155
 156 /* SPD_MODULE_ATTRIBUTES values. */
 157 #define MODULE_BUFFERED                  1
 158 #define MODULE_REGISTERED                2
 159
 160 /* DIMM SPD addresses */
 161 #define DIMM0                            0x50
 162 #define DIMM1                            0x51
 163 #define DIMM2                            0x52
 164 #define DIMM3                            0x53
 165 #define DIMM4                            0x54
 166 #define DIMM5                            0x55
 167 #define DIMM6                            0x56
 168 #define DIMM7                            0x57
 169
 170 #define RC00 0
 171 #define RC01 1
 172 #define RC02 2
 173 #define RC03 3
 174 #define RC04 4
 175 #define RC05 5
 176 #define RC06 6
 177 #define RC07 7
 178 #define RC08 8
 179 #define RC09 9
 180 #define RC10 10
 181 #define RC11 11
 182 #define RC12 12
 183 #define RC13 13
 184 #define RC14 14
 185 #define RC15 15
 186 #define RC16 16
 187 #define RC17 17
 188 #define RC18 18
 189 #define RC19 19
 190 #define RC20 20
 191 #define RC21 21
 192 #define RC22 22
 193 #define RC23 23
 194 #define RC24 24
 195 #define RC25 25
 196 #define RC26 26
 197 #define RC27 27
 198 #define RC28 28
 199 #define RC29 29
 200 #define RC30 30
 201 #define RC31 31
 202
 203 #define RC32 32
 204 #define RC33 33
 205 #define RC34 34
 206 #define RC35 35
 207 #define RC36 36
 208 #define RC37 37
 209 #define RC38 38
 210 #define RC39 39
 211 #define RC40 40
 212 #define RC41 41
 213 #define RC42 42
 214 #define RC43 43
 215 #define RC44 44
 216 #define RC45 45
 217 #define RC46 46
 218 #define RC47 47
 219 #define RC48 48
 220 #define RC49 49
 221 #define RC50 50
 222 #define RC51 51
 223 #define RC52 52
 224 #define RC53 53
 225 #define RC54 54
 226 #define RC55 55
 227 #define RC56 56
 228 #define RC57 57
 229 #define RC58 58
 230 #define RC59 59
 231 #define RC60 60
 232 #define RC61 61
 233 #define RC62 62
 234 #define RC63 63
 235
 236 #define SPD_UNDEFINED 0
 237 #define SPD_RDIMM 1
 238 #define SPD_UDIMM 2
 239 #define SPD_SODIMM 3
 240 #define SPD_MICRO_DIMM 4
 241 #define SPD_MINI_RDIMM 5
 242 #define SPD_MINI_UDIMM 6
 243
 244 #endif