2 * This file is part of msrtool.
4 * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 int intel_pentium3_early_probe(const struct targetdef
*target
, const struct cpuid_t
*id
) {
19 return ((VENDOR_INTEL
== id
->vendor
) &&
20 (0x6 == id
->family
) && (
26 const struct msrdef intel_pentium3_early_msrs
[] = {
27 {0x0, MSRTYPE_RDWR
, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
30 {0x1, MSRTYPE_RDWR
, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
33 {0x10, MSRTYPE_RDWR
, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
36 {0x17, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PLATFORM_ID", "", {
39 {0x1b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_APIC_BASE", "", {
42 {0x2a, MSRTYPE_RDWR
, MSR2(0,0), "EBL_CR_POWERON", "", {
45 {0x33, MSRTYPE_RDWR
, MSR2(0,0), "TEST_CTL", "", {
48 {0x88, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_D0", "", {
51 {0x89, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_D1", "", {
54 {0x8a, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_D2", "", {
57 {0x8b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
60 {0xc1, MSRTYPE_RDWR
, MSR2(0,0), "PERFCTR0", "", {
63 {0xc2, MSRTYPE_RDWR
, MSR2(0,0), "PERFCTR1", "", {
66 {0xfe, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRRCAP", "", {
69 {0x116, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_ADDR", "", {
72 {0x118, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_DECC", "", {
75 {0x119, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_CTL", "", {
78 {0x11b, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_BUSY", "", {
81 {0x11e, MSRTYPE_RDWR
, MSR2(0,0), "BBL_CR_CTL3", "", {
84 {0x174, MSRTYPE_RDWR
, MSR2(0,0), "IA32_SYSENTER_CS", "", {
87 {0x175, MSRTYPE_RDWR
, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
90 {0x176, MSRTYPE_RDWR
, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
93 {0x179, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCG_CAP", "", {
96 {0x17a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCG_STATUS", "", {
99 {0x17b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCG_CTL", "", {
102 {0x186, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", {
105 {0x187, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", {
108 {0x1d9, MSRTYPE_RDWR
, MSR2(0,0), "IA32_DEBUGCTL", "", {
111 {0x1db, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", {
114 {0x1dc, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", {
117 {0x1dd, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTINTFROMIP", "", {
120 {0x1de, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTINTTOIP", "", {
123 {0x1e0, MSRTYPE_RDWR
, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", {
126 {0x200, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
129 {0x201, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
132 {0x202, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
135 {0x203, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
138 {0x204, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
141 {0x205, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
144 {0x206, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
147 {0x207, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
150 {0x208, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
153 {0x209, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
156 {0x20a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
159 {0x20b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
162 {0x20c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
165 {0x20d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
168 {0x20e, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
171 {0x20f, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
174 {0x250, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
177 {0x258, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
180 {0x259, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
183 {0x268, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
186 {0x269, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
189 {0x26a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
192 {0x26b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
195 {0x26c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
198 {0x26d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
201 {0x26e, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
204 {0x26f, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
207 {0x2ff, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
210 {0x400, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC0_CTL", "", {
213 {0x401, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC0_STATUS", "", {
216 {0x402, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC0_ADDR", "", {
219 {0x404, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC1_CTL", "", {
222 {0x405, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC1_STATUS", "", {
225 {0x406, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC1_ADDR", "", {
228 {0x408, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC2_CTL", "", {
231 {0x409, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC2_STATUS", "", {
234 {0x40a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC2_ADDR", "", {
237 {0x40c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC3_CTL", "", {
240 {0x40d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC3_STATUS", "", {
243 {0x40e, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC3_ADDR", "", {
246 {0x410, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC4_CTL", "", {
249 {0x411, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC4_STATUS", "", {
252 {0x412, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC4_ADDR", "", {