src/soc/amd/stoneyridge/mca.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2018 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <cpu/x86/msr.h>
  17 #include <arch/acpi.h>
  18 #include <cpu/amd/amdfam15.h>
  19 #include <soc/cpu.h>
  20 #include <soc/northbridge.h>
  21 #include <console/console.h>
  22
  23 struct mca_bank {
  24         msr_t ctl;
  25         msr_t sts;
  26         msr_t addr;
  27         msr_t misc;
  28         msr_t cmask;
  29 };
  30
  31 static const char *const mca_bank_name[] = {
  32         "Load-store unit",
  33         "Instruction fetch unit",
  34         "Combined unit",
  35         "Reserved",
  36         "Northbridge",
  37         "Execution unit",
  38         "Floating point unit"
  39 };
  40
  41 void check_mca(void)
  42 {
  43         int i;
  44         msr_t cap;
  45         struct mca_bank mci;
  46         int num_banks;
  47
  48         cap = rdmsr(MCG_CAP);
  49         num_banks = cap.lo & MCA_BANKS_MASK;
  50
  51         if (is_warm_reset()) {
  52                 for (i = 0 ; i < num_banks ; i++) {
  53                         if (i == 3) /* Reserved in Family 15h */
  54                                 continue;
  55
  56                         mci.sts = rdmsr(MC0_STATUS + (i * 4));
  57                         if (mci.sts.hi || mci.sts.lo) {
  58                                 int core = cpuid_ebx(1) >> 24;
  59
  60                                 printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n",
  61                                                 core, i, mca_bank_name[i]);
  62
  63                                 printk(BIOS_WARNING, "   MC%d_STATUS =   %08x_%08x\n",
  64                                                 i, mci.sts.hi, mci.sts.lo);
  65                                 mci.addr = rdmsr(MC0_ADDR + (i * 4));
  66                                 printk(BIOS_WARNING, "   MC%d_ADDR =     %08x_%08x\n",
  67                                                 i, mci.addr.hi, mci.addr.lo);
  68                                 mci.misc = rdmsr(MC0_MISC + (i * 4));
  69                                 printk(BIOS_WARNING, "   MC%d_MISC =     %08x_%08x\n",
  70                                                 i, mci.misc.hi, mci.misc.lo);
  71                                 mci.ctl = rdmsr(MC0_CTL + (i * 4));
  72                                 printk(BIOS_WARNING, "   MC%d_CTL =      %08x_%08x\n",
  73                                                 i, mci.ctl.hi, mci.ctl.lo);
  74                                 mci.cmask = rdmsr(MC0_CTL_MASK + i);
  75                                 printk(BIOS_WARNING, "   MC%d_CTL_MASK = %08x_%08x\n",
  76                                                 i, mci.cmask.hi, mci.cmask.lo);
  77                         }
  78                 }
  79         }
  80
  81         /* zero the machine check error status registers */
  82         mci.sts.lo = 0;
  83         mci.sts.hi = 0;
  84         for (i = 0 ; i < num_banks ; i++)
  85                 wrmsr(MC0_STATUS + (i * 4), mci.sts);
  86 }