src/soc/intel/alderlake/systemagent.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 /*
   4  * This file is created based on Intel Alder Lake Processor SA Datasheet
   5  * Document number: 619503
   6  * Chapter number: 3
   7  */
   8
   9 #include <console/console.h>
  10 #include <device/device.h>
  11 #include <device/pci.h>
  12 #include <delay.h>
  13 #include <intelblocks/power_limit.h>
  14 #include <intelblocks/systemagent.h>
  15 #include <soc/iomap.h>
  16 #include <soc/soc_chip.h>
  17 #include <soc/systemagent.h>
  18
  19 /*
  20  * SoC implementation
  21  *
  22  * Add all known fixed memory ranges for Host Controller/Memory
  23  * controller.
  24  */
  25 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
  26 {
  27         static const struct sa_mmio_descriptor soc_fixed_resources[] = {
  28                 { PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
  29                                 "PCIEXBAR" },
  30                 { MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
  31                 { DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
  32                 { EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
  33                 { REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
  34                 { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
  35         };
  36
  37         sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
  38                         ARRAY_SIZE(soc_fixed_resources));
  39
  40         /* Add Vt-d resources if VT-d is enabled */
  41         if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
  42                 return;
  43
  44         sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
  45                         ARRAY_SIZE(soc_vtd_resources));
  46 }
  47
  48 /*
  49  * SoC implementation
  50  *
  51  * Perform System Agent Initialization during Ramstage phase.
  52  */
  53 void soc_systemagent_init(struct device *dev)
  54 {
  55         struct soc_power_limits_config *soc_config;
  56         struct device *sa;
  57         uint16_t sa_pci_id;
  58         u8 tdp;
  59         size_t i;
  60         config_t *config;
  61
  62         /* Enable Power Aware Interrupt Routing */
  63         enable_power_aware_intr();
  64
  65         /* Enable BIOS Reset CPL */
  66         enable_bios_reset_cpl();
  67
  68         /* Configure turbo power limits 1ms after reset complete bit */
  69         mdelay(1);
  70         config = config_of_soc();
  71
  72         /* Get System Agent PCI ID */
  73         sa = pcidev_path_on_root(SA_DEVFN_ROOT);
  74         sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
  75
  76         tdp = get_cpu_tdp();
  77
  78         /* Choose power limits configuration based on the CPU SA PCI ID and
  79          * CPU TDP value. */
  80         for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) {
  81                 if (sa_pci_id == cpuid_to_adl[i].cpu_id &&
  82                                 tdp == cpuid_to_adl[i].cpu_tdp) {
  83                         soc_config = &config->power_limits_config[cpuid_to_adl[i].limits];
  84                         set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
  85                         break;
  86                 }
  87         }
  88
  89         if (i == ARRAY_SIZE(cpuid_to_adl)) {
  90                 printk(BIOS_ERR, "unknown SA ID: 0x%4x, skipped power limits configuration.\n",
  91                         sa_pci_id);
  92                 return;
  93         }
  94 }
  95
  96 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
  97 {
  98         switch (capid0_a_ddrsz) {
  99         case 1:
 100                 return 8192;
 101         case 2:
 102                 return 4096;
 103         case 3:
 104                 return 2048;
 105         default:
 106                 return 65536;
 107         }
 108 }