src/soc/intel/alderlake/romstage/fsp_params.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <assert.h>
   4 #include <console/console.h>
   5 #include <cpu/x86/msr.h>
   6 #include <cpu/intel/cpu_ids.h>
   7 #include <device/device.h>
   8 #include <fsp/util.h>
   9 #include <intelblocks/cpulib.h>
  10 #include <intelblocks/pcie_rp.h>
  11 #include <soc/gpio_soc_defs.h>
  12 #include <soc/iomap.h>
  13 #include <soc/msr.h>
  14 #include <soc/pci_devs.h>
  15 #include <soc/pcie.h>
  16 #include <soc/romstage.h>
  17 #include <soc/soc_chip.h>
  18 #include <string.h>
  19
  20 #define FSP_CLK_NOTUSED                 0xFF
  21 #define FSP_CLK_LAN                     0x70
  22 #define FSP_CLK_FREE_RUNNING            0x80
  23
  24 #define CPU_PCIE_BASE                   0x40
  25
  26 enum vtd_base_index_type {
  27         VTD_GFX,
  28         VTD_IPU,
  29         VTD_VTVCO,
  30         VTD_TBT0,
  31         VTD_TBT1,
  32         VTD_TBT2,
  33         VTD_TBT3,
  34 };
  35
  36 static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
  37 {
  38         assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU);
  39
  40         if (type == PCIE_RP_PCH)
  41                 return rp_number;
  42         else // type == PCIE_RP_CPU
  43                 return CPU_PCIE_BASE + rp_number;
  44 }
  45
  46 static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type,
  47                         const struct pcie_rp_config *cfg, size_t cfg_count)
  48 {
  49         size_t i;
  50         /* bitmask to save the status of clkreq assignment */
  51         static unsigned int clk_req_mapping = 0;
  52
  53         for (i = 0; i < cfg_count; i++) {
  54                 if (!(en_mask & BIT(i)))
  55                         continue;
  56                 if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
  57                         continue;
  58                 if (clk_req_mapping & (1 << cfg[i].clk_req))
  59                         printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
  60                                 , cfg[i].clk_req);
  61                 if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
  62                         m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
  63                         clk_req_mapping |= 1 << cfg[i].clk_req;
  64                 }
  65                 m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i);
  66         }
  67 }
  68
  69 static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
  70                 const struct soc_intel_alderlake_config *config)
  71 {
  72         /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */
  73         unsigned int i;
  74
  75         for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
  76                 if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
  77                         m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
  78                 else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
  79                         m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;
  80                 else
  81                         m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED;
  82                 m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
  83         }
  84
  85         /* Configure PCH PCIE ports */
  86         m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
  87         pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp,
  88                         CONFIG_MAX_PCH_ROOT_PORTS);
  89
  90         /* Configure CPU PCIE ports */
  91         m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table());
  92         pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp,
  93                         CONFIG_MAX_CPU_ROOT_PORTS);
  94 }
  95
  96 static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
  97                 const struct soc_intel_alderlake_config *config)
  98 {
  99         unsigned int i;
 100         const struct ddi_port_upds {
 101                 uint8_t *ddc;
 102                 uint8_t *hpd;
 103         } ddi_port_upds[] = {
 104                 [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd},
 105                 [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd},
 106                 [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd},
 107                 [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd},
 108                 [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd},
 109                 [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd},
 110                 [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd},
 111         };
 112         m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
 113         if (m_cfg->InternalGfx) {
 114                 /* IGD is enabled, set IGD stolen size to 60MB. */
 115                 m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
 116                 /* DP port config */
 117                 m_cfg->DdiPortAConfig = config->DdiPortAConfig;
 118                 m_cfg->DdiPortBConfig = config->DdiPortBConfig;
 119                 for  (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
 120                         *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] &
 121                                                                 DDI_ENABLE_DDC);
 122                         *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] &
 123                                                                 DDI_ENABLE_HPD);
 124                 }
 125         } else {
 126                 /* IGD is disabled, skip IGD init in FSP. */
 127                 m_cfg->IgdDvmt50PreAlloc = 0;
 128                 /* DP port config */
 129                 m_cfg->DdiPortAConfig = 0;
 130                 m_cfg->DdiPortBConfig = 0;
 131                 for  (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) {
 132                         *ddi_port_upds[i].ddc = 0;
 133                         *ddi_port_upds[i].hpd = 0;
 134                 }
 135         }
 136 }
 137 static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 138                 const struct soc_intel_alderlake_config *config)
 139 {
 140         m_cfg->SaGv = config->SaGv;
 141         m_cfg->RMT = config->RMT;
 142         if (config->MaxDramSpeed)
 143                 m_cfg->DdrFreqLimit = config->MaxDramSpeed;
 144 }
 145
 146 static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,
 147                 const struct soc_intel_alderlake_config *config)
 148 {
 149         m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
 150         /* CpuRatio Settings */
 151         if (config->cpu_ratio_override)
 152                 m_cfg->CpuRatio = config->cpu_ratio_override;
 153         else
 154                 /* Set CpuRatio to match existing MSR value */
 155                 m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
 156
 157         m_cfg->PrmrrSize = get_valid_prmrr_size();
 158         m_cfg->EnableC6Dram = config->enable_c6dram;
 159         /* Enable Hyper Threading */
 160         m_cfg->HyperThreading = 1;
 161 }
 162
 163 static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg,
 164                 const struct soc_intel_alderlake_config *config)
 165 {
 166         /* Disable BIOS Guard */
 167         m_cfg->BiosGuard = 0;
 168         m_cfg->TmeEnable = CONFIG(INTEL_TME);
 169 }
 170
 171 static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg,
 172                 const struct soc_intel_alderlake_config *config)
 173 {
 174         /* UART Debug Log */
 175         m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
 176                         DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
 177         if (CONFIG(DRIVERS_UART_8250IO))
 178                 m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
 179         m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
 180         m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
 181 }
 182
 183 static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg,
 184                 const struct soc_intel_alderlake_config *config)
 185 {
 186         /* Image clock: disable all clocks for bypassing FSP pin mux */
 187         memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
 188         /* IPU */
 189         m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
 190 }
 191
 192 static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg,
 193                 const struct soc_intel_alderlake_config *config)
 194 {
 195         m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
 196 }
 197
 198 static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg,
 199                 const struct soc_intel_alderlake_config *config)
 200 {
 201         /* Disable Lock PCU Thermal Management registers */
 202         m_cfg->LockPTMregs = 0;
 203
 204         /* Skip CPU replacement check */
 205         m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
 206
 207         /* Skip GPIO configuration from FSP */
 208         m_cfg->GpioOverride = 0x1;
 209
 210         /* CNVi DDR RFI Mitigation */
 211         m_cfg->CnviDdrRfim = config->CnviDdrRfim;
 212 }
 213
 214 static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg,
 215                 const struct soc_intel_alderlake_config *config)
 216 {
 217         /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
 218         m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
 219         m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
 220         m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
 221         m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
 222         m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable;
 223         /*
 224          * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
 225          * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
 226          * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
 227          * configuration for audio pads.
 228          */
 229         m_cfg->PchHdaAudioLinkHdaEnable = 0;
 230         memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
 231         memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
 232         memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
 233 }
 234
 235 static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg,
 236                 const struct soc_intel_alderlake_config *config)
 237 {
 238         m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH);
 239 }
 240
 241 static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg,
 242                 const struct soc_intel_alderlake_config *config)
 243 {
 244         /* Tcss USB */
 245         m_cfg->TcssXhciEn = is_devfn_enabled(SA_DEVFN_TCSS_XHCI);
 246         m_cfg->TcssXdciEn = is_devfn_enabled(SA_DEVFN_TCSS_XDCI);
 247
 248         /* TCSS DMA */
 249         m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0);
 250         m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1);
 251 }
 252
 253 static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg,
 254                 const struct soc_intel_alderlake_config *config)
 255 {
 256         m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0);
 257         m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1);
 258         m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2);
 259         m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3);
 260 }
 261
 262 static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg,
 263                 const struct soc_intel_alderlake_config *config)
 264 {
 265         const uint32_t cpuid = cpu_get_cpuid();
 266
 267         /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */
 268         if (cpuid == CPUID_ALDERLAKE_A0 || cpuid == CPUID_ALDERLAKE_A1) {
 269                 m_cfg->VtdDisable = 1;
 270                 return;
 271         }
 272
 273         m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS;
 274         m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS;
 275         m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS;
 276
 277         m_cfg->VtdDisable = 0;
 278         m_cfg->VtdIopEnable = !m_cfg->VtdDisable;
 279         m_cfg->VtdIgdEnable = m_cfg->InternalGfx;
 280         m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable;
 281
 282         if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) {
 283                 m_cfg->VtdIgdEnable = 0;
 284                 printk(BIOS_ERR, "Requested IGD VT-d, but GFXVT_BASE_ADDRESS is 0\n");
 285         }
 286
 287         if (m_cfg->VtdIpuEnable && m_cfg->VtdBaseAddress[VTD_IPU] == 0) {
 288                 m_cfg->VtdIpuEnable = 0;
 289                 printk(BIOS_ERR, "Requested IPU VT-d, but IPUVT_BASE_ADDRESS is 0\n");
 290         }
 291
 292         if (!m_cfg->VtdDisable && m_cfg->VtdBaseAddress[VTD_VTVCO] == 0) {
 293                 m_cfg->VtdDisable = 1;
 294                 printk(BIOS_ERR, "Requested VT-d, but VTVCO_BASE_ADDRESS is 0\n");
 295         }
 296
 297         if (m_cfg->TcssDma0En || m_cfg->TcssDma1En)
 298                 m_cfg->VtdItbtEnable = 1;
 299
 300         if (m_cfg->TcssItbtPcie0En)
 301                 m_cfg->VtdBaseAddress[VTD_TBT0] = TBT0_BASE_ADDRESS;
 302
 303         if (m_cfg->TcssItbtPcie1En)
 304                 m_cfg->VtdBaseAddress[VTD_TBT1] = TBT1_BASE_ADDRESS;
 305
 306         if (m_cfg->TcssItbtPcie2En)
 307                 m_cfg->VtdBaseAddress[VTD_TBT2] = TBT2_BASE_ADDRESS;
 308
 309         if (m_cfg->TcssItbtPcie3En)
 310                 m_cfg->VtdBaseAddress[VTD_TBT3] = TBT3_BASE_ADDRESS;
 311
 312         /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
 313         m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
 314 }
 315
 316 static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg,
 317                 const struct soc_intel_alderlake_config *config)
 318 {
 319         /* Set MRC debug level */
 320         m_cfg->SerialDebugMrcLevel = fsp_map_console_log_level();
 321
 322         /* Set debug probe type */
 323         m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
 324
 325         /* CrashLog config */
 326         m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT);
 327         m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice;
 328 }
 329
 330 static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 331                 const struct soc_intel_alderlake_config *config)
 332 {
 333         const void (*fill_fspm_params[])(FSP_M_CONFIG *m_cfg,
 334                         const struct soc_intel_alderlake_config *config) = {
 335                 fill_fspm_igd_params,
 336                 fill_fspm_mrc_params,
 337                 fill_fspm_cpu_params,
 338                 fill_fspm_security_params,
 339                 fill_fspm_uart_params,
 340                 fill_fspm_ipu_params,
 341                 fill_fspm_smbus_params,
 342                 fill_fspm_misc_params,
 343                 fill_fspm_audio_params,
 344                 fill_fspm_pcie_rp_params,
 345                 fill_fspm_ish_params,
 346                 fill_fspm_tcss_params,
 347                 fill_fspm_usb4_params,
 348                 fill_fspm_vtd_params,
 349                 fill_fspm_trace_params,
 350         };
 351
 352         for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++)
 353                 fill_fspm_params[i](m_cfg, config);
 354 }
 355
 356 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 357 {
 358         const struct soc_intel_alderlake_config *config;
 359         FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 360
 361         config = config_of_soc();
 362
 363         soc_memory_init_params(m_cfg, config);
 364         mainboard_memory_init_params(m_cfg);
 365 }
 366
 367 __weak void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
 368 {
 369         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 370 }