util/bincfg/ddr4_unbuffered_spd_512.spec

   1 # 4_01_02_AnnexL-R25_SPD_for_DDR4_SDRAM_Release_3_Sep2015.pdf
   2 #
   3 # JEDEC Standard No. 21-C
   4 # Page 4.1.2.12.3 – 1
   5 # Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules
   6 # DDR4 SPD Document Release 3
   7 # UDIMM Revision 1.1
   8 # RDIMM Revision 1.1
   9 # LRDIMM Revision 1.1
  10 # NVDIMM Revision 1.0
  11
  12 {
  13         # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device /
  14         #         CRC Coverage
  15         "SPD_Bytes_Used"                                                : 4,
  16         "SPD_Bytes_Total"                                               : 3,
  17         "CRC_Coverage"                                                  : 1,
  18
  19         # Byte 1: SPD Revision
  20         "SPD_Revision"                                                  : 8,
  21
  22         # Byte 2: Key Byte / DRAM Device Type
  23         "DRAM_Device_Type"                                              : 8,
  24
  25         # Byte 3: Key Byte / Module Type
  26         "Base_Module_Type"                                              : 4,
  27         "Hybrid_Media"                                                  : 3,
  28         "Is_Hybrid"                                                     : 1,
  29
  30         # Byte 4: SDRAM Density and Banks
  31         "SDRAM_Capacity"                                                : 4,
  32         "Bank_Address_Bits"                                             : 2,
  33         "Bank_Group_Bits"                                               : 2,
  34
  35         # Byte 5: SDRAM Addressing
  36         "Column_Address_Bits"                                           : 3,
  37         "Row_Address_Bits"                                              : 3,
  38         "Byte_5_reserved"                                               : 2,
  39
  40         # Byte 6:  SDRAM Package Type
  41         "Signal_Loading"                                                : 2,
  42         "Byte_6_reserved"                                               : 2,
  43         "Die_Count"                                                     : 3,
  44         "SDRAM_Package_Type"                                            : 1,
  45
  46         # Byte 7:  SDRAM Optional Features
  47         "Maximum_Activate_Count"                                        : 4,
  48         "Maximum_Activate_Window"                                       : 2,
  49         "Byte_7_reserved"                                               : 2,
  50
  51         # Byte 8: SDRAM Thermal and Refresh Options
  52         "Byte_8_reserved"                                               : 8,
  53
  54         # Byte 9:  Other SDRAM Optional Features
  55         "Byte_9_reserved"                                               : 5,
  56         "Soft_PPR"                                                      : 1,
  57         "Post_Package_Repair"                                           : 2,
  58
  59         # Byte 10: Secondary SDRAM Package Type
  60         "Secondary_Signal_Loading"                                      : 2,
  61         "Secondary_DRAM_Densityt_Ratio"                                 : 2,
  62         "Secondary_Die_Count"                                           : 3,
  63         "Secondary_SDRAM_Package_Type"                                  : 1,
  64
  65         # Byte 11:  Module Nominal Voltage, VDD
  66         "DRAM_VDD_1_2_V"                                                : 2,
  67         "Byte_11_reserved"                                              : 6,
  68
  69         # Byte 12: Module Organization
  70         "SDRAM_Device_Width"                                            : 3,
  71         "Number_of_Package_Ranks_per_DIMM"                              : 3,
  72         "Rank_Mix"                                                      : 1,
  73         "Byte_12_reserved"                                              : 1,
  74
  75         # Byte 13: Module Memory Bus Width
  76         "Primary_bus_width_in_bits"                                     : 3,
  77         "Bus_width_extension_in_bits"                                   : 2,
  78         "Byte_13_reserved"                                              : 3,
  79
  80         # Byte 14: Module Thermal Sensor
  81         "Byte_14_reserved"                                              : 7,
  82         "Thermal_Sensor"                                                : 1,
  83
  84         # Byte 15:  Extended Module Type
  85         "Extended_Base_Module_Type"                                     : 4,
  86         "Byte_15_reserved"                                              : 4,
  87
  88         # Byte 16: Reserved
  89         "Byte_16_reserved"                                              : 8,
  90
  91         # Byte 17: Timebases
  92         "Fine_Timebase"                                                 : 2,
  93         "Medium_Timebase"                                               : 2,
  94         "Byte_17_reserved"                                              : 4,
  95
  96         # Byte 18:  SDRAM Minimum Cycle Time (tCKAVGmin)
  97         "tCKAVGmin"                                                     : 8,
  98
  99         # Byte 19:  SDRAM Maximum Cycle Time (tCKAVGmax)
 100         "tCKAVGmax"                                                     : 8,
 101
 102         # Bytes 20 - 23: CAS Latencies Supported
 103         "CL_7_Supported"                                                : 1,
 104         "CL_8_Supported"                                                : 1,
 105         "CL_9_Supported"                                                : 1,
 106         "CL_10_Supported"                                               : 1,
 107         "CL_11_Supported"                                               : 1,
 108         "CL_12_Supported"                                               : 1,
 109         "CL_13_Supported"                                               : 1,
 110         "CL_14_Supported"                                               : 1,
 111
 112         "CL_15_Supported"                                               : 1,
 113         "CL_16_Supported"                                               : 1,
 114         "CL_17_Supported"                                               : 1,
 115         "CL_18_Supported"                                               : 1,
 116         "CL_19_Supported"                                               : 1,
 117         "CL_20_Supported"                                               : 1,
 118         "CL_21_Supported"                                               : 1,
 119         "CL_22_Supported"                                               : 1,
 120
 121         "CL_23_Supported"                                               : 1,
 122         "CL_24_Supported"                                               : 1,
 123         "CL_25_Supported"                                               : 1,
 124         "CL_26_Supported"                                               : 1,
 125         "CL_27_Supported"                                               : 1,
 126         "CL_28_Supported"                                               : 1,
 127         "CL_29_Supported"                                               : 1,
 128         "CL_30_Supported"                                               : 1,
 129
 130         "CL_31_Supported"                                               : 1,
 131         "CL_32_Supported"                                               : 1,
 132         "CL_33_Supported"                                               : 1,
 133         "CL_34_Supported"                                               : 1,
 134         "CL_35_Supported"                                               : 1,
 135         "CL_36_Supported"                                               : 1,
 136         "Byte_23_reserved"                                              : 1,
 137         "CL_range"                                                      : 1,
 138
 139         # Byte 24: Minimum CAS Latency Time (tAAmin)
 140         "tAAmin"                                                        : 8,
 141
 142         # Byte 25: Minimum RAS to CAS Delay Time (tRCDmin)
 143         "tRCDmin"                                                       : 8,
 144
 145         # Byte 26: Minimum Row Precharge Delay Time (tRPmin)
 146         "tRPmin"                                                        : 8,
 147
 148         # Bytes 27 - 29: Minimum Active to Precharge Delay Time (tRASmin)
 149         #               / Minimum Active to Active/Refresh Delay Time
 150         #               (tRCmin)
 151         "tRASmin_MSN"                                                   : 4,
 152         "tRCmin_MSN"                                                    : 4,
 153         "tRASmin_LSB"                                                   : 8,
 154         "tRCmin_LSB"                                                    : 8,
 155
 156         # Bytes 30 - 31: Minimum Refresh Recovery Delay Time (tRFC1min)
 157         "tRFC1min_LSB"                                                  : 8,
 158         "tRFC1min_MSB"                                                  : 8,
 159
 160         # Bytes 32 - 33: Minimum Refresh Recovery Delay Time (tRFC2min)
 161         "tRFC2min_LSB"                                                  : 8,
 162         "tRFC2min_MSB"                                                  : 8,
 163
 164         # Bytes 34 - 35: Minimum Refresh Recovery Delay Time (tRFC4min)
 165         "tRFC4min_LSB"                                                  : 8,
 166         "tRFC4min_MSB"                                                  : 8,
 167
 168         # Byte 36 - 37:  Minimum Four Activate Window Delay Time
 169         #               (tFAWmin)
 170         "tFAWmin_MSN"                                                   : 4,
 171         "Byte_36_reserved"                                              : 4,
 172         "tFAWmin_LSB"                                                   : 8,
 173
 174         # Bytes 38: Minimum Activate to Activate Delay Time (tRRD_Smin),
 175         #                different bank group
 176         "tRRD_Smin"                                                     : 8,
 177
 178         # Byte 39: Minimum Activate to Activate Delay Time (tRRD_Lmin),
 179         #          same bank group
 180         "tRRD_Lmin"                                                     : 8,
 181
 182         # Byte 40: Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank
 183         #          group
 184         "tCCD_Lmin"                                                     : 8,
 185
 186         # Byte 41 - 42: Minimum Write Recovery Time (tWRmin)
 187         "tWRmin_MSN"                                                    : 4,
 188         "Byte_41_reserved"                                              : 4,
 189         "tWRmin_MSB"                                                    : 8,
 190
 191         # Byte 43-45: Minimum Write to Read Time (tWTR_Smin),
 192         #             different bank group / Minimum Write to Read Time
 193         #             (tWTR_Lmin), same bank group
 194         "tWTR_Smin_MSN"                                                 : 4,
 195         "tWTR_Lmin_MSN"                                                 : 4,
 196         "tWTR_Smin_LSB"                                                 : 8,
 197         "tWTR_Lmin_LSB"                                                 : 8,
 198
 199         # Byte 46~59: Reserved, Base Configuration Section
 200         "Byte_46_59_reserved" [14]                                      : 8,
 201
 202         # Byte 60: Connector to SDRAM Bit Mapping (DQ0-3)
 203         "DQ0_3"                                                         : 8,
 204         # Byte 61: Connector to SDRAM Bit Mapping (DQ4-7)
 205         "DQ4_7"                                                         : 8,
 206
 207         # Byte 62: Connector to SDRAM Bit Mapping (DQ8-11)
 208         "DQ8_11"                                                        : 8,
 209
 210         # Byte 63: Connector to SDRAM Bit Mapping (DQ12-15)
 211         "DQ12_15"                                                       : 8,
 212
 213         # Byte 64: Connector to SDRAM Bit Mapping (DQ16-19)
 214         "DQ16_19"                                                       : 8,
 215
 216         # Byte 65: Connector to SDRAM Bit Mapping (DQ20-23)
 217         "DQ20_23"                                                       : 8,
 218
 219         # Byte 66: Connector to SDRAM Bit Mapping (DQ24-27)
 220         "DQ24_27"                                                       : 8,
 221
 222         # Byte 67: Connector to SDRAM Bit Mapping (DQ28-31)
 223         "DQ28_31"                                                       : 8,
 224
 225         # Byte 68: Connector to SDRAM Bit Mapping (CB0-3)
 226         "CB0_3"                                                         : 8,
 227
 228         # Byte 69: Connector to SDRAM Bit Mapping (CB4-7)
 229         "CB4_7"                                                         : 8,
 230
 231         # Byte 70: Connector to SDRAM Bit Mapping (DQ32-35)
 232         "DQ32_35"                                                       : 8,
 233
 234         # Byte 71: Connector to SDRAM Bit Mapping (DQ36-39)
 235         "DQ36_39"                                                       : 8,
 236
 237         # Byte 72: Connector to SDRAM Bit Mapping (DQ40-43)
 238         "DQ40_43"                                                       : 8,
 239
 240         # Byte 73: Connector to SDRAM Bit Mapping (DQ44-47)
 241         "DQ44_47"                                                       : 8,
 242
 243         # Byte 74: Connector to SDRAM Bit Mapping (DQ48-51)
 244         "DQ48_51"                                                       : 8,
 245
 246         # Byte 75: Connector to SDRAM Bit Mapping (DQ52-55)
 247         "DQ52_55"                                                       : 8,
 248
 249         # Byte 76: Connector to SDRAM Bit Mapping (DQ56-59)
 250         "DQ56_59"                                                       : 8,
 251
 252         # Byte 77: Connector to SDRAM Bit Mapping (DQ60-63)
 253         "DQ60_63"                                                       : 8,
 254
 255         # Bytes 78~116: Reserved, Base Configuration Section
 256         # Must be coded as 0x00
 257         "Byte_78_116_reserved" [39]                                     : 8,
 258
 259         # Byte 117: Fine Offset for Minimum CAS to CAS Delay Time
 260         #           (tCCD_Lmin), same bank group
 261         "tCCD_Lmin_Fine_Offset"                                         : 8,
 262
 263         # Byte 118: Fine Offset for Minimum Activate to Activate Delay
 264         #           Time (tRRD_Lmin), same bank group
 265         "tRRD_Lmin_Fine_Offset"                                         : 8,
 266
 267         # Byte 119:  Fine Offset for Minimum Activate to Activate Delay
 268         #            Time (tRRD_Smin), different bank group
 269         "tRRD_Smin_Fine_Offset"                                         : 8,
 270
 271         # Byte 120: Fine Offset for Minimum Active to Active/Refresh
 272         #           Delay Time (tRCmin)
 273         "tRCmin_Fine_Offset"                                            : 8,
 274
 275         # Byte 121: Fine Offset for Minimum Row Precharge Delay
 276         #           Time (tRPmin)
 277         "tRPmin_Fine_Offset"                                            : 8,
 278
 279         # Byte 122: Fine Offset for Minimum RAS to CAS Delay
 280         #           Time (tRCDmin)
 281         "tRCDmin_Fine_Offset"                                           : 8,
 282
 283         # Byte 123: Fine Offset for Minimum CAS Latency Time (tAAmin)
 284         "tAAmin_Fine_Offset"                                            : 8,
 285
 286         # Byte 124: Fine Offset for SDRAM Maximum Cycle Time
 287         #           (tCKAVGmax)
 288         "tCKAVGmax_Fine_Offset"                                         : 8,
 289
 290         # Byte 125: Fine Offset for SDRAM Minimum Cycle Time
 291         #           (tCKAVGmin)
 292         "tCKAVGmin_Fine_Offset"                                         : 8,
 293
 294         # Byte 126 - 127: Cyclical Redundancy Code (CRC) for
 295         #                 Base Configuration Section
 296         "CRC_Base_Configuration"                                        : 16,
 297
 298 # Standard Module Parameters - Overlay Bytes 128~191
 299 #  Module Specific Bytes for Unbuffered Memory Module Types
 300
 301         # Byte 128: Raw Card Extension, Module Nominal Height
 302         "Module_Nominal_Height_Max"                                     : 5,
 303         "Raw_Card_Extension"                                            : 3,
 304
 305         # Byte 129: Module Maximum Thickness
 306         "Module_Maximum_Thickness_Front"                                : 4,
 307         "Module_Maximum_Thickness_Back"                                 : 4,
 308
 309         # Byte 130: Reference Raw Card Used
 310         "Reference_Raw_Card"                                            : 5,
 311         "Reference_Raw_Card_Revision"                                   : 2,
 312         "Reference_Raw_Card_Extension"                                  : 1,
 313
 314         # Byte 131: Address Mapping from Edge Connector to DRAM
 315         "Rank_1_Mapping"                                                : 1,
 316         "Byte_131_reserved"                                             : 7,
 317
 318         # Byte 132 - 191: Reserved
 319         "Byte_132_191_reserved" [60]                                    : 8,
 320
 321 # Unused
 322         # Byte 192 - 253: Unused
 323         "Byte_192_255_unused" [62]                                      : 8,
 324
 325         # Byte 254 - 255: CRC for SPD Block 1
 326         "CRC_SPD_Block_1"                                               : 16,
 327
 328 # Reserved
 329         # Byte 256 - 319: Reserved
 330         "Byte_256_319_reserved" [64]                                    : 8,
 331
 332 # End User Programmable
 333         # Byte 384 - 511
 334         "End_User_Programmable" [128]                                   : 8
 335 }