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PCI subsystem: Drop parameter max from scan_bus
[coreboot.git] / src / northbridge / amd / amdk8 / northbridge.c
blob63a25abff3d301dc113c811a4b8d9b5f2cc47712
1 /* This should be done by Eric
2 2004.12 yhlu add dual core support
3 2005.01 yhlu add support move apic before pci_domain in MB devicetree.cb
4 2005.02 yhlu add e0 memory hole support
5 2005.11 yhlu add put sb ht chain on bus 0
6 */
7
8 #include <console/console.h>
9 #include <arch/io.h>
10 #include <stdint.h>
11 #include <device/device.h>
12 #include <device/pci.h>
13 #include <device/pci_ids.h>
14 #include <device/hypertransport.h>
15 #include <stdlib.h>
16 #include <string.h>
17 #include <lib.h>
18 #include <cpu/cpu.h>
19 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
20 #include <arch/acpi.h>
21 #include "acpi.h"
22 #endif
23
24 #include <cpu/x86/lapic.h>
25 #include <cpu/amd/mtrr.h>
26
27 #include <cpu/amd/multicore.h>
28 #if CONFIG_LOGICAL_CPUS
29 #include <pc80/mc146818rtc.h>
30 #endif
31
32 #include "northbridge.h"
33
34 #include "amdk8.h"
35
36 #include <cpu/amd/model_fxx_rev.h>
37
38 #include <cpu/amd/amdk8_sysconf.h>
39
40 struct amdk8_sysconf_t sysconf;
41
42 #define MAX_FX_DEVS 8
43 static device_t __f0_dev[MAX_FX_DEVS];
44 static device_t __f1_dev[MAX_FX_DEVS];
45 static unsigned fx_devs=0;
46
47 static void get_fx_devs(void)
48 {
49 int i;
50 for(i = 0; i < MAX_FX_DEVS; i++) {
51 __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
52 __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
53 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
54 fx_devs = i+1;
55 }
56 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
57 die("Cannot find 0:0x18.[0|1]\n");
58 }
59 }
60
61 static u32 f1_read_config32(unsigned reg)
62 {
63 if (fx_devs == 0)
64 get_fx_devs();
65 return pci_read_config32(__f1_dev[0], reg);
66 }
67
68 static void f1_write_config32(unsigned reg, u32 value)
69 {
70 int i;
71 if (fx_devs == 0)
72 get_fx_devs();
73 for(i = 0; i < fx_devs; i++) {
74 device_t dev;
75 dev = __f1_dev[i];
76 if (dev && dev->enabled) {
77 pci_write_config32(dev, reg, value);
78 }
79 }
80 }
81
82 static bool is_non_coherent_link(struct device *dev, struct bus *link)
83 {
84 u32 link_type;
85 do {
86 link_type = pci_read_config32(dev, link->cap + 0x18);
87 } while (link_type & ConnectionPending);
88
89 if (!(link_type & LinkConnected))
90 return false;
91
92 do {
93 link_type = pci_read_config32(dev, link->cap + 0x18);
94 } while (!(link_type & InitComplete));
95
96 return !!(link_type & NonCoherent);
97 }
98
99 static u32 amdk8_nodeid(device_t dev)
100 {
101 return (dev->path.pci.devfn >> 3) - 0x18;
102 }
103
104 static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink,
105 u32 max)
106 {
107 int i;
108 unsigned int next_unitid;
109 u32 busses, config_busses;
110 u32 free_reg, config_reg;
111 u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
112 u32 max_bus;
113 u32 min_bus;
114 u32 max_devfn;
115
116 link->cap = 0x80 + (link->link_num * 0x20);
117 if (!is_non_coherent_link(dev, link))
118 return max;
119
120 /* See if there is an available configuration space mapping
121 * register in function 1.
122 */
123 free_reg = 0;
124 for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
125 u32 config;
126 config = f1_read_config32(config_reg);
127 if (!free_reg && ((config & 3) == 0)) {
128 free_reg = config_reg;
129 continue;
130 }
131 if (((config & 3) == 3) &&
132 (((config >> 4) & 7) == nodeid) &&
133 (((config >> 8) & 3) == link->link_num)) {
134 break;
135 }
136 }
137 if (free_reg && (config_reg > 0xec)) {
138 config_reg = free_reg;
139 }
140 /* If we can't find an available configuration space mapping
141 * register skip this bus
142 */
143 if (config_reg > 0xec) {
144 return max;
145 }
146
147 /* Set up the primary, secondary and subordinate bus numbers.
148 * We have no idea how many busses are behind this bridge yet,
149 * so we set the subordinate bus number to 0xff for the moment.
150 */
151 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
152 // first chain will on bus 0
153 if(is_sblink) { // actually max is 0 here
154 min_bus = max;
155 }
156 #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
157 // second chain will be on 0x40, third 0x80, forth 0xc0
158 else {
159 min_bus = ((max>>6) + 1) * 0x40;
160 }
161 max = min_bus;
162 #else
163 //other ...
164 else {
165 min_bus = ++max;
166 }
167 #endif
168 #else
169 min_bus = ++max;
170 #endif
171 max_bus = 0xff;
172
173 link->secondary = min_bus;
174 link->subordinate = link->secondary;
175
176 /* Read the existing primary/secondary/subordinate bus
177 * number configuration.
178 */
179 busses = pci_read_config32(dev, link->cap + 0x14);
180 config_busses = f1_read_config32(config_reg);
181
182 /* Configure the bus numbers for this bridge: the configuration
183 * transactions will not be propagates by the bridge if it is
184 * not correctly configured
185 */
186 busses &= 0xff000000;
187 busses |= (((unsigned int)(dev->bus->secondary) << 0) |
188 ((unsigned int)(link->secondary) << 8) |
189 (max_bus << 16));
190 pci_write_config32(dev, link->cap + 0x14, busses);
191
192 config_busses &= 0x000fc88;
193 config_busses |=
194 (3 << 0) | /* rw enable, no device compare */
195 (( nodeid & 7) << 4) |
196 ((link->link_num & 3) << 8) |
197 ((link->secondary) << 16) |
198 (max_bus << 24);
199 f1_write_config32(config_reg, config_busses);
200
201 /* Now we can scan all of the subordinate busses i.e. the
202 * chain on the hypertranport link
203 */
204 for(i=0;i<4;i++) {
205 ht_unitid_base[i] = 0x20;
206 }
207
208 if (min_bus == 0)
209 max_devfn = (0x17<<3) | 7;
210 else
211 max_devfn = (0x1f<<3) | 7;
212
213 next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink));
214
215 /* Now that nothing is overlapping it is safe to scan the children. */
216 pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7);
217
218 /* We know the number of busses behind this bridge. Set the
219 * subordinate bus number to it's real value
220 */
221 busses = (busses & 0xff00ffff) |
222 ((unsigned int) (link->subordinate) << 16);
223 pci_write_config32(dev, link->cap + 0x14, busses);
224
225 config_busses = (config_busses & 0x00ffffff) |
226 (link->subordinate << 24);
227 f1_write_config32(config_reg, config_busses);
228
229 {
230 // use config_reg and ht_unitid_base to update hcdn_reg
231 int index;
232 u32 temp = 0;
233 index = (config_reg-0xe0) >> 2;
234 for(i=0;i<4;i++) {
235 temp |= (ht_unitid_base[i] & 0xff) << (i*8);
236 }
237
238 sysconf.hcdn_reg[index] = temp;
239
240 }
241 return link->subordinate;
242 }
243
244 static unsigned amdk8_scan_chains(device_t dev, unsigned unused)
245 {
246 unsigned nodeid;
247 struct bus *link;
248 unsigned sblink = 0;
249 unsigned int max = dev->bus->subordinate;
250
251 nodeid = amdk8_nodeid(dev);
252 if (nodeid == 0)
253 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
254
255 // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
256 for (link = dev->link_list; link; link = link->next) {
257 bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
258 if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
259 max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max);
260 }
261
262 for (link = dev->link_list; link; link = link->next) {
263 bool is_sblink = (nodeid == 0) && (link->link_num == sblink);
264 if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)
265 continue;
266
267 max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max);
268 }
269
270 dev->bus->subordinate = max;
271
272 return unused;
273 }
274
275
276 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
277 unsigned goal_link)
278 {
279 struct resource *res;
280 unsigned nodeid, link = 0;
281 int result;
282 res = 0;
283 for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
284 device_t dev;
285 dev = __f0_dev[nodeid];
286 if (!dev)
287 continue;
288 for(link = 0; !res && (link < 3); link++) {
289 res = probe_resource(dev, IOINDEX(0x100 + reg, link));
290 }
291 }
292 result = 2;
293 if (res) {
294 result = 0;
295 if ( (goal_link == (link - 1)) &&
296 (goal_nodeid == (nodeid - 1)) &&
297 (res->flags <= 1)) {
298 result = 1;
299 }
300 }
301 return result;
302 }
303
304 static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
305 unsigned min, unsigned max)
306 {
307 unsigned resource;
308 unsigned free_reg, reg;
309 resource = 0;
310 free_reg = 0;
311 for(reg = min; reg <= max; reg += 0x8) {
312 int result;
313 result = reg_useable(reg, dev, nodeid, link);
314 if (result == 1) {
315 /* I have been allocated this one */
316 break;
317 }
318 else if (result > 1) {
319 /* I have a free register pair */
320 free_reg = reg;
321 }
322 }
323 if (reg > max) {
324 reg = free_reg;
325 }
326 if (reg > 0) {
327 resource = IOINDEX(0x100 + reg, link);
328 }
329 return resource;
330 }
331
332 static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
333 {
334 return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
335 }
336
337 static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
338 {
339 return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
340 }
341
342 static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
343 {
344 struct resource *resource;
345
346 /* Initialize the io space constraints on the current bus */
347 resource = new_resource(dev, IOINDEX(0, link));
348 if (resource) {
349 resource->base = 0;
350 resource->size = 0;
351 resource->align = log2(HT_IO_HOST_ALIGN);
352 resource->gran = log2(HT_IO_HOST_ALIGN);
353 resource->limit = 0xffffUL;
354 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
355 }
356
357 /* Initialize the prefetchable memory constraints on the current bus */
358 resource = new_resource(dev, IOINDEX(2, link));
359 if (resource) {
360 resource->base = 0;
361 resource->size = 0;
362 resource->align = log2(HT_MEM_HOST_ALIGN);
363 resource->gran = log2(HT_MEM_HOST_ALIGN);
364 resource->limit = 0xffffffffffULL;
365 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
366 resource->flags |= IORESOURCE_BRIDGE;
367 }
368
369 /* Initialize the memory constraints on the current bus */
370 resource = new_resource(dev, IOINDEX(1, link));
371 if (resource) {
372 resource->base = 0;
373 resource->size = 0;
374 resource->align = log2(HT_MEM_HOST_ALIGN);
375 resource->gran = log2(HT_MEM_HOST_ALIGN);
376 resource->limit = 0xffffffffULL;
377 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
378 }
379 }
380
381 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
382
383 static void amdk8_read_resources(device_t dev)
384 {
385 unsigned nodeid;
386 struct bus *link;
387 nodeid = amdk8_nodeid(dev);
388 for(link = dev->link_list; link; link = link->next) {
389 if (link->children) {
390 amdk8_link_read_bases(dev, nodeid, link->link_num);
391 }
392 }
393 amdk8_create_vga_resource(dev, nodeid);
394 }
395
396 static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
397 {
398 struct bus *link;
399 resource_t rbase, rend;
400 unsigned reg, link_num;
401 char buf[50];
402
403 /* Make certain the resource has actually been set */
404 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
405 printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
406 __func__, resource->index, resource->flags);
407 return;
408 }
409
410 /* If I have already stored this resource don't worry about it */
411 if (resource->flags & IORESOURCE_STORED) {
412 printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
413 resource->index, resource->flags);
414 return;
415 }
416
417 /* Only handle PCI memory and IO resources */
418 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
419 return;
420
421 /* Ensure I am actually looking at a resource of function 1 */
422 if (resource->index < 0x100) {
423 return;
424 }
425
426 if (resource->size == 0)
427 return;
428
429 /* Get the base address */
430 rbase = resource->base;
431
432 /* Get the limit (rounded up) */
433 rend = resource_end(resource);
434
435 /* Get the register and link */
436 reg = resource->index & 0xfc;
437 link_num = IOINDEX_LINK(resource->index);
438
439 for (link = dev->link_list; link; link = link->next)
440 if (link->link_num == link_num)
441 break;
442
443 if (link == NULL) {
444 printk(BIOS_ERR, "%s: can't find link %x for %lx\n", __func__,
445 link_num, resource->index);
446 return;
447 }
448
449 if (resource->flags & IORESOURCE_IO) {
450 u32 base, limit;
451 base = f1_read_config32(reg);
452 limit = f1_read_config32(reg + 0x4);
453 base &= 0xfe000fcc;
454 base |= rbase & 0x01fff000;
455 base |= 3;
456 limit &= 0xfe000fc8;
457 limit |= rend & 0x01fff000;
458 limit |= (link_num & 3) << 4;
459 limit |= (nodeid & 7);
460
461 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
462 printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
463 __func__, dev_path(dev), link_num);
464 base |= PCI_IO_BASE_VGA_EN;
465 }
466 if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
467 base |= PCI_IO_BASE_NO_ISA;
468 }
469
470 f1_write_config32(reg + 0x4, limit);
471 f1_write_config32(reg, base);
472 }
473 else if (resource->flags & IORESOURCE_MEM) {
474 u32 base, limit;
475 base = f1_read_config32(reg);
476 limit = f1_read_config32(reg + 0x4);
477 base &= 0x000000f0;
478 base |= (rbase >> 8) & 0xffffff00;
479 base |= 3;
480 limit &= 0x00000048;
481 limit |= (rend >> 8) & 0xffffff00;
482 limit |= (link_num & 3) << 4;
483 limit |= (nodeid & 7);
484 f1_write_config32(reg + 0x4, limit);
485 f1_write_config32(reg, base);
486 }
487 resource->flags |= IORESOURCE_STORED;
488 snprintf(buf, sizeof (buf), " <node %x link %x>",
489 nodeid, link_num);
490 report_resource_stored(dev, resource, buf);
491 }
492
493 static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
494 {
495 struct resource *resource;
496 struct bus *link;
497
498 /* find out which link the VGA card is connected,
499 * we only deal with the 'first' vga card */
500 for (link = dev->link_list; link; link = link->next) {
501 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
502 #if CONFIG_MULTIPLE_VGA_ADAPTERS
503 extern device_t vga_pri; // the primary vga device, defined in device.c
504 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
505 link->secondary,link->subordinate);
506 /* We need to make sure the vga_pri is under the link */
507 if((vga_pri->bus->secondary >= link->secondary ) &&
508 (vga_pri->bus->secondary <= link->subordinate )
509 )
510 #endif
511 break;
512 }
513 }
514
515 /* no VGA card installed */
516 if (link == NULL)
517 return;
518
519 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
520
521 /* allocate a temp resource for the legacy VGA buffer */
522 resource = new_resource(dev, IOINDEX(4, link->link_num));
523 if(!resource){
524 printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
525 return;
526 }
527 resource->base = 0xa0000;
528 resource->size = 0x20000;
529 resource->limit = 0xffffffff;
530 resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
531 IORESOURCE_ASSIGNED;
532 }
533
534 static void amdk8_set_resources(device_t dev)
535 {
536 unsigned nodeid;
537 struct bus *bus;
538 struct resource *res;
539
540 /* Find the nodeid */
541 nodeid = amdk8_nodeid(dev);
542
543 /* Set each resource we have found */
544 for(res = dev->resource_list; res; res = res->next) {
545 struct resource *old = NULL;
546 unsigned index;
547
548 if (res->size == 0) /* No need to allocate registers. */
549 continue;
550
551 if (res->flags & IORESOURCE_IO)
552 index = amdk8_find_iopair(dev, nodeid,
553 IOINDEX_LINK(res->index));
554 else
555 index = amdk8_find_mempair(dev, nodeid,
556 IOINDEX_LINK(res->index));
557
558 old = probe_resource(dev, index);
559 if (old) {
560 res->index = old->index;
561 old->index = 0;
562 old->flags = 0;
563 }
564 else
565 res->index = index;
566
567 amdk8_set_resource(dev, res, nodeid);
568 }
569
570 compact_resources(dev);
571
572 for(bus = dev->link_list; bus; bus = bus->next) {
573 if (bus->children) {
574 assign_resources(bus);
575 }
576 }
577 }
578
579 static void mcf0_control_init(struct device *dev)
580 {
581 #if 0
582 printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
583 #endif
584 #if 0
585 printk(BIOS_DEBUG, "done.\n");
586 #endif
587 }
588
589 static struct device_operations northbridge_operations = {
590 .read_resources = amdk8_read_resources,
591 .set_resources = amdk8_set_resources,
592 .enable_resources = pci_dev_enable_resources,
593 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
594 .acpi_fill_ssdt_generator = k8acpi_write_vars,
595 .write_acpi_tables = northbridge_write_acpi_tables,
596 #endif
597 .init = mcf0_control_init,
598 .scan_bus = amdk8_scan_chains,
599 .enable = 0,
600 .ops_pci = 0,
601 };
602
603
604 static const struct pci_driver mcf0_driver __pci_driver = {
605 .ops = &northbridge_operations,
606 .vendor = PCI_VENDOR_ID_AMD,
607 .device = 0x1100,
608 };
609
610 struct chip_operations northbridge_amd_amdk8_ops = {
611 CHIP_NAME("AMD K8 Northbridge")
612 .enable_dev = 0,
613 };
614
615 static void amdk8_domain_read_resources(device_t dev)
616 {
617 unsigned reg;
618
619 /* Find the already assigned resource pairs */
620 get_fx_devs();
621 for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
622 u32 base, limit;
623 base = f1_read_config32(reg);
624 limit = f1_read_config32(reg + 0x04);
625 /* Is this register allocated? */
626 if ((base & 3) != 0) {
627 unsigned nodeid, reg_link;
628 device_t reg_dev;
629 nodeid = limit & 7;
630 reg_link = (limit >> 4) & 3;
631 reg_dev = __f0_dev[nodeid];
632 if (reg_dev) {
633 /* Reserve the resource */
634 struct resource *res;
635 res = new_resource(reg_dev, IOINDEX(0x100 + reg, reg_link));
636 if (res) {
637 res->base = base;
638 res->limit = limit;
639 res->flags = 1;
640 }
641 }
642 }
643 }
644
645 pci_domain_read_resources(dev);
646
647 #if CONFIG_PCI_64BIT_PREF_MEM
648 /* Initialize the system wide prefetchable memory resources constraints */
649 resource = new_resource(dev, 2);
650 resource->limit = 0xfcffffffffULL;
651 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
652 #endif
653 }
654
655 static void my_tolm_test(void *gp, struct device *dev, struct resource *new)
656 {
657 struct resource **best_p = gp;
658 struct resource *best;
659 best = *best_p;
660 /* Skip VGA. */
661 if (!best || (best->base > new->base && new->base > 0xa0000)) {
662 best = new;
663 }
664 *best_p = best;
665 }
666
667 static u32 my_find_pci_tolm(struct bus *bus)
668 {
669 struct resource *min;
670 u32 tolm;
671 min = 0;
672 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, my_tolm_test, &min);
673 tolm = 0xffffffffUL;
674 if (min && tolm > min->base) {
675 tolm = min->base;
676 }
677 return tolm;
678 }
679
680 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
681
682 struct hw_mem_hole_info {
683 unsigned hole_startk;
684 int node_id;
685 };
686
687 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
688 {
689 struct hw_mem_hole_info mem_hole;
690 int i;
691
692 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
693 mem_hole.node_id = -1;
694
695 for (i = 0; i < fx_devs; i++) {
696 u32 base;
697 u32 hole;
698 base = f1_read_config32(0x40 + (i << 3));
699 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
700 continue;
701 }
702
703 hole = pci_read_config32(__f1_dev[i], 0xf0);
704 if(hole & 1) { // we find the hole
705 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
706 mem_hole.node_id = i; // record the node No with hole
707 break; // only one hole
708 }
709 }
710
711 /* We need to double check if there is special set on base reg and limit reg
712 * are not continuous instead of hole, it will find out its hole_startk.
713 */
714 if(mem_hole.node_id==-1) {
715 u32 limitk_pri = 0;
716 for(i=0; i<8; i++) {
717 u32 base, limit;
718 unsigned base_k, limit_k;
719 base = f1_read_config32(0x40 + (i << 3));
720 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
721 continue;
722 }
723
724 base_k = (base & 0xffff0000) >> 2;
725 if(limitk_pri != base_k) { // we find the hole
726 mem_hole.hole_startk = limitk_pri;
727 mem_hole.node_id = i;
728 break; //only one hole
729 }
730
731 limit = f1_read_config32(0x44 + (i << 3));
732 limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
733 limitk_pri = limit_k;
734 }
735 }
736 return mem_hole;
737 }
738
739 static void disable_hoist_memory(unsigned long hole_startk, int node_id)
740 {
741 int i;
742 device_t dev;
743 u32 base, limit;
744 u32 hoist;
745 u32 hole_sizek;
746
747
748 //1. find which node has hole
749 //2. change limit in that node.
750 //3. change base and limit in later node
751 //4. clear that node f0
752
753 //if there is not mem hole enabled, we need to change it's base instead
754
755 hole_sizek = (4*1024*1024) - hole_startk;
756
757 for(i=7;i>node_id;i--) {
758
759 base = f1_read_config32(0x40 + (i << 3));
760 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
761 continue;
762 }
763 limit = f1_read_config32(0x44 + (i << 3));
764 f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
765 f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
766 }
767 limit = f1_read_config32(0x44 + (node_id << 3));
768 f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
769 dev = __f1_dev[node_id];
770 if (dev == NULL) {
771 printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
772 return;
773 }
774 hoist = pci_read_config32(dev, 0xf0);
775 if(hoist & 1) {
776 pci_write_config32(dev, 0xf0, 0);
777 } else {
778 base = pci_read_config32(dev, 0x40 + (node_id << 3));
779 f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
780 }
781 }
782
783 static u32 hoist_memory(unsigned long hole_startk, int node_id)
784 {
785 int i;
786 u32 carry_over;
787 device_t dev;
788 u32 base, limit;
789 u32 basek;
790 u32 hoist;
791
792 carry_over = (4*1024*1024) - hole_startk;
793
794 for(i=7;i>node_id;i--) {
795
796 base = f1_read_config32(0x40 + (i << 3));
797 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
798 continue;
799 }
800 limit = f1_read_config32(0x44 + (i << 3));
801 f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
802 f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
803 }
804 limit = f1_read_config32(0x44 + (node_id << 3));
805 f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
806 dev = __f1_dev[node_id];
807 base = pci_read_config32(dev, 0x40 + (node_id << 3));
808 basek = (base & 0xffff0000) >> 2;
809 if(basek == hole_startk) {
810 //don't need set memhole here, because hole off set will be 0, overflow
811 //so need to change base reg instead, new basek will be 4*1024*1024
812 base &= 0x0000ffff;
813 base |= (4*1024*1024)<<2;
814 f1_write_config32(0x40 + (node_id<<3), base);
815 }
816 else if (dev)
817 {
818 hoist = /* hole start address */
819 ((hole_startk << 10) & 0xff000000) +
820 /* hole address to memory controller address */
821 (((basek + carry_over) >> 6) & 0x0000ff00) +
822 /* enable */
823 1;
824
825 pci_write_config32(dev, 0xf0, hoist);
826 }
827
828 return carry_over;
829 }
830 #endif
831
832 #include <cbmem.h>
833
834 static void setup_uma_memory(void)
835 {
836 #if CONFIG_GFXUMA
837 uint32_t topmem = (uint32_t) bsp_topmem();
838
839 #if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY
840
841 switch (topmem) {
842 case 0x10000000: /* 256M system memory */
843 uma_memory_size = 0x2000000; /* 32M recommended UMA */
844 break;
845
846 case 0x18000000: /* 384M system memory */
847 uma_memory_size = 0x4000000; /* 64M recommended UMA */
848 break;
849
850 case 0x20000000: /* 512M system memory */
851 uma_memory_size = 0x4000000; /* 64M recommended UMA */
852 break;
853
854 default: /* 1GB and above system memory */
855 uma_memory_size = 0x8000000; /* 128M recommended UMA */
856 break;
857 }
858 #else
859 /* refer to UMA Size Consideration in 780 BDG. */
860 switch (topmem) {
861 case 0x10000000: /* 256M system memory */
862 uma_memory_size = 0x4000000; /* 64M recommended UMA */
863 break;
864
865 case 0x20000000: /* 512M system memory */
866 uma_memory_size = 0x8000000; /* 128M recommended UMA */
867 break;
868
869 default: /* 1GB and above system memory */
870 uma_memory_size = 0x10000000; /* 256M recommended UMA */
871 break;
872 }
873 #endif
874
875 uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
876 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
877 __func__, uma_memory_size, uma_memory_base);
878 #endif
879 }
880
881 static void amdk8_domain_set_resources(device_t dev)
882 {
883 #if CONFIG_PCI_64BIT_PREF_MEM
884 struct resource *io, *mem1, *mem2;
885 struct resource *res;
886 #endif
887 unsigned long mmio_basek;
888 u32 pci_tolm;
889 u64 ramtop = 0;
890 int i, idx;
891 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
892 struct hw_mem_hole_info mem_hole;
893 u32 reset_memhole = 1;
894 #endif
895
896 #if 0
897 /* Place the IO devices somewhere safe */
898 io = find_resource(dev, 0);
899 io->base = DEVICE_IO_START;
900 #endif
901 #if CONFIG_PCI_64BIT_PREF_MEM
902 /* Now reallocate the pci resources memory with the
903 * highest addresses I can manage.
904 */
905 mem1 = find_resource(dev, 1);
906 mem2 = find_resource(dev, 2);
907
908 #if 1
909 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
910 mem1->base, mem1->limit, mem1->size, mem1->align);
911 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
912 mem2->base, mem2->limit, mem2->size, mem2->align);
913 #endif
914
915 /* See if both resources have roughly the same limits */
916 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
917 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
918 {
919 /* If so place the one with the most stringent alignment first
920 */
921 if (mem2->align > mem1->align) {
922 struct resource *tmp;
923 tmp = mem1;
924 mem1 = mem2;
925 mem2 = tmp;
926 }
927 /* Now place the memory as high up as it will go */
928 mem2->base = resource_max(mem2);
929 mem1->limit = mem2->base - 1;
930 mem1->base = resource_max(mem1);
931 }
932 else {
933 /* Place the resources as high up as they will go */
934 mem2->base = resource_max(mem2);
935 mem1->base = resource_max(mem1);
936 }
937
938 #if 1
939 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
940 mem1->base, mem1->limit, mem1->size, mem1->align);
941 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
942 mem2->base, mem2->limit, mem2->size, mem2->align);
943 #endif
944
945 for(res = dev->resource_list; res; res = res->next)
946 {
947 res->flags |= IORESOURCE_ASSIGNED;
948 res->flags |= IORESOURCE_STORED;
949 report_resource_stored(dev, res, "");
950 }
951 #endif
952
953 pci_tolm = my_find_pci_tolm(dev->link_list);
954
955 // FIXME handle interleaved nodes. If you fix this here, please fix
956 // amdfam10, too.
957 mmio_basek = pci_tolm >> 10;
958 /* Round mmio_basek to something the processor can support */
959 mmio_basek &= ~((1 << 6) -1);
960
961 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
962 // MMIO hole. If you fix this here, please fix amdfam10, too.
963 /* Round the mmio hole to 64M */
964 mmio_basek &= ~((64*1024) - 1);
965
966 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
967 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek
968 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
969 * otherwise We reset the hole to the mmio_basek
970 */
971 #if !CONFIG_K8_REV_F_SUPPORT
972 if (!is_cpu_pre_e0()) {
973 #endif
974
975 mem_hole = get_hw_mem_hole_info();
976
977 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore
978 mmio_basek = mem_hole.hole_startk;
979 reset_memhole = 0;
980 }
981
982 //mmio_basek = 3*1024*1024; // for debug to meet boundary
983
984 if(reset_memhole) {
985 if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
986 // We need to reset our Mem Hole, because We want more big HOLE than we already set
987 //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead
988 disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
989 }
990
991 #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
992 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
993 u32 basek_pri;
994 for (i = 0; i < fx_devs; i++) {
995 u32 base;
996 u32 basek;
997 base = f1_read_config32(0x40 + (i << 3));
998 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
999 continue;
1000 }
1001
1002 basek = (base & 0xffff0000) >> 2;
1003 if(mmio_basek == basek) {
1004 mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node
1005 break;
1006 }
1007 basek_pri = basek;
1008 }
1009 #endif
1010 }
1011
1012 #if !CONFIG_K8_REV_F_SUPPORT
1013 } // is_cpu_pre_e0
1014 #endif
1015
1016 #endif
1017
1018 idx = 0x10;
1019 for(i = 0; i < fx_devs; i++) {
1020 u32 base, limit;
1021 u32 basek, limitk, sizek;
1022 base = f1_read_config32(0x40 + (i << 3));
1023 limit = f1_read_config32(0x44 + (i << 3));
1024 if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
1025 continue;
1026 }
1027 basek = (base & 0xffff0000) >> 2;
1028 limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
1029 sizek = limitk - basek;
1030
1031 /* see if we need a hole from 0xa0000 to 0xbffff */
1032 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
1033 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
1034 idx += 0x10;
1035 basek = (8*64)+(16*16);
1036 sizek = limitk - ((8*64)+(16*16));
1037
1038 }
1039
1040
1041 #if CONFIG_GFXUMA
1042 printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
1043 if ((uma_memory_base >> 10) < mmio_basek)
1044 printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
1045 #else
1046 // printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
1047 #endif
1048
1049 /* See if I need to split the region to accommodate pci memory space */
1050 if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
1051 if (basek <= mmio_basek) {
1052 unsigned pre_sizek;
1053 pre_sizek = mmio_basek - basek;
1054 if(pre_sizek>0) {
1055 ram_resource(dev, (idx | i), basek, pre_sizek);
1056 idx += 0x10;
1057 sizek -= pre_sizek;
1058 if (!ramtop)
1059 ramtop = mmio_basek * 1024;
1060 }
1061 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
1062 if(reset_memhole)
1063 #if !CONFIG_K8_REV_F_SUPPORT
1064 if(!is_cpu_pre_e0() )
1065 #endif
1066 sizek += hoist_memory(mmio_basek,i);
1067 #endif
1068
1069 basek = mmio_basek;
1070 }
1071 if ((basek + sizek) <= 4*1024*1024) {
1072 sizek = 0;
1073 }
1074 else {
1075 basek = 4*1024*1024;
1076 sizek -= (4*1024*1024 - mmio_basek);
1077 }
1078 }
1079
1080 ram_resource(dev, (idx | i), basek, sizek);
1081 idx += 0x10;
1082 printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
1083 i, mmio_basek, basek, limitk);
1084 if (!ramtop)
1085 ramtop = limitk * 1024;
1086 }
1087
1088 #if CONFIG_GFXUMA
1089 set_top_of_ram(uma_memory_base);
1090 uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
1091 #else
1092 set_top_of_ram(ramtop);
1093 #endif
1094 assign_resources(dev->link_list);
1095
1096 }
1097
1098 static u32 amdk8_domain_scan_bus(device_t dev, u32 unused)
1099 {
1100 u32 reg;
1101 int i;
1102 struct bus *link = dev->link_list;
1103
1104 /* Unmap all of the HT chains */
1105 for(reg = 0xe0; reg <= 0xec; reg += 4) {
1106 f1_write_config32(reg, 0);
1107 }
1108
1109 link->secondary = dev->bus->subordinate;
1110 pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff);
1111 dev->bus->subordinate = link->subordinate;
1112
1113 /* Tune the hypertransport transaction for best performance.
1114 * Including enabling relaxed ordering if it is safe.
1115 */
1116 get_fx_devs();
1117 for(i = 0; i < fx_devs; i++) {
1118 device_t f0_dev;
1119 f0_dev = __f0_dev[i];
1120 if (f0_dev && f0_dev->enabled) {
1121 u32 httc;
1122 httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
1123 httc &= ~HTTC_RSP_PASS_PW;
1124 if (!dev->link_list->disable_relaxed_ordering) {
1125 httc |= HTTC_RSP_PASS_PW;
1126 }
1127 printk(BIOS_SPEW, "%s passpw: %s\n",
1128 dev_path(dev),
1129 (!dev->link_list->disable_relaxed_ordering)?
1130 "enabled":"disabled");
1131 pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
1132 }
1133 }
1134 return unused;
1135 }
1136
1137 static struct device_operations pci_domain_ops = {
1138 .read_resources = amdk8_domain_read_resources,
1139 .set_resources = amdk8_domain_set_resources,
1140 .enable_resources = NULL,
1141 .init = NULL,
1142 .scan_bus = amdk8_domain_scan_bus,
1143 .ops_pci_bus = pci_bus_default_ops,
1144 };
1145
1146 static void add_more_links(device_t dev, unsigned total_links)
1147 {
1148 struct bus *link, *last = NULL;
1149 int link_num = -1;
1150
1151 for (link = dev->link_list; link; link = link->next) {
1152 if (link_num < link->link_num)
1153 link_num = link->link_num;
1154 last = link;
1155 }
1156
1157 if (last) {
1158 int links = total_links - (link_num + 1);
1159 if (links > 0) {
1160 link = malloc(links*sizeof(*link));
1161 if (!link)
1162 die("Couldn't allocate more links!\n");
1163 memset(link, 0, links*sizeof(*link));
1164 last->next = link;
1165 }
1166 }
1167 else {
1168 link = malloc(total_links*sizeof(*link));
1169 memset(link, 0, total_links*sizeof(*link));
1170 dev->link_list = link;
1171 }
1172
1173 for (link_num = link_num + 1; link_num < total_links; link_num++) {
1174 link->link_num = link_num;
1175 link->dev = dev;
1176 link->next = link + 1;
1177 last = link;
1178 link = link->next;
1179 }
1180 last->next = NULL;
1181 }
1182
1183 static u32 cpu_bus_scan(device_t dev, u32 passthru)
1184 {
1185 struct bus *cpu_bus;
1186 device_t dev_mc;
1187 int bsp_apicid;
1188 int i,j;
1189 unsigned nb_cfg_54;
1190 unsigned siblings;
1191 int e0_later_single_core;
1192 int disable_siblings;
1193
1194 nb_cfg_54 = 0;
1195 sysconf.enabled_apic_ext_id = 0;
1196 sysconf.lift_bsp_apicid = 0;
1197 siblings = 0;
1198
1199 /* Find the bootstrap processors apicid */
1200 bsp_apicid = lapicid();
1201 sysconf.apicid_offset = bsp_apicid;
1202
1203 disable_siblings = !CONFIG_LOGICAL_CPUS;
1204 #if CONFIG_LOGICAL_CPUS
1205 get_option(&disable_siblings, "multi_core");
1206 #endif
1207
1208 // for pre_e0, nb_cfg_54 can not be set, (when you read it still is 0)
1209 // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
1210 // and differ d0 and e0 single core
1211 nb_cfg_54 = read_nb_cfg_54();
1212
1213 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1214 if (!dev_mc) {
1215 die("0:18.0 not found?");
1216 }
1217
1218 sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
1219
1220
1221 if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
1222 {
1223 sysconf.enabled_apic_ext_id = 1;
1224 if(bsp_apicid == 0) {
1225 /* bsp apic id is not changed */
1226 sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
1227 } else
1228 {
1229 sysconf.lift_bsp_apicid = 1;
1230 }
1231
1232 }
1233
1234 /* Find which cpus are present */
1235 cpu_bus = dev->link_list;
1236
1237 /* Always use the devicetree node with lapic_id 0 for BSP. */
1238 remap_bsp_lapic(cpu_bus);
1239
1240 for(i = 0; i < sysconf.nodes; i++) {
1241 device_t cpu_dev;
1242
1243 /* Find the cpu's pci device */
1244 cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
1245 if (!cpu_dev) {
1246 /* If I am probing things in a weird order
1247 * ensure all of the cpu's pci devices are found.
1248 */
1249 int local_j;
1250 device_t dev_f0;
1251 for(local_j = 0; local_j <= 3; local_j++) {
1252 cpu_dev = pci_probe_dev(NULL, dev_mc->bus,
1253 PCI_DEVFN(0x18 + i, local_j));
1254 }
1255 /* Ok, We need to set the links for that device.
1256 * otherwise the device under it will not be scanned
1257 */
1258 dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
1259 if(dev_f0) {
1260 add_more_links(dev_f0, 3);
1261 }
1262 }
1263
1264 e0_later_single_core = 0;
1265 int enable_node = cpu_dev && cpu_dev->enabled;
1266 if (enable_node) {
1267 j = pci_read_config32(cpu_dev, 0xe8);
1268 j = (j >> 12) & 3; // dev is func 3
1269 printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cpu_dev), j);
1270
1271 if(nb_cfg_54) {
1272 // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
1273 // ----> you can mixed single core e0 and dual core e0 at any sequence
1274 // That is the typical case
1275
1276 if(j == 0 ){
1277 #if !CONFIG_K8_REV_F_SUPPORT
1278 e0_later_single_core = is_e0_later_in_bsp(i); // single core
1279 #else
1280 e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
1281 #endif
1282 } else {
1283 e0_later_single_core = 0;
1284 }
1285 if(e0_later_single_core) {
1286 printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
1287
1288 j=1;
1289 }
1290
1291 if(siblings > j ) {
1292 }
1293 else {
1294 siblings = j;
1295 }
1296 } else {
1297 siblings = j;
1298 }
1299 }
1300
1301 u32 jj;
1302 if(e0_later_single_core || disable_siblings) {
1303 jj = 0;
1304 } else
1305 {
1306 jj = siblings;
1307 }
1308
1309 for (j = 0; j <=jj; j++ ) {
1310 u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
1311 if(sysconf.enabled_apic_ext_id) {
1312 if (apic_id != 0 || sysconf.lift_bsp_apicid) {
1313 apic_id += sysconf.apicid_offset;
1314 }
1315 }
1316
1317 device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1318 if (cpu)
1319 amd_cpu_topology(cpu, i, j);
1320 } //j
1321 }
1322 return passthru;
1323 }
1324
1325 static void cpu_bus_init(device_t dev)
1326 {
1327 #if CONFIG_WAIT_BEFORE_CPUS_INIT
1328 cpus_ready_for_init();
1329 #endif
1330 initialize_cpus(dev->link_list);
1331 }
1332
1333 static struct device_operations cpu_bus_ops = {
1334 .read_resources = DEVICE_NOOP,
1335 .set_resources = DEVICE_NOOP,
1336 .enable_resources = DEVICE_NOOP,
1337 .init = cpu_bus_init,
1338 .scan_bus = cpu_bus_scan,
1339 };
1340
1341 static void root_complex_enable_dev(struct device *dev)
1342 {
1343 static int done = 0;
1344
1345 /* Do not delay UMA setup, as a device on the PCI bus may evaluate
1346 the global uma_memory variables already in its enable function. */
1347 if (!done) {
1348 setup_bsp_ramtop();
1349 setup_uma_memory();
1350 done = 1;
1351 }
1352
1353 /* Set the operations if it is a special bus type */
1354 if (dev->path.type == DEVICE_PATH_DOMAIN) {
1355 dev->ops = &pci_domain_ops;
1356 }
1357 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
1358 dev->ops = &cpu_bus_ops;
1359 }
1360 }
1361
1362 struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
1363 CHIP_NAME("AMD K8 Root Complex")
1364 .enable_dev = root_complex_enable_dev,
1365 };
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