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PCI subsystem: Drop parameter max from scan_bus
[coreboot.git] / src / northbridge / amd / agesa / family15 / northbridge.c
blobe480ebaff7227d78583b027a78f20c4c3f54d5e9
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc.
18 */
19
20 #include <console/console.h>
21 #include <arch/acpi.h>
22 #include <arch/acpigen.h>
23 #include <arch/io.h>
24 #include <stdint.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <device/hypertransport.h>
29 #include <stdlib.h>
30 #include <string.h>
31 #include <lib.h>
32 #include <cpu/cpu.h>
33 #include <cbmem.h>
34
35 #include <cpu/x86/lapic.h>
36 #include <cpu/amd/mtrr.h>
37
38 #include <Porting.h>
39 #include <AGESA.h>
40 #include <Options.h>
41 #include <Topology.h>
42 #include <cpu/amd/amdfam15.h>
43 #include <cpuRegisters.h>
44 #include <northbridge/amd/agesa/agesawrapper.h>
45 #include "sb_cimx.h"
46
47 #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
48
49 typedef struct dram_base_mask {
50 u32 base; //[47:27] at [28:8]
51 u32 mask; //[47:27] at [28:8] and enable at bit 0
52 } dram_base_mask_t;
53
54 static unsigned node_nums;
55 static unsigned sblink;
56 static device_t __f0_dev[MAX_NODE_NUMS];
57 static device_t __f1_dev[MAX_NODE_NUMS];
58 static device_t __f2_dev[MAX_NODE_NUMS];
59 static device_t __f4_dev[MAX_NODE_NUMS];
60 static unsigned fx_devs = 0;
61
62 static dram_base_mask_t get_dram_base_mask(u32 nodeid)
63 {
64 device_t dev;
65 dram_base_mask_t d;
66 dev = __f1_dev[0];
67 u32 temp;
68 temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
69 d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
70 temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
71 d.mask |= temp<<21;
72 temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
73 d.mask |= (temp & 1); // enable bit
74 d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
75 temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
76 d.base |= temp<<21;
77 return d;
78 }
79
80 static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
81 u32 io_min, u32 io_max)
82 {
83 u32 i;
84 u32 tempreg;
85 /* io range allocation */
86 tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
87 for (i=0; i<node_nums; i++)
88 pci_write_config32(__f1_dev[i], reg+4, tempreg);
89 tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
90 #if 0
91 // FIXME: can we use VGA reg instead?
92 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
93 printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
94 __func__, dev_path(dev), link);
95 tempreg |= PCI_IO_BASE_VGA_EN;
96 }
97 if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
98 tempreg |= PCI_IO_BASE_NO_ISA;
99 }
100 #endif
101 for (i=0; i<node_nums; i++)
102 pci_write_config32(__f1_dev[i], reg, tempreg);
103 }
104
105 static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
106 {
107 u32 i;
108 u32 tempreg;
109 /* io range allocation */
110 tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit
111 for (i=0; i<nodes; i++)
112 pci_write_config32(__f1_dev[i], reg+4, tempreg);
113 tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
114 for (i=0; i<node_nums; i++)
115 pci_write_config32(__f1_dev[i], reg, tempreg);
116 }
117
118 static device_t get_node_pci(u32 nodeid, u32 fn)
119 {
120 #if MAX_NODE_NUMS + CONFIG_CDB >= 32
121 if ((CONFIG_CDB + nodeid) < 32) {
122 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
123 } else {
124 return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
125 }
126 #else
127 return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
128 #endif
129 }
130
131 static void get_fx_devs(void)
132 {
133 int i;
134 for (i = 0; i < MAX_NODE_NUMS; i++) {
135 __f0_dev[i] = get_node_pci(i, 0);
136 __f1_dev[i] = get_node_pci(i, 1);
137 __f2_dev[i] = get_node_pci(i, 2);
138 __f4_dev[i] = get_node_pci(i, 4);
139 if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
140 fx_devs = i+1;
141 }
142 if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
143 die("Cannot find 0:0x18.[0|1]\n");
144 }
145 printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
146 }
147
148 static u32 f1_read_config32(unsigned reg)
149 {
150 if (fx_devs == 0)
151 get_fx_devs();
152 return pci_read_config32(__f1_dev[0], reg);
153 }
154
155 static void f1_write_config32(unsigned reg, u32 value)
156 {
157 int i;
158 if (fx_devs == 0)
159 get_fx_devs();
160 for(i = 0; i < fx_devs; i++) {
161 device_t dev;
162 dev = __f1_dev[i];
163 if (dev && dev->enabled) {
164 pci_write_config32(dev, reg, value);
165 }
166 }
167 }
168
169 static u32 amdfam15_nodeid(device_t dev)
170 {
171 #if MAX_NODE_NUMS == 64
172 unsigned busn;
173 busn = dev->bus->secondary;
174 if (busn != CONFIG_CBB) {
175 return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
176 } else {
177 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
178 }
179
180 #else
181 return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
182 #endif
183 }
184
185 static void set_vga_enable_reg(u32 nodeid, u32 linkn)
186 {
187 u32 val;
188
189 val = 1 | (nodeid<<4) | (linkn<<12);
190 /* it will routing
191 * (1)mmio 0xa0000:0xbffff
192 * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
193 */
194 f1_write_config32(0xf4, val);
195
196 }
197
198 /**
199 * @return
200 * @retval 2 resoure does not exist, usable
201 * @retval 0 resource exists, not usable
202 * @retval 1 resource exist, resource has been allocated before
203 */
204 static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
205 unsigned goal_link)
206 {
207 struct resource *res;
208 unsigned nodeid, link = 0;
209 int result;
210 res = 0;
211 for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
212 device_t dev;
213 dev = __f0_dev[nodeid];
214 if (!dev)
215 continue;
216 for (link = 0; !res && (link < 8); link++) {
217 res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
218 }
219 }
220 result = 2;
221 if (res) {
222 result = 0;
223 if ((goal_link == (link - 1)) &&
224 (goal_nodeid == (nodeid - 1)) &&
225 (res->flags <= 1)) {
226 result = 1;
227 }
228 }
229 return result;
230 }
231
232 static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link)
233 {
234 struct resource *resource;
235 u32 free_reg, reg;
236 resource = 0;
237 free_reg = 0;
238 for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
239 int result;
240 result = reg_useable(reg, dev, nodeid, link);
241 if (result == 1) {
242 /* I have been allocated this one */
243 break;
244 }
245 else if (result > 1) {
246 /* I have a free register pair */
247 free_reg = reg;
248 }
249 }
250 if (reg > 0xd8) {
251 reg = free_reg; // if no free, the free_reg still be 0
252 }
253
254 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
255
256 return resource;
257 }
258
259 static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link)
260 {
261 struct resource *resource;
262 u32 free_reg, reg;
263 resource = 0;
264 free_reg = 0;
265 for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
266 int result;
267 result = reg_useable(reg, dev, nodeid, link);
268 if (result == 1) {
269 /* I have been allocated this one */
270 break;
271 }
272 else if (result > 1) {
273 /* I have a free register pair */
274 free_reg = reg;
275 }
276 }
277 if (reg > 0xb8) {
278 reg = free_reg;
279 }
280
281 resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
282 return resource;
283 }
284
285 static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
286 {
287 struct resource *resource;
288
289 /* Initialize the io space constraints on the current bus */
290 resource = amdfam15_find_iopair(dev, nodeid, link);
291 if (resource) {
292 u32 align;
293 align = log2(HT_IO_HOST_ALIGN);
294 resource->base = 0;
295 resource->size = 0;
296 resource->align = align;
297 resource->gran = align;
298 resource->limit = 0xffffUL;
299 resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
300 }
301
302 /* Initialize the prefetchable memory constraints on the current bus */
303 resource = amdfam15_find_mempair(dev, nodeid, link);
304 if (resource) {
305 resource->base = 0;
306 resource->size = 0;
307 resource->align = log2(HT_MEM_HOST_ALIGN);
308 resource->gran = log2(HT_MEM_HOST_ALIGN);
309 resource->limit = 0xffffffffffULL;
310 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
311 resource->flags |= IORESOURCE_BRIDGE;
312 }
313
314 /* Initialize the memory constraints on the current bus */
315 resource = amdfam15_find_mempair(dev, nodeid, link);
316 if (resource) {
317 resource->base = 0;
318 resource->size = 0;
319 resource->align = log2(HT_MEM_HOST_ALIGN);
320 resource->gran = log2(HT_MEM_HOST_ALIGN);
321 resource->limit = 0xffffffffffULL;
322 resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
323 }
324
325 }
326
327 static void nb_read_resources(device_t dev)
328 {
329 u32 nodeid;
330 struct bus *link;
331
332 nodeid = amdfam15_nodeid(dev);
333 for (link = dev->link_list; link; link = link->next) {
334 if (link->children) {
335 amdfam15_link_read_bases(dev, nodeid, link->link_num);
336 }
337 }
338
339 /*
340 * This MMCONF resource must be reserved in the PCI domain.
341 * It is not honored by the coreboot resource allocator if it is in
342 * the CPU_CLUSTER.
343 */
344 #if CONFIG_MMCONF_SUPPORT
345 struct resource *resource = new_resource(dev, 0xc0010058);
346 resource->base = CONFIG_MMCONF_BASE_ADDRESS;
347 resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
348 resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
349 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
350 #endif
351 }
352
353 static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
354 {
355 resource_t rbase, rend;
356 unsigned reg, link_num;
357 char buf[50];
358
359 /* Make certain the resource has actually been set */
360 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
361 return;
362 }
363
364 /* If I have already stored this resource don't worry about it */
365 if (resource->flags & IORESOURCE_STORED) {
366 return;
367 }
368
369 /* Only handle PCI memory and IO resources */
370 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
371 return;
372
373 /* Ensure I am actually looking at a resource of function 1 */
374 if ((resource->index & 0xffff) < 0x1000) {
375 return;
376 }
377 /* Get the base address */
378 rbase = resource->base;
379
380 /* Get the limit (rounded up) */
381 rend = resource_end(resource);
382
383 /* Get the register and link */
384 reg = resource->index & 0xfff; // 4k
385 link_num = IOINDEX_LINK(resource->index);
386
387 if (resource->flags & IORESOURCE_IO) {
388 set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
389 }
390 else if (resource->flags & IORESOURCE_MEM) {
391 set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums);// [39:8]
392 }
393 resource->flags |= IORESOURCE_STORED;
394 snprintf(buf, sizeof (buf), " <node %x link %x>",
395 nodeid, link_num);
396 report_resource_stored(dev, resource, buf);
397 }
398
399 /**
400 * I tried to reuse the resource allocation code in set_resource()
401 * but it is too difficult to deal with the resource allocation magic.
402 */
403
404 static void create_vga_resource(device_t dev, unsigned nodeid)
405 {
406 struct bus *link;
407
408 /* find out which link the VGA card is connected,
409 * we only deal with the 'first' vga card */
410 for (link = dev->link_list; link; link = link->next) {
411 if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
412 #if CONFIG_MULTIPLE_VGA_ADAPTERS
413 extern device_t vga_pri; // the primary vga device, defined in device.c
414 printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
415 link->secondary,link->subordinate);
416 /* We need to make sure the vga_pri is under the link */
417 if((vga_pri->bus->secondary >= link->secondary ) &&
418 (vga_pri->bus->secondary <= link->subordinate )
419 )
420 #endif
421 break;
422 }
423 }
424
425 /* no VGA card installed */
426 if (link == NULL)
427 return;
428
429 printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
430 set_vga_enable_reg(nodeid, sblink);
431 }
432
433 static void nb_set_resources(device_t dev)
434 {
435 unsigned nodeid;
436 struct bus *bus;
437 struct resource *res;
438
439 /* Find the nodeid */
440 nodeid = amdfam15_nodeid(dev);
441
442 create_vga_resource(dev, nodeid); //TODO: do we need this?
443
444 /* Set each resource we have found */
445 for (res = dev->resource_list; res; res = res->next) {
446 set_resource(dev, res, nodeid);
447 }
448
449 for (bus = dev->link_list; bus; bus = bus->next) {
450 if (bus->children) {
451 assign_resources(bus);
452 }
453 }
454
455 /* Print the MMCONF region if it has been reserved. */
456 res = find_resource(dev, 0xc0010058);
457 if (res) {
458 report_resource_stored(dev, res, " <mmconfig>");
459 }
460 }
461
462 static unsigned scan_chains(device_t dev, unsigned unused)
463 {
464 unsigned nodeid;
465 struct bus *link;
466 device_t io_hub = NULL;
467 u32 next_unitid = 0x18;
468 unsigned int max = dev->bus->subordinate;
469
470 nodeid = amdfam15_nodeid(dev);
471 if (nodeid == 0) {
472 ASSERT(dev->bus->secondary == 0);
473 for (link = dev->link_list; link; link = link->next) {
474 //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */
475 if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */
476 io_hub = link->children;
477 if (!io_hub || !io_hub->enabled) {
478 die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
479 }
480 /* Now that nothing is overlapping it is safe to scan the children. */
481 pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7);
482 }
483 }
484 max = dev->bus->subordinate;
485 }
486
487 dev->bus->subordinate = max;
488
489 return unused;
490 }
491
492
493 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
494 {
495 void *addr, *current;
496
497 /* Skip the HEST header. */
498 current = (void *)(hest + 1);
499
500 addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
501 if (addr != NULL)
502 current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
503
504 addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
505 if (addr != NULL)
506 current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
507
508 return (unsigned long)current;
509 }
510
511 static void northbridge_fill_ssdt_generator(void)
512 {
513 msr_t msr;
514 char pscope[] = "\\_SB.PCI0";
515
516 acpigen_write_scope(pscope);
517 msr = rdmsr(TOP_MEM);
518 acpigen_write_name_dword("TOM1", msr.lo);
519 msr = rdmsr(TOP_MEM2);
520 /*
521 * Since XP only implements parts of ACPI 2.0, we can't use a qword
522 * here.
523 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
524 * slide 22ff.
525 * Shift value right by 20 bit to make it fit into 32bit,
526 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
527 */
528 acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
529 acpigen_pop_len();
530 }
531
532 static unsigned long agesa_write_acpi_tables(unsigned long current,
533 acpi_rsdp_t *rsdp)
534 {
535 acpi_srat_t *srat;
536 acpi_slit_t *slit;
537 acpi_header_t *ssdt;
538 acpi_header_t *alib;
539 acpi_hest_t *hest;
540
541 /* HEST */
542 current = ALIGN(current, 8);
543 hest = (acpi_hest_t *)current;
544 acpi_write_hest((void *)current, acpi_fill_hest);
545 acpi_add_table(rsdp, (void *)current);
546 current += ((acpi_header_t *)current)->length;
547
548 /* SRAT */
549 current = ALIGN(current, 8);
550 printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
551 srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
552 if (srat != NULL) {
553 memcpy((void *)current, srat, srat->header.length);
554 srat = (acpi_srat_t *) current;
555 //acpi_create_srat(srat);
556 current += srat->header.length;
557 acpi_add_table(rsdp, srat);
558 }
559
560 /* SLIT */
561 current = ALIGN(current, 8);
562 printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
563 slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
564 if (slit != NULL) {
565 memcpy((void *)current, slit, slit->header.length);
566 slit = (acpi_slit_t *) current;
567 //acpi_create_slit(slit);
568 current += slit->header.length;
569 acpi_add_table(rsdp, slit);
570 }
571
572 /* SSDT */
573 current = ALIGN(current, 16);
574 printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
575 alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
576 if (alib != NULL) {
577 memcpy((void *)current, alib, alib->length);
578 alib = (acpi_header_t *) current;
579 current += alib->length;
580 acpi_add_table(rsdp, (void *)alib);
581 } else {
582 printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
583 }
584
585 /* The DSDT needs additional work for the AGESA SSDT Pstate table */
586 /* Keep the comment for a while. */
587 current = ALIGN(current, 16);
588 printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current);
589 ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
590 if (ssdt != NULL) {
591 memcpy((void *)current, ssdt, ssdt->length);
592 ssdt = (acpi_header_t *) current;
593 current += ssdt->length;
594 acpi_add_table(rsdp,ssdt);
595 } else {
596 printk(BIOS_DEBUG, " AGESA SSDT Pstate table NULL. Skipping.\n");
597 }
598
599 return current;
600 }
601
602
603 static struct device_operations northbridge_operations = {
604 .read_resources = nb_read_resources,
605 .set_resources = nb_set_resources,
606 .enable_resources = pci_dev_enable_resources,
607 .init = DEVICE_NOOP,
608 .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
609 .write_acpi_tables = agesa_write_acpi_tables,
610 .scan_bus = scan_chains,
611 .enable = 0,
612 .ops_pci = 0,
613 };
614
615 static const struct pci_driver family15_northbridge __pci_driver = {
616 .ops = &northbridge_operations,
617 .vendor = PCI_VENDOR_ID_AMD,
618 .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT,
619 };
620
621 static const struct pci_driver family10_northbridge __pci_driver = {
622 .ops = &northbridge_operations,
623 .vendor = PCI_VENDOR_ID_AMD,
624 .device = PCI_DEVICE_ID_AMD_10H_NB_HT,
625 };
626
627 struct chip_operations northbridge_amd_agesa_family15_ops = {
628 CHIP_NAME("AMD FAM15 Northbridge")
629 .enable_dev = 0,
630 };
631
632 static void domain_read_resources(device_t dev)
633 {
634 unsigned reg;
635
636 /* Find the already assigned resource pairs */
637 get_fx_devs();
638 for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
639 u32 base, limit;
640 base = f1_read_config32(reg);
641 limit = f1_read_config32(reg + 0x04);
642 /* Is this register allocated? */
643 if ((base & 3) != 0) {
644 unsigned nodeid, reg_link;
645 device_t reg_dev;
646 if (reg<0xc0) { // mmio
647 nodeid = (limit & 0xf) + (base&0x30);
648 } else { // io
649 nodeid = (limit & 0xf) + ((base>>4)&0x30);
650 }
651 reg_link = (limit >> 4) & 7;
652 reg_dev = __f0_dev[nodeid];
653 if (reg_dev) {
654 /* Reserve the resource */
655 struct resource *res;
656 res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
657 if (res) {
658 res->flags = 1;
659 }
660 }
661 }
662 }
663 /* FIXME: do we need to check extend conf space?
664 I don't believe that much preset value */
665
666 #if !CONFIG_PCI_64BIT_PREF_MEM
667 pci_domain_read_resources(dev);
668
669 #else
670 struct bus *link;
671 struct resource *resource;
672 for (link=dev->link_list; link; link = link->next) {
673 /* Initialize the system wide io space constraints */
674 resource = new_resource(dev, 0|(link->link_num<<2));
675 resource->base = 0x400;
676 resource->limit = 0xffffUL;
677 resource->flags = IORESOURCE_IO;
678
679 /* Initialize the system wide prefetchable memory resources constraints */
680 resource = new_resource(dev, 1|(link->link_num<<2));
681 resource->limit = 0xfcffffffffULL;
682 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
683
684 /* Initialize the system wide memory resources constraints */
685 resource = new_resource(dev, 2|(link->link_num<<2));
686 resource->limit = 0xfcffffffffULL;
687 resource->flags = IORESOURCE_MEM;
688 }
689 #endif
690 }
691
692 static void domain_enable_resources(device_t dev)
693 {
694 /* Must be called after PCI enumeration and resource allocation */
695 printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);
696
697 #if CONFIG_AMD_SB_CIMX
698 sb_After_Pci_Init();
699 #endif
700 /* Enable MMIO on AMD CPU Address Map Controller */
701 amd_initcpuio();
702
703 agesawrapper_amdinitmid();
704 printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__);
705 }
706
707 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
708 struct hw_mem_hole_info {
709 unsigned hole_startk;
710 int node_id;
711 };
712 static struct hw_mem_hole_info get_hw_mem_hole_info(void)
713 {
714 struct hw_mem_hole_info mem_hole;
715 int i;
716 mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
717 mem_hole.node_id = -1;
718 for (i = 0; i < node_nums; i++) {
719 dram_base_mask_t d;
720 u32 hole;
721 d = get_dram_base_mask(i);
722 if (!(d.mask & 1)) continue; // no memory on this node
723 hole = pci_read_config32(__f1_dev[i], 0xf0);
724 if (hole & 1) { // we find the hole
725 mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
726 mem_hole.node_id = i; // record the node No with hole
727 break; // only one hole
728 }
729 }
730
731 /* We need to double check if there is special set on base reg and limit reg
732 * are not continuous instead of hole, it will find out its hole_startk.
733 */
734 if (mem_hole.node_id == -1) {
735 resource_t limitk_pri = 0;
736 for (i=0; i<node_nums; i++) {
737 dram_base_mask_t d;
738 resource_t base_k, limit_k;
739 d = get_dram_base_mask(i);
740 if (!(d.base & 1)) continue;
741 base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
742 if (base_k > 4 *1024 * 1024) break; // don't need to go to check
743 if (limitk_pri != base_k) { // we find the hole
744 mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
745 mem_hole.node_id = i;
746 break; //only one hole
747 }
748 limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
749 limitk_pri = limit_k;
750 }
751 }
752 return mem_hole;
753 }
754 #endif
755
756 #define ONE_MB_SHIFT 20
757
758 static void setup_uma_memory(void)
759 {
760 #if CONFIG_GFXUMA
761 uint32_t topmem = (uint32_t) bsp_topmem();
762 uint32_t sys_mem;
763
764 /* refer to UMA Size Consideration in Family15h BKDG. */
765 /* Please reference MemNGetUmaSizeOR () */
766 /*
767 * Total system memory UMASize
768 * >= 2G 512M
769 * >=1G 256M
770 * <1G 64M
771 */
772 sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size
773 if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) {
774 uma_memory_size = 512 << ONE_MB_SHIFT;
775 } else if (sys_mem >= 1024 << ONE_MB_SHIFT) {
776 uma_memory_size = 256 << ONE_MB_SHIFT;
777 } else {
778 uma_memory_size = 64 << ONE_MB_SHIFT;
779 }
780 uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */
781
782 printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
783 __func__, uma_memory_size, uma_memory_base);
784 #endif
785 }
786
787
788 static void domain_set_resources(device_t dev)
789 {
790 #if CONFIG_PCI_64BIT_PREF_MEM
791 struct resource *io, *mem1, *mem2;
792 struct resource *res;
793 #endif
794 unsigned long mmio_basek;
795 u32 pci_tolm;
796 u64 ramtop = 0;
797 int i, idx;
798 struct bus *link;
799 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
800 struct hw_mem_hole_info mem_hole;
801 u32 reset_memhole = 1;
802 #endif
803
804 #if CONFIG_PCI_64BIT_PREF_MEM
805
806 for (link = dev->link_list; link; link = link->next) {
807 /* Now reallocate the pci resources memory with the
808 * highest addresses I can manage.
809 */
810 mem1 = find_resource(dev, 1|(link->link_num<<2));
811 mem2 = find_resource(dev, 2|(link->link_num<<2));
812
813 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
814 mem1->base, mem1->limit, mem1->size, mem1->align);
815 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
816 mem2->base, mem2->limit, mem2->size, mem2->align);
817
818 /* See if both resources have roughly the same limits */
819 if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
820 ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
821 {
822 /* If so place the one with the most stringent alignment first */
823 if (mem2->align > mem1->align) {
824 struct resource *tmp;
825 tmp = mem1;
826 mem1 = mem2;
827 mem2 = tmp;
828 }
829 /* Now place the memory as high up as it will go */
830 mem2->base = resource_max(mem2);
831 mem1->limit = mem2->base - 1;
832 mem1->base = resource_max(mem1);
833 }
834 else {
835 /* Place the resources as high up as they will go */
836 mem2->base = resource_max(mem2);
837 mem1->base = resource_max(mem1);
838 }
839
840 printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
841 mem1->base, mem1->limit, mem1->size, mem1->align);
842 printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
843 mem2->base, mem2->limit, mem2->size, mem2->align);
844 }
845
846 for (res = &dev->resource_list; res; res = res->next)
847 {
848 res->flags |= IORESOURCE_ASSIGNED;
849 res->flags |= IORESOURCE_STORED;
850 report_resource_stored(dev, res, "");
851 }
852 #endif
853
854 pci_tolm = 0xffffffffUL;
855 for (link = dev->link_list; link; link = link->next) {
856 pci_tolm = find_pci_tolm(link);
857 }
858
859 // FIXME handle interleaved nodes. If you fix this here, please fix
860 // amdk8, too.
861 mmio_basek = pci_tolm >> 10;
862 /* Round mmio_basek to something the processor can support */
863 mmio_basek &= ~((1 << 6) -1);
864
865 // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
866 // MMIO hole. If you fix this here, please fix amdk8, too.
867 /* Round the mmio hole to 64M */
868 mmio_basek &= ~((64*1024) - 1);
869
870 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
871 /* if the hw mem hole is already set in raminit stage, here we will compare
872 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
873 * use hole_basek as mmio_basek and we don't need to reset hole.
874 * otherwise We reset the hole to the mmio_basek
875 */
876
877 mem_hole = get_hw_mem_hole_info();
878
879 // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
880 if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
881 mmio_basek = mem_hole.hole_startk;
882 reset_memhole = 0;
883 }
884 #endif
885
886 idx = 0x10;
887 for (i = 0; i < node_nums; i++) {
888 dram_base_mask_t d;
889 resource_t basek, limitk, sizek; // 4 1T
890
891 d = get_dram_base_mask(i);
892
893 if (!(d.mask & 1)) continue;
894 basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
895 limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9;
896
897 sizek = limitk - basek;
898
899 /* see if we need a hole from 0xa0000 to 0xbffff */
900 if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
901 ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
902 idx += 0x10;
903 basek = (8*64)+(16*16);
904 sizek = limitk - ((8*64)+(16*16));
905
906 }
907
908 //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
909
910 /* split the region to accommodate pci memory space */
911 if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
912 if (basek <= mmio_basek) {
913 unsigned pre_sizek;
914 pre_sizek = mmio_basek - basek;
915 if (pre_sizek>0) {
916 ram_resource(dev, (idx | i), basek, pre_sizek);
917 idx += 0x10;
918 sizek -= pre_sizek;
919 if (!ramtop)
920 ramtop = mmio_basek * 1024;
921 }
922 basek = mmio_basek;
923 }
924 if ((basek + sizek) <= 4*1024*1024) {
925 sizek = 0;
926 }
927 else {
928 basek = 4*1024*1024;
929 sizek -= (4*1024*1024 - mmio_basek);
930 }
931 }
932
933 ram_resource(dev, (idx | i), basek, sizek);
934 idx += 0x10;
935 printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
936 i, mmio_basek, basek, limitk);
937 if (!ramtop)
938 ramtop = limitk * 1024;
939 }
940
941 #if CONFIG_GFXUMA
942 set_top_of_ram(uma_memory_base);
943 uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
944 #else
945 set_top_of_ram(ramtop);
946 #endif
947
948 for(link = dev->link_list; link; link = link->next) {
949 if (link->children) {
950 assign_resources(link);
951 }
952 }
953 }
954
955 /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */
956 static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int unused)
957 {
958 struct bus *link = dev->link_list;
959 pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff);
960 return unused;
961 }
962
963 static struct device_operations pci_domain_ops = {
964 .read_resources = domain_read_resources,
965 .set_resources = domain_set_resources,
966 .enable_resources = domain_enable_resources,
967 .init = DEVICE_NOOP,
968 .scan_bus = f15_pci_domain_scan_bus,
969 .ops_pci_bus = pci_bus_default_ops,
970 };
971
972 static void sysconf_init(device_t dev) // first node
973 {
974 sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
975 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
976 }
977
978 static void add_more_links(device_t dev, unsigned total_links)
979 {
980 struct bus *link, *last = NULL;
981 int link_num;
982
983 for (link = dev->link_list; link; link = link->next)
984 last = link;
985
986 if (last) {
987 int links = total_links - last->link_num;
988 link_num = last->link_num;
989 if (links > 0) {
990 link = malloc(links*sizeof(*link));
991 if (!link)
992 die("Couldn't allocate more links!\n");
993 memset(link, 0, links*sizeof(*link));
994 last->next = link;
995 }
996 }
997 else {
998 link_num = -1;
999 link = malloc(total_links*sizeof(*link));
1000 memset(link, 0, total_links*sizeof(*link));
1001 dev->link_list = link;
1002 }
1003
1004 for (link_num = link_num + 1; link_num < total_links; link_num++) {
1005 link->link_num = link_num;
1006 link->dev = dev;
1007 link->next = link + 1;
1008 last = link;
1009 link = link->next;
1010 }
1011 last->next = NULL;
1012 }
1013
1014 static u32 cpu_bus_scan(device_t dev, u32 passthru)
1015 {
1016 struct bus *cpu_bus;
1017 device_t dev_mc;
1018 #if CONFIG_CBB
1019 device_t pci_domain;
1020 #endif
1021 int i,j;
1022 int coreid_bits;
1023 int core_max = 0;
1024 unsigned ApicIdCoreIdSize;
1025 unsigned core_nums;
1026 int siblings = 0;
1027 unsigned int family;
1028
1029 #if CONFIG_CBB
1030 dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
1031 if (dev_mc && dev_mc->bus) {
1032 printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
1033 pci_domain = dev_mc->bus->dev;
1034 if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
1035 printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
1036 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
1037 printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
1038 } else {
1039 printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
1040 }
1041 printk(BIOS_DEBUG, "\n");
1042 }
1043 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
1044 if (!dev_mc) {
1045 dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
1046 if (dev_mc && dev_mc->bus) {
1047 printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
1048 pci_domain = dev_mc->bus->dev;
1049 if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) {
1050 if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
1051 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
1052 dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
1053 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
1054 while (dev_mc) {
1055 printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
1056 dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
1057 printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
1058 dev_mc = dev_mc->sibling;
1059 }
1060 }
1061 }
1062 }
1063 }
1064 #endif
1065 dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
1066 if (!dev_mc) {
1067 printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
1068 die("");
1069 }
1070 sysconf_init(dev_mc);
1071 #if CONFIG_CBB && (MAX_NODE_NUMS > 32)
1072 if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
1073 if (pci_domain->link_list && !pci_domain->link_list->next) {
1074 struct bus *new_link = new_link(pci_domain);
1075 pci_domain->link_list->next = new_link;
1076 new_link->link_num = 1;
1077 new_link->dev = pci_domain;
1078 new_link->children = 0;
1079 printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
1080 }
1081 pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
1082 }
1083 #endif
1084
1085 /* Get Max Number of cores(MNC) */
1086 coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
1087 core_max = 1 << (coreid_bits & 0x000F); //mnc
1088
1089 ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
1090 if (ApicIdCoreIdSize) {
1091 core_nums = (1 << ApicIdCoreIdSize) - 1;
1092 } else {
1093 core_nums = 3; //quad core
1094 }
1095
1096 /* Find which cpus are present */
1097 cpu_bus = dev->link_list;
1098 for (i = 0; i < node_nums; i++) {
1099 device_t cdb_dev;
1100 unsigned busn, devn;
1101 struct bus *pbus;
1102
1103 busn = CONFIG_CBB;
1104 devn = CONFIG_CDB + i;
1105 pbus = dev_mc->bus;
1106 #if CONFIG_CBB && (MAX_NODE_NUMS > 32)
1107 if (i >= 32) {
1108 busn--;
1109 devn -= 32;
1110 pbus = pci_domain->link_list->next;
1111 }
1112 #endif
1113
1114 /* Find the cpu's pci device */
1115 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1116 if (!cdb_dev) {
1117 /* If I am probing things in a weird order
1118 * ensure all of the cpu's pci devices are found.
1119 */
1120 int fn;
1121 for(fn = 0; fn <= 5; fn++) { //FBDIMM?
1122 cdb_dev = pci_probe_dev(NULL, pbus,
1123 PCI_DEVFN(devn, fn));
1124 }
1125 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
1126 } else {
1127 /* Ok, We need to set the links for that device.
1128 * otherwise the device under it will not be scanned
1129 */
1130 add_more_links(cdb_dev, 8);
1131 }
1132
1133 family = cpuid_eax(1);
1134 family = (family >> 20) & 0xFF;
1135 if (family == 1) { //f10
1136 u32 dword;
1137 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
1138 dword = pci_read_config32(cdb_dev, 0xe8);
1139 siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
1140 } else if (family == 6) {//f15
1141 cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5));
1142 if (cdb_dev && cdb_dev->enabled) {
1143 siblings = pci_read_config32(cdb_dev, 0x84);
1144 siblings &= 0xFF;
1145 }
1146 } else {
1147 siblings = 0; //default one core
1148 }
1149 int enable_node = cdb_dev && cdb_dev->enabled;
1150 printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
1151 dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
1152
1153 for (j = 0; j <= siblings; j++ ) {
1154 u32 lapicid_start = 0;
1155
1156 /*
1157 * APIC ID calucation is tightly coupled with AGESA v5 code.
1158 * This calculation MUST match the assignment calculation done
1159 * in LocalApicInitializationAtEarly() function.
1160 * And reference GetLocalApicIdForCore()
1161 *
1162 * Apply apic enumeration rules
1163 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
1164 * put the local-APICs at m..z
1165 *
1166 * This is needed because many IO-APIC devices only have 4 bits
1167 * for their APIC id and therefore must reside at 0..15
1168 */
1169 #ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
1170 #define CFG_PLAT_NUM_IO_APICS 3
1171 #endif
1172 if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
1173 lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
1174 lapicid_start = (lapicid_start + 1) * core_max;
1175 printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
1176 }
1177 #if CONFIG_CPU_AMD_SOCKET_G34
1178 u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0);
1179 #else
1180 u32 apic_id = (i * core_max) + j + lapicid_start;
1181 #endif
1182 printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
1183 i, j, apic_id);
1184
1185 device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1186 if (cpu)
1187 amd_cpu_topology(cpu, i, j);
1188 } //j
1189 }
1190 return passthru;
1191 }
1192
1193 static void cpu_bus_init(device_t dev)
1194 {
1195 initialize_cpus(dev->link_list);
1196 }
1197
1198 static struct device_operations cpu_bus_ops = {
1199 .read_resources = DEVICE_NOOP,
1200 .set_resources = DEVICE_NOOP,
1201 .enable_resources = DEVICE_NOOP,
1202 .init = cpu_bus_init,
1203 .scan_bus = cpu_bus_scan,
1204 };
1205
1206 static void root_complex_enable_dev(struct device *dev)
1207 {
1208 static int done = 0;
1209
1210 /* Do not delay UMA setup, as a device on the PCI bus may evaluate
1211 the global uma_memory variables already in its enable function. */
1212 if (!done) {
1213 setup_bsp_ramtop();
1214 setup_uma_memory();
1215 done = 1;
1216 }
1217
1218 /* Set the operations if it is a special bus type */
1219 if (dev->path.type == DEVICE_PATH_DOMAIN) {
1220 dev->ops = &pci_domain_ops;
1221 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
1222 dev->ops = &cpu_bus_ops;
1223 }
1224 }
1225
1226 struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = {
1227 CHIP_NAME("AMD FAM15 Root Complex")
1228 .enable_dev = root_complex_enable_dev,
1229 };
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