2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
20 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <pc80/mc146818rtc.h>
28 #include <drivers/intel/gma/edid.h>
29 #include <drivers/intel/gma/i915.h>
32 #include <pc80/vga_io.h>
39 #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
40 #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
41 #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
42 #define DISPPLANE_BGRX888 (0x6<<26)
43 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
45 #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
47 #define PGETBL_CTL 0x2020
48 #define PGETBL_ENABLED 0x00000001
50 #define BASE_FREQUENCY 120000
52 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
54 static int gtt_setup(void *mmiobase
)
56 unsigned long PGETBL_save
;
57 unsigned long tom
; // top of memory
60 * The Video BIOS places the GTT right below top of memory.
62 tom
= pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD
) << 24;
63 PGETBL_save
= tom
- 256 * KiB
;
64 PGETBL_save
|= PGETBL_ENABLED
;
65 PGETBL_save
|= 2; /* set GTT to 256kb */
67 write32(mmiobase
+ GFX_FLSH_CNTL
, 0);
69 write32(mmiobase
+ PGETBL_CTL
, PGETBL_save
);
72 if (read32(mmiobase
+ PGETBL_CTL
) & PGETBL_ENABLED
) {
73 printk(BIOS_DEBUG
, "gtt_setup is enabled.\n");
75 printk(BIOS_DEBUG
, "gtt_setup failed!!!\n");
78 write32(mmiobase
+ GFX_FLSH_CNTL
, 0);
83 static int intel_gma_init(struct northbridge_intel_i945_config
*conf
,
84 unsigned int pphysbase
, unsigned int piobase
,
85 void *pmmio
, unsigned int pgfx
)
90 int hpolarity
, vpolarity
;
92 u32 best_delta
= 0xffffffff;
98 u32 hactive
, vactive
, right_border
, bottom_border
;
99 u32 vsync
, hsync
, vblank
, hblank
, hfront_porch
, vfront_porch
;
105 "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
106 (void *)pgfx
, pmmio
, piobase
, pphysbase
);
108 intel_gmbus_read_edid(pmmio
+ GMBUS0
, 3, 0x50, edid_data
, 128);
109 decode_edid(edid_data
, sizeof(edid_data
), &edid
);
111 hpolarity
= (edid
.phsync
== '-');
112 vpolarity
= (edid
.pvsync
== '-');
113 hactive
= edid
.x_resolution
;
114 vactive
= edid
.y_resolution
;
115 right_border
= edid
.hborder
;
116 bottom_border
= edid
.vborder
;
121 hfront_porch
= edid
.hso
;
122 vfront_porch
= edid
.vso
;
124 for (i
= 0; i
< 2; i
++)
125 for (j
= 0; j
< 0x100; j
++)
127 write32(pmmio
+ PALETTE(i
) + 4 * j
, 0x10101 * j
);
129 write32(pmmio
+ PCH_PP_CONTROL
, PANEL_UNLOCK_REGS
130 | (read32(pmmio
+ PCH_PP_CONTROL
) & ~PANEL_UNLOCK_MASK
));
132 write32(pmmio
+ MI_ARB_STATE
, MI_ARB_C3_LP_WRITE_ENABLE
| (1 << 27));
133 /* Clean registers. */
134 for (i
= 0; i
< 0x20; i
+= 4)
135 write32(pmmio
+ RENDER_RING_BASE
+ i
, 0);
136 for (i
= 0; i
< 0x20; i
+= 4)
137 write32(pmmio
+ FENCE_REG_965_0
+ i
, 0);
138 write32(pmmio
+ PP_ON_DELAYS
, 0);
139 write32(pmmio
+ PP_OFF_DELAYS
, 0);
142 write32(pmmio
+ VGACNTRL
, VGA_DISP_DISABLE
);
145 write32(pmmio
+ PIPECONF(0), 0);
146 write32(pmmio
+ PIPECONF(1), 0);
149 write32(pmmio
+ HWS_PGA
, 0x352d2000);
150 write32(pmmio
+ PRB0_CTL
, 0);
151 write32(pmmio
+ PRB0_HEAD
, 0);
152 write32(pmmio
+ PRB0_TAIL
, 0);
153 write32(pmmio
+ PRB0_START
, 0);
154 write32(pmmio
+ PRB0_CTL
, 0x0001f001);
156 write32(pmmio
+ D_STATE
, DSTATE_PLL_D3_OFF
157 | DSTATE_GFX_CLOCK_GATING
| DSTATE_DOT_CLOCK_GATING
);
158 write32(pmmio
+ ECOSKPD
, 0x00010000);
159 write32(pmmio
+ HWSTAM
, 0xeffe);
160 write32(pmmio
+ PORT_HOTPLUG_EN
, conf
->gpu_hotplug
);
161 write32(pmmio
+ INSTPM
, 0x08000000 | INSTPM_AGPBUSY_DIS
);
163 target_frequency
= conf
->gpu_lvds_is_dual_channel
? edid
.pixel_clock
164 : (2 * edid
.pixel_clock
);
166 /* Find suitable divisors. */
167 for (candp1
= 1; candp1
<= 8; candp1
++) {
168 for (candn
= 5; candn
<= 10; candn
++) {
170 u32 m
; /* 77 - 131. */
171 u32 denom
; /* 35 - 560. */
174 denom
= candn
* candp1
* 7;
175 /* Doesnt overflow for up to
176 5000000 kHz = 5 GHz. */
177 m
= (target_frequency
* denom
178 + BASE_FREQUENCY
/ 2) / BASE_FREQUENCY
;
180 if (m
< 77 || m
> 131)
183 cur_frequency
= (BASE_FREQUENCY
* m
) / denom
;
184 if (target_frequency
> cur_frequency
)
185 current_delta
= target_frequency
- cur_frequency
;
187 current_delta
= cur_frequency
- target_frequency
;
189 if (best_delta
> current_delta
) {
190 best_delta
= current_delta
;
193 pixel_m2
= ((m
+ 3) % 5) + 7;
194 pixel_m1
= (m
- pixel_m2
) / 5;
199 if (best_delta
== 0xffffffff) {
200 printk (BIOS_ERR
, "Couldn't find GFX clock divisors\n");
204 printk(BIOS_INFO
, "bringing up panel at resolution %d x %d\n",
206 printk(BIOS_DEBUG
, "Borders %d x %d\n", right_border
, bottom_border
);
207 printk(BIOS_DEBUG
, "Blank %d x %d\n", hblank
, vblank
);
208 printk(BIOS_DEBUG
, "Sync %d x %d\n", hsync
, vsync
);
209 printk(BIOS_DEBUG
, "Front porch %d x %d\n", hfront_porch
, vfront_porch
);
210 printk(BIOS_DEBUG
, (conf
->gpu_lvds_use_spread_spectrum_clock
211 ? "Spread spectrum clock\n"
213 printk(BIOS_DEBUG
, (conf
->gpu_lvds_is_dual_channel
215 : "Single channel\n"));
216 printk(BIOS_DEBUG
, "Polarities %d, %d\n",
217 hpolarity
, vpolarity
);
218 printk(BIOS_DEBUG
, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
219 pixel_n
, pixel_m1
, pixel_m2
, pixel_p1
);
220 printk(BIOS_DEBUG
, "Pixel clock %d kHz\n",
221 BASE_FREQUENCY
* (5 * pixel_m1
+ pixel_m2
) / pixel_n
224 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
225 write32(pmmio
+ PF_WIN_SZ(0), vactive
| (hactive
<< 16));
226 write32(pmmio
+ PF_WIN_POS(0), 0);
227 write32(pmmio
+ PF_CTL(0),PF_ENABLE
| PF_FILTER_MED_3x3
);
228 write32(pmmio
+ PFIT_CONTROL
, PFIT_ENABLE
| (1 << PFIT_PIPE_SHIFT
) | HORIZ_AUTO_SCALE
| VERT_AUTO_SCALE
);
230 /* Disable panel fitter (we're in native resolution). */
231 write32(pmmio
+ PF_CTL(0), 0);
232 write32(pmmio
+ PF_WIN_SZ(0), 0);
233 write32(pmmio
+ PF_WIN_POS(0), 0);
234 write32(pmmio
+ PFIT_PGM_RATIOS
, 0);
235 write32(pmmio
+ PFIT_CONTROL
, 0);
240 write32(pmmio
+ DSPCNTR(0), DISPPLANE_BGRX888
241 | DISPPLANE_SEL_PIPE_B
| DISPPLANE_GAMMA_ENABLE
);
244 write32(pmmio
+ PP_CONTROL
, PANEL_UNLOCK_REGS
245 | (read32(pmmio
+ PP_CONTROL
) & ~PANEL_UNLOCK_MASK
));
246 write32(pmmio
+ FP0(1),
247 ((pixel_n
- 2) << 16)
248 | ((pixel_m1
- 2) << 8) | pixel_m2
);
249 write32(pmmio
+ DPLL(1),
251 DPLL_VCO_ENABLE
| DPLLB_MODE_LVDS
252 | (conf
->gpu_lvds_is_dual_channel
? DPLLB_LVDS_P2_CLOCK_DIV_7
253 : DPLLB_LVDS_P2_CLOCK_DIV_14
)
254 | (conf
->gpu_lvds_use_spread_spectrum_clock
255 ? DPLL_INTEGRATED_CLOCK_VLV
| DPLL_INTEGRATED_CRI_CLK_VLV
260 write32(pmmio
+ DPLL(1),
262 DPLL_VCO_ENABLE
| DPLLB_MODE_LVDS
263 | (conf
->gpu_lvds_is_dual_channel
? DPLLB_LVDS_P2_CLOCK_DIV_7
264 : DPLLB_LVDS_P2_CLOCK_DIV_14
)
265 | ((conf
->gpu_lvds_use_spread_spectrum_clock
? 3 : 0) << 13)
269 write32(pmmio
+ HTOTAL(1),
270 ((hactive
+ right_border
+ hblank
- 1) << 16)
272 write32(pmmio
+ HBLANK(1),
273 ((hactive
+ right_border
+ hblank
- 1) << 16)
274 | (hactive
+ right_border
- 1));
275 write32(pmmio
+ HSYNC(1),
276 ((hactive
+ right_border
+ hfront_porch
+ hsync
- 1) << 16)
277 | (hactive
+ right_border
+ hfront_porch
- 1));
279 write32(pmmio
+ VTOTAL(1), ((vactive
+ bottom_border
+ vblank
- 1) << 16)
281 write32(pmmio
+ VBLANK(1), ((vactive
+ bottom_border
+ vblank
- 1) << 16)
282 | (vactive
+ bottom_border
- 1));
283 write32(pmmio
+ VSYNC(1),
284 (vactive
+ bottom_border
+ vfront_porch
+ vsync
- 1)
285 | (vactive
+ bottom_border
+ vfront_porch
- 1));
287 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
288 write32(pmmio
+ PIPESRC(1), (639 << 16) | 399);
290 write32(pmmio
+ PIPESRC(1), ((hactive
- 1) << 16) | (vactive
- 1));
294 write32(pmmio
+ DSPSIZE(0), (hactive
- 1) | ((vactive
- 1) << 16));
295 write32(pmmio
+ DSPPOS(0), 0);
297 /* Backlight init. */
298 write32(pmmio
+ FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
);
299 write32(pmmio
+ FW_BLC
, 0x011d011a);
300 write32(pmmio
+ FW_BLC2
, 0x00000102);
301 write32(pmmio
+ FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
);
302 write32(pmmio
+ FW_BLC_SELF
, 0x0001003f);
303 write32(pmmio
+ FW_BLC
, 0x011d0109);
304 write32(pmmio
+ FW_BLC2
, 0x00000102);
305 write32(pmmio
+ FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
);
306 write32(pmmio
+ BLC_PWM_CTL
, conf
->gpu_backlight
);
308 edid
.bytes_per_line
= (edid
.bytes_per_line
+ 63) & ~63;
309 write32(pmmio
+ DSPADDR(0), 0);
310 write32(pmmio
+ DSPSURF(0), 0);
311 write32(pmmio
+ DSPSTRIDE(0), edid
.bytes_per_line
);
312 write32(pmmio
+ DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888
313 | DISPPLANE_SEL_PIPE_B
| DISPPLANE_GAMMA_ENABLE
);
316 write32(pmmio
+ PIPECONF(1), PIPECONF_ENABLE
);
317 write32(pmmio
+ LVDS
, LVDS_ON
318 | (hpolarity
<< 20) | (vpolarity
<< 21)
319 | (conf
->gpu_lvds_is_dual_channel
? LVDS_CLOCK_B_POWERUP_ALL
320 | LVDS_CLOCK_BOTH_POWERUP_ALL
: 0)
321 | LVDS_CLOCK_A_POWERUP_ALL
324 write32(pmmio
+ PP_CONTROL
, PANEL_UNLOCK_REGS
| PANEL_POWER_OFF
);
325 write32(pmmio
+ PP_CONTROL
, PANEL_UNLOCK_REGS
| PANEL_POWER_RESET
);
327 write32(pmmio
+ PP_CONTROL
, PANEL_UNLOCK_REGS
328 | PANEL_POWER_ON
| PANEL_POWER_RESET
);
330 printk (BIOS_DEBUG
, "waiting for panel powerup\n");
333 reg32
= read32(pmmio
+ PP_STATUS
);
334 if ((reg32
& PP_SEQUENCE_MASK
) == PP_SEQUENCE_NONE
)
337 printk (BIOS_DEBUG
, "panel powered up\n");
339 write32(pmmio
+ PP_CONTROL
, PANEL_POWER_ON
| PANEL_POWER_RESET
);
341 /* Clear interrupts. */
342 write32(pmmio
+ DEIIR
, 0xffffffff);
343 write32(pmmio
+ SDEIIR
, 0xffffffff);
344 write32(pmmio
+ IIR
, 0xffffffff);
345 write32(pmmio
+ IMR
, 0xffffffff);
346 write32(pmmio
+ EIR
, 0xffffffff);
348 if (gtt_setup(pmmio
)) {
349 printk(BIOS_ERR
, "ERROR: GTT Setup Failed!!!\n");
355 reg16
= pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC
);
369 printk(BIOS_DEBUG
, "%dM UMA\n", uma_size
>> 10);
372 for (i
= 0; i
< (uma_size
- 256) / 4; i
++)
374 outl((i
<< 2) | 1, piobase
);
375 outl(pphysbase
+ (i
<< 12) + 1, piobase
+ 4);
378 temp
= read32(pmmio
+ PGETBL_CTL
);
379 printk(BIOS_INFO
, "GTT PGETBL_CTL register: 0x%lx\n", temp
);
382 printk(BIOS_INFO
, "GTT Enabled\n");
384 printk(BIOS_ERR
, "ERROR: GTT is still Disabled!!!\n");
386 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
387 vga_misc_write(0x67);
389 write32(pmmio
+ DSPCNTR(0), DISPPLANE_SEL_PIPE_B
);
391 write32(pmmio
+ VGACNTRL
, 0x02c4008e | VGA_PIPE_B_SELECT
);
395 printk(BIOS_SPEW
, "memset %p to 0x00 for %d bytes\n",
396 (void *)pgfx
, hactive
* vactive
* 4);
397 memset((void *)pgfx
, 0x00, hactive
* vactive
* 4);
399 set_vbe_mode_info_valid(&edid
, pgfx
);
405 static void gma_func0_init(struct device
*dev
)
409 /* Unconditionally reset graphics */
410 pci_write_config8(dev
, GDRST
, 1);
412 pci_write_config8(dev
, GDRST
, 0);
413 /* wait for device to finish */
414 while (pci_read_config8(dev
, GDRST
) & 1) { };
416 /* IGD needs to be Bus Master */
417 reg32
= pci_read_config32(dev
, PCI_COMMAND
);
418 pci_write_config32(dev
, PCI_COMMAND
, reg32
| PCI_COMMAND_MASTER
419 | PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
);
421 #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
422 /* PCI Init, will run VBIOS */
427 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
428 /* This should probably run before post VBIOS init. */
429 printk(BIOS_SPEW
, "Initializing VGA without OPROM.\n");
431 u32 iobase
, graphics_base
;
432 struct northbridge_intel_i945_config
*conf
= dev
->chip_info
;
434 iobase
= dev
->resource_list
[1].base
;
435 mmiobase
= (void *)(uintptr_t)dev
->resource_list
[0].base
;
436 graphics_base
= dev
->resource_list
[2].base
;
438 printk(BIOS_SPEW
, "GMADR=0x%08x GTTADR=0x%08x\n",
439 pci_read_config32(dev
, GMADR
),
440 pci_read_config32(dev
, GTTADR
)
444 err
= intel_gma_init(conf
, pci_read_config32(dev
, 0x5c) & ~0xf,
445 iobase
, mmiobase
, graphics_base
);
447 gfx_set_init_done(1);
451 /* This doesn't reclaim stolen UMA memory, but IGD could still
452 be reenabled later. */
453 static void gma_func0_disable(struct device
*dev
)
455 struct device
*dev_host
= dev_find_slot(0, PCI_DEVFN(0x0, 0));
457 pci_write_config16(dev
, GCFC
, 0xa00);
458 pci_write_config16(dev_host
, GGC
, (1 << 1));
460 unsigned int reg32
= pci_read_config32(dev_host
, DEVEN
);
461 reg32
&= ~(DEVEN_D2F0
| DEVEN_D2F1
);
462 pci_write_config32(dev_host
, DEVEN
, reg32
);
467 static void gma_func1_init(struct device
*dev
)
471 /* IGD needs to be Bus Master, also enable IO accesss */
472 reg32
= pci_read_config32(dev
, PCI_COMMAND
);
473 pci_write_config32(dev
, PCI_COMMAND
, reg32
|
474 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
);
476 /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */
477 pci_write_config8(dev
, 0xf4, 0xff);
480 static void gma_set_subsystem(device_t dev
, unsigned vendor
, unsigned device
)
482 if (!vendor
|| !device
) {
483 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
484 pci_read_config32(dev
, PCI_VENDOR_ID
));
486 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
487 ((device
& 0xffff) << 16) | (vendor
& 0xffff));
491 const struct i915_gpu_controller_info
*
492 intel_gma_get_controller_info(void)
494 device_t dev
= dev_find_slot(0, PCI_DEVFN(0x2,0));
498 struct northbridge_intel_i945_config
*chip
= dev
->chip_info
;
502 static void gma_ssdt(void)
504 const struct i915_gpu_controller_info
*gfx
= intel_gma_get_controller_info();
509 drivers_intel_gma_displays_ssdt_generate(gfx
);
512 static struct pci_operations gma_pci_ops
= {
513 .set_subsystem
= gma_set_subsystem
,
516 static struct device_operations gma_func0_ops
= {
517 .read_resources
= pci_dev_read_resources
,
518 .set_resources
= pci_dev_set_resources
,
519 .enable_resources
= pci_dev_enable_resources
,
520 .init
= gma_func0_init
,
521 .acpi_fill_ssdt_generator
= gma_ssdt
,
524 .disable
= gma_func0_disable
,
525 .ops_pci
= &gma_pci_ops
,
529 static struct device_operations gma_func1_ops
= {
530 .read_resources
= pci_dev_read_resources
,
531 .set_resources
= pci_dev_set_resources
,
532 .enable_resources
= pci_dev_enable_resources
,
533 .init
= gma_func1_init
,
536 .ops_pci
= &gma_pci_ops
,
539 static const unsigned short pci_device_ids
[] = { 0x27a2, 0x27ae, 0 };
541 static const struct pci_driver i945_gma_func0_driver __pci_driver
= {
542 .ops
= &gma_func0_ops
,
543 .vendor
= PCI_VENDOR_ID_INTEL
,
544 .devices
= pci_device_ids
,
547 static const struct pci_driver i945_gma_func1_driver __pci_driver
= {
548 .ops
= &gma_func1_ops
,
549 .vendor
= PCI_VENDOR_ID_INTEL
,