2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
20 config NORTHBRIDGE_INTEL_I945
23 if NORTHBRIDGE_INTEL_I945
25 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
28 select MMCONF_SUPPORT_DEFAULT
29 select HAVE_DEBUG_RAM_SETUP
30 select LAPIC_MONOTONIC_TIMER
34 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
36 config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
39 config BOOTBLOCK_NORTHBRIDGE_INIT
41 default "northbridge/intel/i945/bootblock.c"
47 config CHANNEL_XOR_RANDOMIZATION
51 config OVERRIDE_CLOCK_DISABLE
55 Usually system firmware turns off system memory clock
56 signals to unused SO-DIMM slots to reduce EMI and power
58 However, some boards do not like unused clock signals to
61 config MAXIMUM_SUPPORTED_FREQUENCY
65 If non-zero, this designates the maximum DDR frequency
66 the board supports, despite what the chipset should be
69 config CHECK_SLFRCS_ON_RESUME
72 On some boards it may be neccessary to hard reset early
73 during resume from S3 if the SLFRCS register indicates that
74 a memory channel is not guaranteed to be in self-refresh.
75 On other boards the check always creates a false positive,
76 effectively making it impossible to resume.