2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
20 #include <drivers/intel/gma/i915.h>
23 * Digital Port Hotplug Enable:
24 * 0x04 = Enabled, 2ms short pulse
25 * 0x05 = Enabled, 4.5ms short pulse
26 * 0x06 = Enabled, 6ms short pulse
27 * 0x07 = Enabled, 100ms short pulse
29 struct northbridge_intel_haswell_config
{
30 u8 gpu_dp_b_hotplug
; /* Digital Port B Hotplug Config */
31 u8 gpu_dp_c_hotplug
; /* Digital Port C Hotplug Config */
32 u8 gpu_dp_d_hotplug
; /* Digital Port D Hotplug Config */
34 u8 gpu_panel_port_select
; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
35 u8 gpu_panel_power_cycle_delay
; /* T4 time sequence */
36 u16 gpu_panel_power_up_delay
; /* T1+T2 time sequence */
37 u16 gpu_panel_power_down_delay
; /* T3 time sequence */
38 u16 gpu_panel_power_backlight_on_delay
; /* T5 time sequence */
39 u16 gpu_panel_power_backlight_off_delay
; /* Tx time sequence */
41 u32 gpu_cpu_backlight
; /* CPU Backlight PWM value */
42 u32 gpu_pch_backlight
; /* PCH Backlight PWM value */
44 struct i915_gpu_controller_info gfx
;
47 extern struct chip_operations northbridge_intel_haswell_ops
;