2 ## This file is part of the coreboot project.
4 ## Copyright
(C
) 2007-2009 coresystems GmbH
6 ## This program is free software
; you can redistribute it
and/or
7 ## modify it under the terms of the GNU General Public License
as
8 ## published by the Free Software Foundation
; version
2 of
11 ## This program is distributed in the hope that it will be useful
,
12 ## but WITHOUT ANY WARRANTY
; without even the implied warranty of
13 ## MERCHANTABILITY
or FITNESS
FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License
for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program
; if not, write
to the Free Software
21 chip northbridge
/intel
/i945
23 register
"gfx.ndid" = "3"
24 register
"gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
26 device cpu_cluster
0 on
27 chip cpu
/intel
/socket_mFCPGA478
33 subsystemid
0x4352 0x6886 inherit
34 device pci
00.0 on
end # host bridge
36 #device pci
01.0 off
end # i945 PCIe root port
37 device pci
02.0 on
end # vga controller
38 device pci
02.1 on
end # display controller
40 chip southbridge
/intel
/i82801gx
41 register
"pirqa_routing" = "0x0b"
42 register
"pirqb_routing" = "0x0b"
43 register
"pirqc_routing" = "0x0b"
44 register
"pirqd_routing" = "0x0b"
45 register
"pirqe_routing" = "0x80"
46 register
"pirqf_routing" = "0x80"
47 register
"pirqg_routing" = "0x0b"
48 register
"pirqh_routing" = "0x0b"
51 #
0 No effect
(default
)
52 #
1 SMI#
(if corresponding ALT_GPI_SMI_EN bit is also
set)
53 #
2 SCI
(if corresponding GPIO_EN bit is also
set)
54 register
"gpi13_routing" = "2"
55 register
"gpi8_routing" = "1"
56 register
"gpi7_routing" = "2"
57 register
"gpe0_en" = "0x20800007"
59 register
"c3_latency" = "0x23"
60 register
"docking_supported" = "1"
61 register
"p_cnt_throttling_supported" = "1"
63 register
"ide_legacy_combined" = "0x1"
64 register
"ide_enable_primary" = "0x1"
65 register
"ide_enable_secondary" = "0x0"
66 register
"sata_ahci" = "0x0"
68 device pci
1b
.0 on
end # High Definition Audio
69 device pci
1c
.0 on
end # PCIe
70 device pci
1c
.1 on
end # PCIe
71 device pci
1c
.2 on
end # PCIe
72 #device pci
1c
.3 off
end # PCIe port
4
73 #device pci
1c
.4 off
end # PCIe port
5
74 #device pci
1c
.5 off
end # PCIe port
6
75 device pci
1d
.0 on
end # USB UHCI
76 device pci
1d
.1 on
end # USB UHCI
77 device pci
1d
.2 on
end # USB UHCI
78 device pci
1d
.3 on
end # USB UHCI
79 device pci
1d
.7 on
end # USB2 EHCI
81 chip southbridge
/ti
/pci7420
82 register
"smartcard_enabled" = "0x0"
86 device pci
3.3 off
end # smartcard
89 #device pci
1e
.2 off
end # AC
'97 Audio
90 #device pci
1e
.3 off
end # AC
'97 Modem
91 device pci
1f
.0 on # LPC bridge
92 chip superio
/smsc
/lpc47n227
93 device pnp
2e
.1 on # Parallel port
97 device pnp
2e
.2 on # COM1
101 device pnp
2e
.3 on # COM2
105 device pnp
2e
.5 off # Keyboard
+Mouse
112 chip superio
/renesas
/m3885x
113 device pnp ff
.1 on # dummy address
120 #device pci
1f
.1 off
end # IDE
121 device pci
1f
.2 on
end # SATA
122 device pci
1f
.3 on
end # SMBus
123 #device pci
1f
.4 off
end # Realtek ID Codec