src/soc/intel/cannonlake/Kconfig

   1 config SOC_INTEL_CANNONLAKE
   2         bool
   3         help
   4           Intel Cannonlake support
   5
   6 if SOC_INTEL_CANNONLAKE
   7
   8 config CPU_SPECIFIC_OPTIONS
   9         def_bool y
  10         select ARCH_BOOTBLOCK_X86_32
  11         select ARCH_RAMSTAGE_X86_32
  12         select ARCH_ROMSTAGE_X86_32
  13         select ARCH_VERSTAGE_X86_32
  14         select C_ENVIRONMENT_BOOTBLOCK
  15         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  16         select HAVE_HARD_RESET
  17         select HAVE_INTEL_FIRMWARE
  18         select HAVE_MONOTONIC_TIMER
  19         select INTEL_CAR_NEM_ENHANCED
  20         select PLATFORM_USES_FSP2_0
  21         select REG_SCRIPT
  22         select RELOCATABLE_RAMSTAGE
  23         select SOC_INTEL_COMMON
  24         select SOC_INTEL_COMMON_BLOCK
  25         select SOC_INTEL_COMMON_BLOCK_CAR
  26         select SOC_INTEL_COMMON_BLOCK_CPU
  27         select SOC_INTEL_COMMON_BLOCK_CSE
  28         select SOC_INTEL_COMMON_BLOCK_FAST_SPI
  29         select SOC_INTEL_COMMON_BLOCK_GPIO
  30         select SOC_INTEL_COMMON_BLOCK_LPSS
  31         select SOC_INTEL_COMMON_BLOCK_PCR
  32         select SOC_INTEL_COMMON_BLOCK_RTC
  33         select SOC_INTEL_COMMON_BLOCK_SA
  34         select SOC_INTEL_COMMON_BLOCK_SMBUS
  35         select SOC_INTEL_COMMON_BLOCK_TIMER
  36         select SOC_INTEL_COMMON_BLOCK_UART
  37         select SOC_INTEL_COMMON_RESET
  38         select SUPPORT_CPU_UCODE_IN_CBFS
  39         select TSC_CONSTANT_RATE
  40         select TSC_MONOTONIC_TIMER
  41         select UDELAY_TSC
  42
  43 config UART_DEBUG
  44         bool "Enable UART debug port."
  45         default y
  46         select CONSOLE_SERIAL
  47         select BOOTBLOCK_CONSOLE
  48         select DRIVERS_UART
  49         select DRIVERS_UART_8250IO
  50
  51 config DCACHE_RAM_BASE
  52         default 0xfef00000
  53
  54 config DCACHE_RAM_SIZE
  55         default 0x40000
  56         help
  57           The size of the cache-as-ram region required during bootblock
  58           and/or romstage.
  59
  60 config DCACHE_BSP_STACK_SIZE
  61         hex
  62         default 0x4000
  63         help
  64           The amount of anticipated stack usage in CAR by bootblock and
  65           other stages.
  66
  67 config PCR_BASE_ADDRESS
  68         hex
  69         default 0xfd000000
  70         help
  71           This option allows you to select MMIO Base Address of sideband bus.
  72
  73 config CPU_BCLK_MHZ
  74         int
  75         default 100
  76
  77 endif