6 static const io_register_t ich6_bios_cntl_registers
[] = {
7 { 0x0, 1, "BIOSWE - write enable" },
8 { 0x1, 1, "BLE - lock enable" },
9 { 0x2, 6, "reserved" },
12 static const io_register_t ich7_bios_cntl_registers
[] = {
13 { 0x0, 1, "BIOSWE - write enable" },
14 { 0x1, 1, "BLE - lock enable" },
15 { 0x2, 2, "SPI Read configuration" },
16 { 0x4, 1, "TopSwapStatus" },
17 { 0x5, 3, "reserved" },
20 static const io_register_t pch_bios_cntl_registers
[] = {
21 { 0x0, 1, "BIOSWE - write enable" },
22 { 0x1, 1, "BLE - lock enable" },
23 { 0x2, 2, "SPI Read configuration" },
24 { 0x4, 1, "TopSwapStatus" },
25 { 0x5, 1, "SMM Bios Write Protect Disable" },
26 { 0x6, 2, "reserved" },
29 #define ICH9_SPIBAR 0x3800
30 #define ICH78_SPIBAR 0x3020
32 static const io_register_t spi_bar_registers
[] = {
33 { 0x00, 4, "BFPR - BIOS Flash primary region" },
34 { 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
35 { 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
36 { 0x08, 4, "FADDR - Flash Address" },
37 { 0x0c, 4, "Reserved" },
38 { 0x10, 4, "FDATA0" },
39 /* 0x10 .. 0x4f are filled with data */
40 { 0x50, 4, "FRACC - Flash Region Access Permissions" },
41 { 0x54, 4, "Flash Region 0" },
42 { 0x58, 4, "Flash Region 1" },
43 { 0x5c, 4, "Flash Region 2" },
44 { 0x60, 4, "Flash Region 3" },
45 { 0x64, 4, "Flash Region 4" },
46 { 0x74, 4, "FPR0 Flash Protected Range 0" },
47 { 0x78, 4, "FPR0 Flash Protected Range 1" },
48 { 0x7c, 4, "FPR0 Flash Protected Range 2" },
49 { 0x80, 4, "FPR0 Flash Protected Range 3" },
50 { 0x84, 4, "FPR0 Flash Protected Range 4" },
51 { 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
52 { 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
53 { 0x94, 2, "PREOP - Prefix opcode Configuration" },
54 { 0x96, 2, "OPTYPE - Opcode Type Configuration" },
55 { 0x98, 8, "OPMENU - Opcode Menu Configuration" },
56 { 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
57 { 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
58 { 0xb8, 4, "Reserved" },
59 { 0xc0, 4, "AFC - Additional Flash Control" },
60 { 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
61 { 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
62 { 0xd0, 4, "FPB - Flash Partition Boundary" },
65 static const io_register_t ich7_spi_bar_registers
[] = {
66 { 0x00, 2, "SPIS - SPI Status" },
67 { 0x02, 2, "SPIC - SPI Control" },
68 { 0x04, 4, "SPIA - SPI Address" },
70 *0x08 .. 0x47 are filled with data
71 *0x48 .. 0x4f is not mentioned by datasheet
73 { 0x50, 4, "BBAR - BIOS Base Address Configuration" },
74 { 0x54, 2, "PREOP Prefix Opcode Configuration" },
75 { 0x56, 2, "OPTYPE Opcode Type Configuration" },
76 { 0x58, 8, "OPMENU Opcode Menu Configuration" },
77 { 0x60, 4, "PBR0 Protected BIOS Range 0" },
78 { 0x64, 4, "PBR1 Protected BIOS Range 1" },
79 { 0x68, 4, "PBR2 Protected BIOS Range 2" },
82 int print_bioscntl(struct pci_dev
*sb
)
85 unsigned char bios_cntl
= 0xff;
86 const io_register_t
*bios_cntl_register
= NULL
;
88 printf("\n============= SPI / BIOS CNTL =============\n\n");
90 switch (sb
->device_id
) {
91 case PCI_DEVICE_ID_INTEL_ICH6
:
92 bios_cntl
= pci_read_byte(sb
, 0xdc);
93 bios_cntl_register
= ich6_bios_cntl_registers
;
94 size
= ARRAY_SIZE(ich6_bios_cntl_registers
);
96 case PCI_DEVICE_ID_INTEL_ICH7
:
97 case PCI_DEVICE_ID_INTEL_ICH7M
:
98 case PCI_DEVICE_ID_INTEL_ICH7DH
:
99 case PCI_DEVICE_ID_INTEL_ICH7MDH
:
100 case PCI_DEVICE_ID_INTEL_ICH8
:
101 case PCI_DEVICE_ID_INTEL_ICH8M
:
102 case PCI_DEVICE_ID_INTEL_ICH8ME
:
103 case PCI_DEVICE_ID_INTEL_ICH9DH
:
104 case PCI_DEVICE_ID_INTEL_ICH9DO
:
105 case PCI_DEVICE_ID_INTEL_ICH9R
:
106 case PCI_DEVICE_ID_INTEL_ICH9
:
107 case PCI_DEVICE_ID_INTEL_ICH9M
:
108 case PCI_DEVICE_ID_INTEL_ICH9ME
:
109 case PCI_DEVICE_ID_INTEL_ICH10R
:
110 case PCI_DEVICE_ID_INTEL_NM10
:
111 bios_cntl
= pci_read_byte(sb
, 0xdc);
112 bios_cntl_register
= ich7_bios_cntl_registers
;
113 size
= ARRAY_SIZE(ich7_bios_cntl_registers
);
115 case PCI_DEVICE_ID_INTEL_3400
:
116 case PCI_DEVICE_ID_INTEL_3420
:
117 case PCI_DEVICE_ID_INTEL_3450
:
118 case PCI_DEVICE_ID_INTEL_3400_DESKTOP
:
119 case PCI_DEVICE_ID_INTEL_B55_A
:
120 case PCI_DEVICE_ID_INTEL_B55_B
:
121 case PCI_DEVICE_ID_INTEL_H55
:
122 case PCI_DEVICE_ID_INTEL_H57
:
123 case PCI_DEVICE_ID_INTEL_P55
:
124 case PCI_DEVICE_ID_INTEL_Q57
:
125 case PCI_DEVICE_ID_INTEL_3400_MOBILE
:
126 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF
:
127 case PCI_DEVICE_ID_INTEL_HM55
:
128 case PCI_DEVICE_ID_INTEL_HM57
:
129 case PCI_DEVICE_ID_INTEL_PM55
:
130 case PCI_DEVICE_ID_INTEL_QM57
:
131 case PCI_DEVICE_ID_INTEL_QS57
:
132 bios_cntl
= pci_read_byte(sb
, 0xdc);
133 bios_cntl_register
= pch_bios_cntl_registers
;
134 size
= ARRAY_SIZE(pch_bios_cntl_registers
);
137 printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
141 printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl
);
143 if (bios_cntl_register
) {
144 for (i
= 0; i
< size
; i
++) {
145 unsigned int val
= bios_cntl
>> bios_cntl_register
[i
].addr
;
146 val
&= ((1 << bios_cntl_register
[i
].size
) -1);
147 printf("0x%04x = %s\n", val
, bios_cntl_register
[i
].name
);
154 int print_spibar(struct pci_dev
*sb
) {
155 int i
, size
= 0, rcba_size
= 0x4000;
156 volatile uint8_t *rcba
;
158 const io_register_t
*spi_register
= NULL
;
159 uint32_t spibaroffset
;
161 printf("\n============= SPI Bar ==============\n\n");
163 switch (sb
->device_id
) {
164 case PCI_DEVICE_ID_INTEL_ICH6
:
165 printf("This southbridge does not have a SPI controller.\n");
167 case PCI_DEVICE_ID_INTEL_ICH7
:
168 case PCI_DEVICE_ID_INTEL_ICH7M
:
169 case PCI_DEVICE_ID_INTEL_ICH7DH
:
170 case PCI_DEVICE_ID_INTEL_ICH7MDH
:
171 spibaroffset
= ICH78_SPIBAR
;
172 rcba_phys
= pci_read_long(sb
, 0xf0) & 0xfffffffe;
173 size
= ARRAY_SIZE(ich7_spi_bar_registers
);
174 spi_register
= ich7_spi_bar_registers
;
176 case PCI_DEVICE_ID_INTEL_ICH8
:
177 spibaroffset
= ICH78_SPIBAR
;
178 rcba_phys
= pci_read_long(sb
, 0xf0) & 0xfffffffe;
179 size
= ARRAY_SIZE(spi_bar_registers
);
180 spi_register
= spi_bar_registers
;
182 case PCI_DEVICE_ID_INTEL_ICH8M
:
183 case PCI_DEVICE_ID_INTEL_ICH8ME
:
184 case PCI_DEVICE_ID_INTEL_ICH9DH
:
185 case PCI_DEVICE_ID_INTEL_ICH9DO
:
186 case PCI_DEVICE_ID_INTEL_ICH9R
:
187 case PCI_DEVICE_ID_INTEL_ICH9
:
188 case PCI_DEVICE_ID_INTEL_ICH9M
:
189 case PCI_DEVICE_ID_INTEL_ICH9ME
:
190 case PCI_DEVICE_ID_INTEL_ICH10R
:
191 case PCI_DEVICE_ID_INTEL_NM10
:
192 case PCI_DEVICE_ID_INTEL_I63XX
:
193 case PCI_DEVICE_ID_INTEL_3400
:
194 case PCI_DEVICE_ID_INTEL_3420
:
195 case PCI_DEVICE_ID_INTEL_3450
:
196 case PCI_DEVICE_ID_INTEL_3400_DESKTOP
:
197 case PCI_DEVICE_ID_INTEL_3400_MOBILE
:
198 case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF
:
199 case PCI_DEVICE_ID_INTEL_B55_A
:
200 case PCI_DEVICE_ID_INTEL_B55_B
:
201 case PCI_DEVICE_ID_INTEL_H55
:
202 case PCI_DEVICE_ID_INTEL_H57
:
203 case PCI_DEVICE_ID_INTEL_HM55
:
204 case PCI_DEVICE_ID_INTEL_HM57
:
205 case PCI_DEVICE_ID_INTEL_P55
:
206 case PCI_DEVICE_ID_INTEL_PM55
:
207 case PCI_DEVICE_ID_INTEL_Q57
:
208 case PCI_DEVICE_ID_INTEL_QM57
:
209 case PCI_DEVICE_ID_INTEL_QS57
:
210 case PCI_DEVICE_ID_INTEL_Z68
:
211 case PCI_DEVICE_ID_INTEL_P67
:
212 case PCI_DEVICE_ID_INTEL_UM67
:
213 case PCI_DEVICE_ID_INTEL_HM65
:
214 case PCI_DEVICE_ID_INTEL_H67
:
215 case PCI_DEVICE_ID_INTEL_HM67
:
216 case PCI_DEVICE_ID_INTEL_Q65
:
217 case PCI_DEVICE_ID_INTEL_QS67
:
218 case PCI_DEVICE_ID_INTEL_Q67
:
219 case PCI_DEVICE_ID_INTEL_QM67
:
220 case PCI_DEVICE_ID_INTEL_B65
:
221 case PCI_DEVICE_ID_INTEL_C202
:
222 case PCI_DEVICE_ID_INTEL_C204
:
223 case PCI_DEVICE_ID_INTEL_C206
:
224 case PCI_DEVICE_ID_INTEL_H61
:
225 case PCI_DEVICE_ID_INTEL_Z77
:
226 case PCI_DEVICE_ID_INTEL_Z75
:
227 case PCI_DEVICE_ID_INTEL_Q77
:
228 case PCI_DEVICE_ID_INTEL_Q75
:
229 case PCI_DEVICE_ID_INTEL_B75
:
230 case PCI_DEVICE_ID_INTEL_H77
:
231 case PCI_DEVICE_ID_INTEL_C216
:
232 case PCI_DEVICE_ID_INTEL_QM77
:
233 case PCI_DEVICE_ID_INTEL_QS77
:
234 case PCI_DEVICE_ID_INTEL_HM77
:
235 case PCI_DEVICE_ID_INTEL_UM77
:
236 case PCI_DEVICE_ID_INTEL_HM76
:
237 case PCI_DEVICE_ID_INTEL_HM75
:
238 case PCI_DEVICE_ID_INTEL_HM70
:
239 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL
:
240 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM
:
241 case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE
:
242 case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP
:
243 spibaroffset
= ICH9_SPIBAR
;
244 rcba_phys
= pci_read_long(sb
, 0xf0) & 0xfffffffe;
245 size
= ARRAY_SIZE(spi_bar_registers
);
246 spi_register
= spi_bar_registers
;
248 case PCI_DEVICE_ID_INTEL_ICH
:
249 case PCI_DEVICE_ID_INTEL_ICH0
:
250 case PCI_DEVICE_ID_INTEL_ICH2
:
251 case PCI_DEVICE_ID_INTEL_ICH4
:
252 case PCI_DEVICE_ID_INTEL_ICH4M
:
253 case PCI_DEVICE_ID_INTEL_ICH5
:
254 printf("This southbridge does not have RCBA.\n");
257 printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
261 rcba
= map_physical(rcba_phys
, rcba_size
);
263 perror("Error mapping RCBA");
267 for (i
= 0; i
< size
; i
++) {
268 switch(spi_register
[i
].size
) {
270 printf("0x%08x = %s\n", *(uint8_t *)(rcba
+ spibaroffset
+ spi_register
[i
].addr
), spi_register
[i
].name
);
273 printf("0x%08x = %s\n", *(uint16_t *)(rcba
+ spibaroffset
+ spi_register
[i
].addr
), spi_register
[i
].name
);
276 printf("0x%08x = %s\n", *(uint32_t *)(rcba
+ spibaroffset
+ spi_register
[i
].addr
), spi_register
[i
].name
);
279 printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba
+ spi_register
[i
].addr
), *(uint32_t *)(rcba
+ spi_register
[i
].addr
+ 4), spi_register
[i
].name
);
284 unmap_physical((void *)rcba
, rcba_size
);
288 int print_spi(struct pci_dev
*sb
) {
289 return (print_bioscntl(sb
) || print_spibar(sb
));