src/southbridge/intel/bd82x6x/pch.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <console/console.h>
  19 #include <delay.h>
  20 #ifdef __SMM__
  21 #include <arch/io.h>
  22 #include <device/pci_def.h>
  23 #else /* !__SMM__ */
  24 #include <device/device.h>
  25 #include <device/pci.h>
  26 #endif
  27 #include "pch.h"
  28 #include <string.h>
  29
  30 int pch_silicon_revision(void)
  31 {
  32         static int pch_revision_id = -1;
  33
  34 #ifdef __SIMPLE_DEVICE__
  35         pci_devfn_t dev;
  36         dev = PCI_DEV(0, 0x1f, 0);
  37 #else
  38         struct device *dev;
  39         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
  40 #endif
  41
  42         if (pch_revision_id < 0)
  43                 pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
  44         return pch_revision_id;
  45 }
  46
  47 int pch_silicon_type(void)
  48 {
  49         static int pch_type = -1;
  50
  51 #ifdef __SIMPLE_DEVICE__
  52         pci_devfn_t dev;
  53         dev = PCI_DEV(0, 0x1f, 0);
  54 #else
  55         struct device *dev;
  56         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
  57 #endif
  58
  59         if (pch_type < 0)
  60                 pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
  61         return pch_type;
  62 }
  63
  64 int pch_silicon_supported(int type, int rev)
  65 {
  66         int cur_type = pch_silicon_type();
  67         int cur_rev = pch_silicon_revision();
  68
  69         switch (type) {
  70         case PCH_TYPE_CPT:
  71                 /* CougarPoint minimum revision */
  72                 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
  73                         return 1;
  74                 /* PantherPoint any revision */
  75                 if (cur_type == PCH_TYPE_PPT)
  76                         return 1;
  77                 break;
  78
  79         case PCH_TYPE_PPT:
  80                 /* PantherPoint minimum revision */
  81                 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
  82                         return 1;
  83                 break;
  84         }
  85
  86         return 0;
  87 }
  88
  89 #define IOBP_RETRY 1000
  90 static inline int iobp_poll(void)
  91 {
  92         unsigned try = IOBP_RETRY;
  93         u32 data;
  94
  95         while (try--) {
  96                 data = RCBA32(IOBPS);
  97                 if ((data & 1) == 0)
  98                         return 1;
  99                 udelay(10);
 100         }
 101
 102         printk(BIOS_ERR, "IOBP timeout\n");
 103         return 0;
 104 }
 105
 106 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 107 {
 108         u32 data;
 109
 110         /* Set the address */
 111         RCBA32(IOBPIRI) = address;
 112
 113         /* READ OPCODE */
 114         if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
 115                 RCBA32(IOBPS) = IOBPS_RW_BX;
 116         else
 117                 RCBA32(IOBPS) = IOBPS_READ_AX;
 118         if (!iobp_poll())
 119                 return;
 120
 121         /* Read IOBP data */
 122         data = RCBA32(IOBPD);
 123         if (!iobp_poll())
 124                 return;
 125
 126         /* Check for successful transaction */
 127         if ((RCBA32(IOBPS) & 0x6) != 0) {
 128                 printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
 129                 return;
 130         }
 131
 132         /* Update the data */
 133         data &= andvalue;
 134         data |= orvalue;
 135
 136         /* WRITE OPCODE */
 137         if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
 138                 RCBA32(IOBPS) = IOBPS_RW_BX;
 139         else
 140                 RCBA32(IOBPS) = IOBPS_WRITE_AX;
 141         if (!iobp_poll())
 142                 return;
 143
 144         /* Write IOBP data */
 145         RCBA32(IOBPD) = data;
 146         if (!iobp_poll())
 147                 return;
 148 }
 149
 150 #ifndef __SMM__
 151 /* Set bit in Function Disble register to hide this device */
 152 static void pch_hide_devfn(unsigned devfn)
 153 {
 154         switch (devfn) {
 155         case PCI_DEVFN(22, 0): /* MEI #1 */
 156                 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 157                 break;
 158         case PCI_DEVFN(22, 1): /* MEI #2 */
 159                 RCBA32_OR(FD2, PCH_DISABLE_MEI2);
 160                 break;
 161         case PCI_DEVFN(22, 2): /* IDE-R */
 162                 RCBA32_OR(FD2, PCH_DISABLE_IDER);
 163                 break;
 164         case PCI_DEVFN(22, 3): /* KT */
 165                 RCBA32_OR(FD2, PCH_DISABLE_KT);
 166                 break;
 167         case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
 168                 RCBA32_OR(BUC, PCH_DISABLE_GBE);
 169                 break;
 170         case PCI_DEVFN(26, 0): /* EHCI #2 */
 171                 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
 172                 break;
 173         case PCI_DEVFN(27, 0): /* HD Audio Controller */
 174                 RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
 175                 break;
 176         case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
 177         case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
 178         case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
 179         case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
 180         case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
 181         case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
 182         case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
 183         case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
 184                 RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
 185                 break;
 186         case PCI_DEVFN(29, 0): /* EHCI #1 */
 187                 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
 188                 break;
 189         case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
 190                 RCBA32_OR(FD, PCH_DISABLE_P2P);
 191                 break;
 192         case PCI_DEVFN(31, 0): /* LPC */
 193                 RCBA32_OR(FD, PCH_DISABLE_LPC);
 194                 break;
 195         case PCI_DEVFN(31, 2): /* SATA #1 */
 196                 RCBA32_OR(FD, PCH_DISABLE_SATA1);
 197                 break;
 198         case PCI_DEVFN(31, 3): /* SMBUS */
 199                 RCBA32_OR(FD, PCH_DISABLE_SMBUS);
 200                 break;
 201         case PCI_DEVFN(31, 5): /* SATA #22 */
 202                 RCBA32_OR(FD, PCH_DISABLE_SATA2);
 203                 break;
 204         case PCI_DEVFN(31, 6): /* Thermal Subsystem */
 205                 RCBA32_OR(FD, PCH_DISABLE_THERMAL);
 206                 break;
 207         }
 208 }
 209
 210 /* Check if any port in set X to X+3 is enabled */
 211 static int pch_pcie_check_set_enabled(struct device *dev)
 212 {
 213         struct device *port;
 214         int port_func;
 215         int dev_func = PCI_FUNC(dev->path.pci.devfn);
 216
 217         printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev));
 218
 219         /* Go through static device tree list of devices
 220          * because enumeration is still in progress */
 221         for (port = all_devices; port; port = port->next) {
 222                 /* Only care about PCIe root ports */
 223                 if (PCI_SLOT(port->path.pci.devfn) !=
 224                     PCI_SLOT(dev->path.pci.devfn))
 225                         continue;
 226
 227                 /* Check if port is in range and enabled */
 228                 port_func = PCI_FUNC(port->path.pci.devfn);
 229                 if (port_func >= dev_func &&
 230                     port_func < (dev_func + 4) &&
 231                     port->enabled)
 232                         return 1;
 233         }
 234
 235         /* None of the ports in this set are enabled */
 236         return 0;
 237 }
 238
 239 /* RPFN is a write-once register so keep a copy until it is written */
 240 static u32 new_rpfn;
 241
 242 /* Swap function numbers assigned to two PCIe Root Ports */
 243 static void pch_pcie_function_swap(u8 old_fn, u8 new_fn)
 244 {
 245         u32 old_rpfn = new_rpfn;
 246
 247         printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n",
 248                old_fn, new_fn);
 249
 250         new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));
 251
 252         /* Old function set to new function and disabled */
 253         new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn));
 254         new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn));
 255 }
 256
 257 /* Update devicetree with new Root Port function number assignment */
 258 static void pch_pcie_devicetree_update(
 259                 struct southbridge_intel_bd82x6x_config *config)
 260 {
 261         struct device *dev;
 262
 263         /*
 264          * hotplug map should also be updated along with their
 265          * corresponding port
 266          */
 267         u8 new_hotplug_map[sizeof(config->pcie_hotplug_map)];
 268
 269         /*
 270          * Slots that didn't move need the hotplug setting copied too,
 271          * so "new_hotplug_map" is initialized with the values of the old map.
 272          */
 273         memcpy(new_hotplug_map, config->pcie_hotplug_map,
 274                sizeof(new_hotplug_map));
 275
 276         /* Update the function numbers in the static devicetree */
 277         for (dev = all_devices; dev; dev = dev->next) {
 278                 u8 new_devfn;
 279
 280                 /* Only care about PCH PCIe root ports */
 281                 if (PCI_SLOT(dev->path.pci.devfn) !=
 282                     PCH_PCIE_DEV_SLOT)
 283                         continue;
 284
 285                 /* Determine the new devfn for this port */
 286                 new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT,
 287                               RPFN_FNGET(new_rpfn,
 288                                  PCI_FUNC(dev->path.pci.devfn)));
 289
 290                 if (dev->path.pci.devfn != new_devfn) {
 291                         printk(BIOS_DEBUG,
 292                                "PCH: PCIe map %02x.%1x -> %02x.%1x\n",
 293                                PCI_SLOT(dev->path.pci.devfn),
 294                                PCI_FUNC(dev->path.pci.devfn),
 295                                PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
 296
 297                         /*
 298                          * Copy the flag to its new position along with
 299                          * the corresponding port
 300                          */
 301                         new_hotplug_map[PCI_FUNC(new_devfn)] =
 302                                 config->pcie_hotplug_map
 303                                 [PCI_FUNC(dev->path.pci.devfn)];
 304
 305                         dev->path.pci.devfn = new_devfn;
 306                 }
 307         }
 308
 309         /* Copy the updated map back to its place */
 310         memcpy(config->pcie_hotplug_map, new_hotplug_map,
 311                sizeof(new_hotplug_map));
 312 }
 313
 314 /* Special handling for PCIe Root Port devices */
 315 static void pch_pcie_enable(struct device *dev)
 316 {
 317         struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 318         u32 reg32;
 319
 320         if (!config)
 321                 return;
 322
 323         /*
 324          * Save a copy of the Root Port Function Number map when
 325          * starting to walk the list of PCIe Root Ports so it can
 326          * be updated locally and written out when the last port
 327          * has been processed.
 328          */
 329         if (PCI_FUNC(dev->path.pci.devfn) == 0) {
 330                 new_rpfn = RCBA32(RPFN);
 331
 332                 /*
 333                  * Enable Root Port coalescing if the first port is disabled
 334                  * or the other devices will not be enumerated by the OS.
 335                  */
 336                 if (!dev->enabled)
 337                         config->pcie_port_coalesce = 1;
 338
 339                 if (config->pcie_port_coalesce)
 340                         printk(BIOS_INFO,
 341                                "PCH: PCIe Root Port coalescing is enabled\n");
 342         }
 343
 344         if (!dev->enabled) {
 345                 printk(BIOS_DEBUG, "%s: Disabling device\n",  dev_path(dev));
 346
 347                 /*
 348                  * PCIE Power Savings for PantherPoint and CougarPoint/B1+
 349                  *
 350                  * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
 351                  * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
 352                  *
 353                  * This check is done here instead of pcie driver
 354                  * because the pcie driver enable() handler is not
 355                  * called unless the device is enabled.
 356                  */
 357                 if ((PCI_FUNC(dev->path.pci.devfn) == 0 ||
 358                      PCI_FUNC(dev->path.pci.devfn) == 4)) {
 359                         /* Handle workaround for PPT and CPT/B1+ */
 360                         if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) &&
 361                             !pch_pcie_check_set_enabled(dev)) {
 362                                 u8 reg8 = pci_read_config8(dev, 0xe2);
 363                                 reg8 |= 1;
 364                                 pci_write_config8(dev, 0xe2, reg8);
 365                         }
 366
 367                         /*
 368                          * Enable Clock Gating for shared PCIe resources
 369                          * before disabling this particular port.
 370                          */
 371                         pci_write_config8(dev, 0xe1, 0x3c);
 372                 }
 373
 374                 /* Ensure memory, io, and bus master are all disabled */
 375                 reg32 = pci_read_config32(dev, PCI_COMMAND);
 376                 reg32 &= ~(PCI_COMMAND_MASTER |
 377                            PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 378                 pci_write_config32(dev, PCI_COMMAND, reg32);
 379
 380                 /* Do not claim downstream transactions for PCIe ports */
 381                 new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
 382
 383                 /* Hide this device if possible */
 384                 pch_hide_devfn(dev->path.pci.devfn);
 385         } else {
 386                 int fn;
 387
 388                 /*
 389                  * Check if there is a lower disabled port to swap with this
 390                  * port in order to maintain linear order starting at zero.
 391                  */
 392                 if (config->pcie_port_coalesce) {
 393                         for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) {
 394                                 if (!(new_rpfn & RPFN_HIDE(fn)))
 395                                         continue;
 396
 397                                 /* Swap places with this function */
 398                                 pch_pcie_function_swap(
 399                                         PCI_FUNC(dev->path.pci.devfn), fn);
 400                                 break;
 401                         }
 402                 }
 403
 404                 /* Enable SERR */
 405                 reg32 = pci_read_config32(dev, PCI_COMMAND);
 406                 reg32 |= PCI_COMMAND_SERR;
 407                 pci_write_config32(dev, PCI_COMMAND, reg32);
 408         }
 409
 410         /*
 411          * When processing the last PCIe root port we can now
 412          * update the Root Port Function Number and Hide register.
 413          */
 414         if (PCI_FUNC(dev->path.pci.devfn) == 7) {
 415                 printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
 416                        RCBA32(RPFN), new_rpfn);
 417                 RCBA32(RPFN) = new_rpfn;
 418
 419                 /* Update static devictree with new function numbers */
 420                 if (config->pcie_port_coalesce)
 421                         pch_pcie_devicetree_update(config);
 422         }
 423 }
 424
 425 void pch_enable(struct device *dev)
 426 {
 427         u32 reg32;
 428
 429         /* PCH PCIe Root Ports get special handling */
 430         if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT)
 431                 return pch_pcie_enable(dev);
 432
 433         if (!dev->enabled) {
 434                 printk(BIOS_DEBUG, "%s: Disabling device\n",  dev_path(dev));
 435
 436                 /* Ensure memory, io, and bus master are all disabled */
 437                 reg32 = pci_read_config32(dev, PCI_COMMAND);
 438                 reg32 &= ~(PCI_COMMAND_MASTER |
 439                            PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
 440                 pci_write_config32(dev, PCI_COMMAND, reg32);
 441
 442                 /* Hide this device if possible */
 443                 pch_hide_devfn(dev->path.pci.devfn);
 444         } else {
 445                 /* Enable SERR */
 446                 reg32 = pci_read_config32(dev, PCI_COMMAND);
 447                 reg32 |= PCI_COMMAND_SERR;
 448                 pci_write_config32(dev, PCI_COMMAND, reg32);
 449         }
 450 }
 451
 452 struct chip_operations southbridge_intel_bd82x6x_ops = {
 453         CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
 454         .enable_dev = pch_enable,
 455 };
 456 #endif