2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 mainmenu "coreboot configuration"
28 This allows you to select certain advanced configuration options.
30 Warning: Only enable this option if you really know what you are
31 doing! You have been warned!
34 string "Local version string"
36 Append an extra string to the end of the coreboot version.
38 This can be useful if, for instance, you want to append the
39 respective board's hostname or some other identifying string to
40 the coreboot version number, so that you can easily distinguish
41 boot logs of different boards from each other.
44 string "CBFS prefix to use"
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
50 config COMMON_CBFS_SPI_WRAPPER
56 Use common wrapper to interface CBFS to SPI bootrom.
58 config MULTIPLE_CBFS_INSTANCES
59 bool "Multiple CBFS instances in the bootrom"
63 Account for the firmware image containing more than one CBFS
64 instance. Locations of instances are known at build time and are
65 communicated between coreboot stages to make sure the next stage is
66 loaded from the appropriate instance.
69 prompt "Compiler to use"
72 This option allows you to select the compiler used for building
78 Use the GNU Compiler Collection (GCC) to build coreboot.
80 For details see http://gcc.gnu.org.
82 config COMPILER_LLVM_CLANG
85 Use LLVM/clang to build coreboot.
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
111 config SCONFIG_GENPARSER
112 bool "Generate SCONFIG parser using flex and bison"
116 Enable this option if you are working on the sconfig device tree
117 parser and made changes to sconfig.l and sconfig.y.
121 config USE_OPTION_TABLE
122 bool "Use CMOS for configuration values"
124 depends on HAVE_OPTION_TABLE
126 Enable this option if coreboot shall read options from the "CMOS"
127 NVRAM instead of using hard-coded values.
129 config STATIC_OPTION_TABLE
130 bool "Load default configuration values into CMOS on each boot"
132 depends on USE_OPTION_TABLE
134 Enable this option to reset "CMOS" NVRAM values to default on
135 every boot. Use this if you want the NVRAM configuration to
136 never be modified from its default values.
138 config UNCOMPRESSED_RAMSTAGE
142 config COMPRESS_RAMSTAGE
143 bool "Compress ramstage with LZMA"
144 default y if !UNCOMPRESSED_RAMSTAGE
147 Compress ramstage to save memory in the flash image. Note
148 that decompression might slow down booting if the boot flash
149 is connected through a slow link (i.e. SPI).
151 config INCLUDE_CONFIG_FILE
152 bool "Include the coreboot .config file into the ROM image"
155 Include the .config file that was used to compile coreboot
156 in the (CBFS) ROM image. This is useful if you want to know which
157 options were used to build a specific coreboot.rom image.
159 Saying Y here will increase the image size by 2-3KB.
161 You can use the following command to easily list the options:
163 grep -a CONFIG_ coreboot.rom
165 Alternatively, you can also use cbfstool to print the image
166 contents (including the raw 'config' item we're looking for).
170 $ cbfstool coreboot.rom print
171 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
175 Name Offset Type Size
176 cmos_layout.bin 0x0 cmos layout 1159
177 fallback/romstage 0x4c0 stage 339756
178 fallback/ramstage 0x53440 stage 186664
179 fallback/payload 0x80dc0 payload 51526
180 config 0x8d740 raw 3324
181 (empty) 0x8e480 null 3610440
183 config EARLY_CBMEM_INIT
184 def_bool !LATE_CBMEM_INIT
186 config COLLECT_TIMESTAMPS
187 bool "Create a table of timestamps collected during boot"
190 Make coreboot create a table of timer-ID/timer-value pairs to
191 allow measuring time spent at different phases of the boot process.
194 bool "Allow use of binary-only repository"
197 This draws in the blobs repository, which contains binary files that
198 might be required for some chipsets or boards.
199 This flag ensures that a "Free" option remains available for users.
202 bool "Code coverage support"
203 depends on COMPILER_GCC
206 Add code coverage support for coreboot. This will store code
207 coverage information in CBMEM for extraction from user space.
210 config RELOCATABLE_MODULES
211 bool "Relocatable Modules"
214 If RELOCATABLE_MODULES is selected then support is enabled for
215 building relocatable modules in the RAM stage. Those modules can be
216 loaded anywhere and all the relocations are handled automatically.
218 config RELOCATABLE_RAMSTAGE
219 depends on (RELOCATABLE_MODULES && EARLY_CBMEM_INIT)
220 bool "Build the ramstage to be relocatable in 32-bit address space."
223 The reloctable ramstage support allows for the ramstage to be built
224 as a relocatable module. The stage loader can identify a place
225 out of the OS way so that copying memory is unnecessary during an S3
226 wake. When selecting this option the romstage is responsible for
227 determing a stack location to use for loading the ramstage.
229 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
230 depends on RELOCATABLE_RAMSTAGE
231 bool "Cache the relocated ramstage outside of cbmem."
234 The relocated ramstage is saved in an area specified by the
235 by the board and/or chipset.
238 prompt "Bootblock behaviour"
239 default BOOTBLOCK_SIMPLE
241 config BOOTBLOCK_SIMPLE
242 bool "Always load fallback"
244 config BOOTBLOCK_NORMAL
245 bool "Switch to normal if CMOS says so"
249 config BOOTBLOCK_SOURCE
251 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
252 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
254 config SKIP_MAX_REBOOT_CNT_CLEAR
255 bool "Do not clear reboot count after successful boot"
259 Do not clear the reboot count immediately after successful boot.
260 Set to allow the payload to control normal/fallback image recovery.
263 bool "Update existing coreboot.rom image"
266 If this option is enabled, no new coreboot.rom file
267 is created. Instead it is expected that there already
268 is a suitable file for further processing.
269 The bootblock will not be modified.
271 config RAM_CODE_SUPPORT
272 bool "Discover RAM configuration code and store it in coreboot table"
275 If enabled, coreboot discovers RAM configuration (value obtained by
276 reading board straps) and stores it in coreboot table.
280 source "src/mainboard/Kconfig"
282 source "src/arch/*/Kconfig"
284 source "src/vendorcode/*/Kconfig"
286 config SYSTEM_TYPE_LAPTOP
293 source "src/cpu/Kconfig"
294 comment "Northbridge"
295 source "src/northbridge/*/*/Kconfig"
296 comment "Southbridge"
297 source "src/southbridge/*/*/Kconfig"
299 source "src/superio/*/Kconfig"
300 comment "Embedded Controllers"
301 source "src/ec/acpi/Kconfig"
302 source "src/ec/*/*/Kconfig"
304 source "src/soc/*/*/Kconfig"
305 source "src/drivers/intel/fsp/Kconfig"
309 source "src/device/Kconfig"
311 menu "Generic Drivers"
312 source "src/drivers/*/Kconfig"
318 select LPC_TPM if ARCH_X86
319 select I2C_TPM if ARCH_ARM
320 select I2C_TPM if ARCH_ARM64
322 Enable this option to enable TPM support in coreboot.
337 default 0x0 if (ARCH_RAMSTAGE_ARM || ARCH_RAMSTAGE_MIPS)
344 config MMCONF_SUPPORT_DEFAULT
348 config MMCONF_SUPPORT
352 config BOOTMODE_STRAPS
356 source "src/console/Kconfig"
358 config HAVE_ACPI_RESUME
362 config HAVE_ACPI_SLIC
366 config HAVE_HARD_RESET
370 This variable specifies whether a given board has a hard_reset
371 function, no matter if it's provided by board code or chipset code.
373 config HAVE_MONOTONIC_TIMER
376 The board/chipset provides a monotonic timer.
378 config GENERIC_UDELAY
380 depends on HAVE_MONOTONIC_TIMER
382 The board/chipset uses a generic udelay function utilizing the
387 depends on HAVE_MONOTONIC_TIMER
389 Provide a timer queue for performing time-based callbacks.
391 config COOP_MULTITASKING
393 depends on TIMER_QUEUE && ARCH_X86
395 Cooperative multitasking allows callbacks to be multiplexed on the
396 main thread of ramstage. With this enabled it allows for multiple
397 execution paths to take place when they have udelay() calls within
403 depends on COOP_MULTITASKING
405 How many execution threads to cooperatively multitask with.
407 config HAVE_OPTION_TABLE
411 This variable specifies whether a given board has a cmos.layout
412 file containing NVRAM/CMOS bit definitions.
413 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
419 config HAVE_SMI_HANDLER
423 config PCI_IO_CFG_EXT
432 hex "Size of CBFS filesystem in ROM"
435 This is the part of the ROM actually managed by CBFS, located at the
436 end of the ROM (passed through cbfstool -o) on x86 and at at the start
437 of the ROM (passed through cbfstool -s) everywhere else. Defaults to
438 span the whole ROM but can be overwritten to make coreboot live
439 alongside other components (like ChromeOS's vboot/FMAP).
441 config CACHE_ROM_SIZE_OVERRIDE
445 # TODO: Can probably be removed once all chipsets have kconfig options for it.
450 config USE_WATCHDOG_ON_BOOT
458 Build board-specific VGA code.
464 Enable Unified Memory Architecture for graphics.
466 config HAVE_ACPI_TABLES
469 This variable specifies whether a given board has ACPI table support.
470 It is usually set in mainboard/*/Kconfig.
475 This variable specifies whether a given board has MP table support.
476 It is usually set in mainboard/*/Kconfig.
477 Whether or not the MP table is actually generated by coreboot
478 is configurable by the user via GENERATE_MP_TABLE.
480 config HAVE_PIRQ_TABLE
483 This variable specifies whether a given board has PIRQ table support.
484 It is usually set in mainboard/*/Kconfig.
485 Whether or not the PIRQ table is actually generated by coreboot
486 is configurable by the user via GENERATE_PIRQ_TABLE.
488 config MAX_PIRQ_LINKS
492 This variable specifies the number of PIRQ interrupt links which are
493 routable. On most chipsets, this is 4, INTA through INTD. Some
494 chipsets offer more than four links, commonly up to INTH. They may
495 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
496 table specifies links greater than 4, pirq_route_irqs will not
497 function properly, unless this variable is correctly set.
499 config PER_DEVICE_ACPI_TABLES
507 #These Options are here to avoid "undefined" warnings.
508 #The actual selection and help texts are in the following menu.
512 config GENERATE_MP_TABLE
513 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
515 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
517 Generate an MP table (conforming to the Intel MultiProcessor
518 specification 1.4) for this board.
522 config GENERATE_PIRQ_TABLE
523 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
525 default HAVE_PIRQ_TABLE
527 Generate a PIRQ table for this board.
531 config GENERATE_SMBIOS_TABLES
533 bool "Generate SMBIOS tables"
536 Generate SMBIOS tables for this board.
540 config MAINBOARD_SERIAL_NUMBER
541 string "SMBIOS Serial Number"
542 depends on GENERATE_SMBIOS_TABLES
545 The Serial Number to store in SMBIOS structures.
547 config MAINBOARD_VERSION
548 string "SMBIOS Version Number"
549 depends on GENERATE_SMBIOS_TABLES
552 The Version Number to store in SMBIOS structures.
554 config MAINBOARD_SMBIOS_MANUFACTURER
555 string "SMBIOS Manufacturer"
556 depends on GENERATE_SMBIOS_TABLES
557 default MAINBOARD_VENDOR
559 Override the default Manufacturer stored in SMBIOS structures.
561 config MAINBOARD_SMBIOS_PRODUCT_NAME
562 string "SMBIOS Product name"
563 depends on GENERATE_SMBIOS_TABLES
564 default MAINBOARD_PART_NUMBER
566 Override the default Product name stored in SMBIOS structures.
573 prompt "Add a payload"
574 default PAYLOAD_NONE if !ARCH_X86
575 default PAYLOAD_SEABIOS if ARCH_X86
580 Select this option if you want to create an "empty" coreboot
581 ROM image for a certain mainboard, i.e. a coreboot ROM image
582 which does not yet contain a payload.
584 For such an image to be useful, you have to use 'cbfstool'
585 to add a payload to the ROM image later.
588 bool "An ELF executable payload"
590 Select this option if you have a payload image (an ELF file)
591 which coreboot should run as soon as the basic hardware
592 initialization is completed.
594 You will be able to specify the location and file name of the
598 bool "A Linux payload"
600 Select this option if you have a Linux bzImage which coreboot
601 should run as soon as the basic hardware initialization
604 You will be able to specify the location and file name of the
607 config PAYLOAD_SEABIOS
611 Select this option if you want to build a coreboot image
612 with a SeaBIOS payload. If you don't know what this is
613 about, just leave it enabled.
615 See http://coreboot.org/Payloads for more information.
620 Select this option if you want to build a coreboot image
621 with a FILO payload. If you don't know what this is
622 about, just leave it enabled.
624 See http://coreboot.org/Payloads for more information.
629 Select this option if you want to build a coreboot image
630 with a GRUB2 payload. If you don't know what this is
631 about, just leave it enabled.
633 See http://coreboot.org/Payloads for more information.
635 config PAYLOAD_TIANOCORE
638 Select this option if you want to build a coreboot image
639 with a Tiano Core payload. If you don't know what this is
640 about, just leave it enabled.
642 See http://coreboot.org/Payloads for more information.
647 prompt "SeaBIOS version"
648 default SEABIOS_STABLE
649 depends on PAYLOAD_SEABIOS
651 config SEABIOS_STABLE
654 Stable SeaBIOS version
655 config SEABIOS_MASTER
658 Newest SeaBIOS version
662 config SEABIOS_PS2_TIMEOUT
663 prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS
668 Some PS/2 keyboard controllers don't respond to commands immediately
669 after powering on. This specifies how long SeaBIOS will wait for the
670 keyboard controller to become ready before giving up.
672 config SEABIOS_THREAD_OPTIONROMS
673 prompt "Hardware init during option ROM execution" if PAYLOAD_SEABIOS
677 Allow hardware init to run in parallel with optionrom execution.
679 This can reduce boot time, but can cause some timing
680 variations during option ROM code execution. It is not
681 known if all option ROMs will behave properly with this option.
683 config SEABIOS_MALLOC_UPPERMEMORY
686 depends on PAYLOAD_SEABIOS
688 Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
689 "low memory" allocations. If this is not selected, the memory is
690 instead allocated from the "9-segment" (0x90000-0xa0000).
691 This is not typically needed, but may be required on some platforms
692 to allow USB and SATA buffers to be written correctly by the
693 hardware. In general, if this is desired, the option will be
694 set to 'N' by the chipset Kconfig.
696 config SEABIOS_VGA_COREBOOT
697 prompt "Include generated option rom that implements legacy VGA BIOS compatibility" if PAYLOAD_SEABIOS
699 depends on !VGA_BIOS && (MAINBOARD_DO_NATIVE_VGA_INIT || MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG)
702 Coreboot can initialize the GPU of some mainboards.
704 After initializing the GPU, the information about it can be passed to the payload.
705 Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
708 prompt "GRUB2 version"
710 depends on PAYLOAD_GRUB2
720 prompt "FILO version"
722 depends on PAYLOAD_FILO
737 string "Payload path and filename"
738 depends on PAYLOAD_ELF
739 default "payload.elf"
741 The path and filename of the ELF executable file to use as payload.
744 string "Linux path and filename"
745 depends on PAYLOAD_LINUX
748 The path and filename of the bzImage kernel to use as payload.
751 depends on PAYLOAD_SEABIOS
752 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
754 config PAYLOAD_VGABIOS_FILE
756 depends on PAYLOAD_SEABIOS && SEABIOS_VGA_COREBOOT
757 default "payloads/external/SeaBIOS/seabios/out/vgabios.bin"
760 depends on PAYLOAD_FILO
761 default "payloads/external/FILO/filo/build/filo.elf"
764 depends on PAYLOAD_GRUB2
765 default "payloads/external/GRUB2/grub2/build/default_payload.elf"
768 string "Tianocore firmware volume"
769 depends on PAYLOAD_TIANOCORE
770 default "COREBOOT.fd"
772 The result of a corebootPkg build
774 # TODO: Defined if no payload? Breaks build?
775 config COMPRESSED_PAYLOAD_LZMA
776 bool "Use LZMA compression for payloads"
778 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2
780 In order to reduce the size payloads take up in the ROM chip
781 coreboot can compress them using the LZMA algorithm.
783 config LINUX_COMMAND_LINE
784 string "Linux command line"
785 depends on PAYLOAD_LINUX
788 A command line to add to the Linux kernel.
791 string "Linux initrd"
792 depends on PAYLOAD_LINUX
795 An initrd image to add to the Linux kernel.
801 # TODO: Better help text and detailed instructions.
803 bool "GDB debugging support"
806 If enabled, you will be able to set breakpoints for gdb debugging.
807 See src/arch/x86/lib/c_start.S for details.
810 bool "Wait for a GDB connection"
814 If enabled, coreboot will wait for a GDB connection.
817 bool "Halt when hitting a BUG() or assertion error"
820 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
823 bool "Output verbose CBFS debug messages"
826 This option enables additional CBFS related debug messages.
828 config HAVE_DEBUG_RAM_SETUP
831 config DEBUG_RAM_SETUP
832 bool "Output verbose RAM init debug messages"
834 depends on HAVE_DEBUG_RAM_SETUP
836 This option enables additional RAM init related debug messages.
837 It is recommended to enable this when debugging issues on your
838 board which might be RAM init related.
840 Note: This option will increase the size of the coreboot image.
844 config HAVE_DEBUG_CAR
849 depends on HAVE_DEBUG_CAR
851 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
852 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
853 # printk(BIOS_DEBUG, ...) calls.
855 bool "Output verbose Cache-as-RAM debug messages"
857 depends on HAVE_DEBUG_CAR
859 This option enables additional CAR related debug messages.
863 bool "Check PIRQ table consistency"
865 depends on GENERATE_PIRQ_TABLE
869 config HAVE_DEBUG_SMBUS
873 bool "Output verbose SMBus debug messages"
875 depends on HAVE_DEBUG_SMBUS
877 This option enables additional SMBus (and SPD) debug messages.
879 Note: This option will increase the size of the coreboot image.
884 bool "Output verbose SMI debug messages"
886 depends on HAVE_SMI_HANDLER
888 This option enables additional SMI related debug messages.
890 Note: This option will increase the size of the coreboot image.
894 config DEBUG_SMM_RELOCATION
895 bool "Debug SMM relocation code"
897 depends on HAVE_SMI_HANDLER
899 This option enables additional SMM handler relocation related
902 Note: This option will increase the size of the coreboot image.
906 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
907 # printk(BIOS_DEBUG, ...) calls.
909 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
913 This option enables additional malloc related debug messages.
915 Note: This option will increase the size of the coreboot image.
919 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
920 # printk(BIOS_DEBUG, ...) calls.
922 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
926 This option enables additional ACPI related debug messages.
928 Note: This option will slightly increase the size of the coreboot image.
932 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
933 # printk(BIOS_DEBUG, ...) calls.
934 config REALMODE_DEBUG
935 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
938 depends on PCI_OPTION_ROM_RUN_REALMODE
940 This option enables additional x86emu related debug messages.
942 Note: This option will increase the time to emulate a ROM.
947 bool "Output verbose x86emu debug messages"
949 depends on PCI_OPTION_ROM_RUN_YABEL
951 This option enables additional x86emu related debug messages.
953 Note: This option will increase the size of the coreboot image.
957 config X86EMU_DEBUG_JMP
958 bool "Trace JMP/RETF"
960 depends on X86EMU_DEBUG
962 Print information about JMP and RETF opcodes from x86emu.
964 Note: This option will increase the size of the coreboot image.
968 config X86EMU_DEBUG_TRACE
969 bool "Trace all opcodes"
971 depends on X86EMU_DEBUG
973 Print _all_ opcodes that are executed by x86emu.
975 WARNING: This will produce a LOT of output and take a long time.
977 Note: This option will increase the size of the coreboot image.
981 config X86EMU_DEBUG_PNP
982 bool "Log Plug&Play accesses"
984 depends on X86EMU_DEBUG
986 Print Plug And Play accesses made by option ROMs.
988 Note: This option will increase the size of the coreboot image.
992 config X86EMU_DEBUG_DISK
995 depends on X86EMU_DEBUG
997 Print Disk I/O related messages.
999 Note: This option will increase the size of the coreboot image.
1003 config X86EMU_DEBUG_PMM
1006 depends on X86EMU_DEBUG
1008 Print messages related to POST Memory Manager (PMM).
1010 Note: This option will increase the size of the coreboot image.
1015 config X86EMU_DEBUG_VBE
1016 bool "Debug VESA BIOS Extensions"
1018 depends on X86EMU_DEBUG
1020 Print messages related to VESA BIOS Extension (VBE) functions.
1022 Note: This option will increase the size of the coreboot image.
1026 config X86EMU_DEBUG_INT10
1027 bool "Redirect INT10 output to console"
1029 depends on X86EMU_DEBUG
1031 Let INT10 (i.e. character output) calls print messages to debug output.
1033 Note: This option will increase the size of the coreboot image.
1037 config X86EMU_DEBUG_INTERRUPTS
1038 bool "Log intXX calls"
1040 depends on X86EMU_DEBUG
1042 Print messages related to interrupt handling.
1044 Note: This option will increase the size of the coreboot image.
1048 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
1049 bool "Log special memory accesses"
1051 depends on X86EMU_DEBUG
1053 Print messages related to accesses to certain areas of the virtual
1054 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
1056 Note: This option will increase the size of the coreboot image.
1060 config X86EMU_DEBUG_MEM
1061 bool "Log all memory accesses"
1063 depends on X86EMU_DEBUG
1065 Print memory accesses made by option ROM.
1066 Note: This also includes accesses to fetch instructions.
1068 Note: This option will increase the size of the coreboot image.
1072 config X86EMU_DEBUG_IO
1073 bool "Log IO accesses"
1075 depends on X86EMU_DEBUG
1077 Print I/O accesses made by option ROM.
1079 Note: This option will increase the size of the coreboot image.
1083 config X86EMU_DEBUG_TIMINGS
1084 bool "Output timing information"
1086 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1088 Print timing information needed by i915tool.
1093 bool "Output verbose TPM debug messages"
1097 This option enables additional TPM related debug messages.
1099 config DEBUG_SPI_FLASH
1100 bool "Output verbose SPI flash debug messages"
1102 depends on SPI_FLASH
1104 This option enables additional SPI flash related debug messages.
1106 config DEBUG_USBDEBUG
1107 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1111 This option enables additional USB 2.0 debug dongle related messages.
1113 Select this to debug the connection of usbdebug dongle. Note that
1114 you need some other working console to receive the messages.
1116 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1117 # Only visible with the right southbridge and loglevel.
1118 config DEBUG_INTEL_ME
1119 bool "Verbose logging for Intel Management Engine"
1122 Enable verbose logging for Intel Management Engine driver that
1123 is present on Intel 6-series chipsets.
1127 bool "Trace function calls"
1130 If enabled, every function will print information to console once
1131 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1132 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1133 of calling function. Please note some printk releated functions
1134 are omitted from trace to have good looking console dumps.
1136 config DEBUG_COVERAGE
1137 bool "Debug code coverage"
1141 If enabled, the code coverage hooks in coreboot will output some
1142 information about the coverage data that is dumped.
1144 config GENERIC_GPIO_LIB
1145 bool "Build generic GPIO library"
1148 If enabled, compile the generic GPIO library. A "generic" GPIO
1149 implies configurability usually found on SoCs, particularly the
1150 ability to control internal pull resistors.
1152 config BOARD_ID_SUPPORT
1153 bool "Discover board ID and store it in coreboot table"
1155 select GENERIC_GPIO_LIB
1157 If enabled, coreboot discovers the board id of the hardware it is
1158 running on and reports it through the coreboot table to the rest of
1163 # These probably belong somewhere else, but they are needed somewhere.
1164 config ENABLE_APIC_EXT_ID
1168 config WARNINGS_ARE_ERRORS
1172 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1173 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1174 # mutually exclusive. One of these options must be selected in the
1175 # mainboard Kconfig if the chipset supports enabling and disabling of
1176 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1177 # in mainboard/Kconfig to know if the button should be enabled or not.
1179 config POWER_BUTTON_DEFAULT_ENABLE
1182 Select when the board has a power button which can optionally be
1183 disabled by the user.
1185 config POWER_BUTTON_DEFAULT_DISABLE
1188 Select when the board has a power button which can optionally be
1189 enabled by the user, e.g. when the board ships with a jumper over
1190 the power switch contacts.
1192 config POWER_BUTTON_FORCE_ENABLE
1195 Select when the board requires that the power button is always
1198 config POWER_BUTTON_FORCE_DISABLE
1201 Select when the board requires that the power button is always
1202 disabled, e.g. when it has been hardwired to ground.
1204 config POWER_BUTTON_IS_OPTIONAL
1206 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1207 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1209 Internal option that controls ENABLE_POWER_BUTTON visibility.
1215 Internal option that controls whether we compile in register scripts.
1217 config MAX_REBOOT_CNT
1221 Internal option that sets the maximum number of bootblock executions allowed
1222 with the normal image enabled before assuming the normal image is defective
1223 and switching to the fallback image.