2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
39 prompt "Compiler to use"
42 This option allows you to select the compiler used for building
44 You must build the coreboot crosscompiler for the board that you
47 To build all the GCC crosscompilers (takes a LONG time), run:
50 For help on individual architectures, run the command:
56 Use the GNU Compiler Collection (GCC) to build coreboot.
58 For details see http://gcc.gnu.org.
60 config COMPILER_LLVM_CLANG
61 bool "LLVM/clang (TESTING ONLY - Not currently working)"
63 Use LLVM/clang to build coreboot. To use this, you must build the
64 coreboot version of the clang compiler. Run the command
66 Note that this option is not currently working correctly and should
67 really only be selected if you're trying to work on getting clang
70 For details see http://clang.llvm.org.
75 bool "Allow building with any toolchain"
77 depends on COMPILER_GCC
79 Many toolchains break when building coreboot since it uses quite
80 unusual linker features. Unless developers explicitely request it,
81 we'll have to assume that they use their distro compiler by mistake.
82 Make sure that using patched compilers is a conscious decision.
85 bool "Use ccache to speed up (re)compilation"
88 Enables the use of ccache for faster builds.
90 Requires the ccache utility in your system $PATH.
92 For details see https://ccache.samba.org.
95 bool "Generate flashmap descriptor parser using flex and bison"
98 Enable this option if you are working on the flashmap descriptor
99 parser and made changes to fmd_scanner.l or fmd_parser.y.
101 Otherwise, say N to use the provided pregenerated scanner/parser.
103 config SCONFIG_GENPARSER
104 bool "Generate SCONFIG parser using flex and bison"
107 Enable this option if you are working on the sconfig device tree
108 parser and made changes to sconfig.l or sconfig.y.
110 Otherwise, say N to use the provided pregenerated scanner/parser.
112 config USE_OPTION_TABLE
113 bool "Use CMOS for configuration values"
114 depends on HAVE_OPTION_TABLE
116 Enable this option if coreboot shall read options from the "CMOS"
117 NVRAM instead of using hard-coded values.
119 config STATIC_OPTION_TABLE
120 bool "Load default configuration values into CMOS on each boot"
121 depends on USE_OPTION_TABLE
123 Enable this option to reset "CMOS" NVRAM values to default on
124 every boot. Use this if you want the NVRAM configuration to
125 never be modified from its default values.
127 config COMPRESS_RAMSTAGE
128 bool "Compress ramstage with LZMA"
129 # Default value set at the end of the file
131 Compress ramstage to save memory in the flash image. Note
132 that decompression might slow down booting if the boot flash
133 is connected through a slow link (i.e. SPI).
135 config COMPRESS_PRERAM_STAGES
136 bool "Compress romstage and verstage with LZ4"
138 # Default value set at the end of the file
140 Compress romstage and (if it exists) verstage with LZ4 to save flash
141 space and speed up boot, since the time for reading the image from SPI
142 (and in the vboot case verifying it) is usually much greater than the
143 time spent decompressing. Doesn't work for XIP stages (assume all
144 ARCH_X86 for now) for obvious reasons.
146 config INCLUDE_CONFIG_FILE
147 bool "Include the coreboot .config file into the ROM image"
148 # Default value set at the end of the file
150 Include the .config file that was used to compile coreboot
151 in the (CBFS) ROM image. This is useful if you want to know which
152 options were used to build a specific coreboot.rom image.
154 Saying Y here will increase the image size by 2-3KB.
156 You can use the following command to easily list the options:
158 grep -a CONFIG_ coreboot.rom
160 Alternatively, you can also use cbfstool to print the image
161 contents (including the raw 'config' item we're looking for).
165 $ cbfstool coreboot.rom print
166 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
170 Name Offset Type Size
171 cmos_layout.bin 0x0 cmos layout 1159
172 fallback/romstage 0x4c0 stage 339756
173 fallback/ramstage 0x53440 stage 186664
174 fallback/payload 0x80dc0 payload 51526
175 config 0x8d740 raw 3324
176 (empty) 0x8e480 null 3610440
178 config COLLECT_TIMESTAMPS
179 bool "Create a table of timestamps collected during boot"
181 Make coreboot create a table of timer-ID/timer-value pairs to
182 allow measuring time spent at different phases of the boot process.
185 bool "Allow use of binary-only repository"
187 This draws in the blobs repository, which contains binary files that
188 might be required for some chipsets or boards.
189 This flag ensures that a "Free" option remains available for users.
192 bool "Code coverage support"
193 depends on COMPILER_GCC
195 Add code coverage support for coreboot. This will store code
196 coverage information in CBMEM for extraction from user space.
199 config RELOCATABLE_RAMSTAGE
200 depends on EARLY_CBMEM_INIT
201 bool "Build the ramstage to be relocatable in 32-bit address space."
202 select RELOCATABLE_MODULES
204 The reloctable ramstage support allows for the ramstage to be built
205 as a relocatable module. The stage loader can identify a place
206 out of the OS way so that copying memory is unnecessary during an S3
207 wake. When selecting this option the romstage is responsible for
208 determing a stack location to use for loading the ramstage.
210 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
211 depends on RELOCATABLE_RAMSTAGE
214 The relocated ramstage is saved in an area specified by the
215 by the board and/or chipset.
218 bool "Update existing coreboot.rom image"
220 If this option is enabled, no new coreboot.rom file
221 is created. Instead it is expected that there already
222 is a suitable file for further processing.
223 The bootblock will not be modified.
225 If unsure, select 'N'
227 config BOARD_ID_STRING
229 # Default value set at the end of the file
230 depends on BOARD_ID_MANUAL
232 This string is placed in the 'board_id' CBFS file for indicating
235 config RAM_CODE_SUPPORT
238 If enabled, coreboot discovers RAM configuration (value obtained by
239 reading board straps) and stores it in coreboot table.
241 config BOOTSPLASH_IMAGE
242 bool "Add a bootsplash image"
244 Select this option if you have a bootsplash image that you would
245 like to add to your ROM.
247 This will only add the image to the ROM. To actually run it check
248 options under 'Display' section.
250 config BOOTSPLASH_FILE
251 string "Bootsplash path and filename"
252 depends on BOOTSPLASH_IMAGE
253 # Default value set at the end of the file
255 The path and filename of the file to use as graphical bootsplash
256 screen. The file format has to be jpg.
262 source "src/mainboard/Kconfig"
266 default "devicetree.cb"
268 This symbol allows mainboards to select a different file under their
269 mainboard directory for the devicetree.cb file. This allows the board
270 variants that need different devicetrees to be in the same directory.
272 Examples: "devicetree.variant.cb"
273 "variant/devicetree.cb"
276 hex "Size of CBFS filesystem in ROM"
277 # Default value set at the end of the file
279 This is the part of the ROM actually managed by CBFS, located at the
280 end of the ROM (passed through cbfstool -o) on x86 and at at the start
281 of the ROM (passed through cbfstool -s) everywhere else. It defaults
282 to span the whole ROM on all but Intel systems that use an Intel Firmware
283 Descriptor. It can be overridden to make coreboot live alongside other
284 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
288 string "fmap description file in fmd format"
289 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
292 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
293 but in some cases more complex setups are required.
294 When an fmd is specified, it overrides the default format.
296 config MAINBOARD_HAS_TPM2
300 There is a TPM device installed on the mainboard, and it is
301 compliant with version 2 TCG TPM specification. Could be connected
302 over LPC, SPI or I2C.
306 # load site-local kconfig to allow user specific defaults and overrides
307 source "site-local/Kconfig"
309 config SYSTEM_TYPE_LAPTOP
313 config CBFS_AUTOGEN_ATTRIBUTES
317 If this option is selected, every file in cbfs which has a constraint
318 regarding position or alignment will get an additional file attribute
319 which describes this constraint.
324 source "src/soc/*/*/Kconfig"
326 source "src/cpu/Kconfig"
327 comment "Northbridge"
328 source "src/northbridge/*/*/Kconfig"
329 comment "Southbridge"
330 source "src/southbridge/*/*/Kconfig"
332 source "src/superio/*/*/Kconfig"
333 comment "Embedded Controllers"
334 source "src/ec/acpi/Kconfig"
335 source "src/ec/*/*/Kconfig"
336 # FIXME move to vendorcode
337 source "src/drivers/intel/fsp1_0/Kconfig"
339 source "src/southbridge/intel/common/firmware/Kconfig"
340 source "src/vboot/Kconfig"
341 source "src/vendorcode/*/Kconfig"
343 source "src/arch/*/Kconfig"
347 source "src/device/Kconfig"
349 menu "Generic Drivers"
350 source "src/drivers/*/Kconfig"
351 source "src/drivers/*/*/Kconfig"
354 source "src/acpi/Kconfig"
356 # This option is for the current boards/chipsets where SPI flash
357 # is not the boot device. Currently nearly all boards/chipsets assume
358 # SPI flash is the boot device.
359 config BOOT_DEVICE_NOT_SPI_FLASH
363 config BOOT_DEVICE_SPI_FLASH
365 default y if !BOOT_DEVICE_NOT_SPI_FLASH
368 config BOOT_DEVICE_MEMORY_MAPPED
370 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
373 Inform system if SPI is memory-mapped or not.
375 config BOOT_DEVICE_SUPPORTS_WRITES
379 Indicate that the platform has writable boot device
389 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
390 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
392 Enable this option to enable TPM support in coreboot.
398 select LPC_TPM if MAINBOARD_HAS_LPC_TPM
399 select I2C_TPM if !MAINBOARD_HAS_LPC_TPM && !SPI_TPM
401 Enable this option to enable TPM2 support in coreboot.
411 default 0x1000 if ARCH_X86
418 source "src/console/Kconfig"
420 config HAVE_ACPI_RESUME
424 config ACPI_HUGE_LOWMEM_BACKUP
428 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
430 config RESUME_PATH_SAME_AS_BOOT
432 default y if ARCH_X86
433 depends on HAVE_ACPI_RESUME
435 This option indicates that when a system resumes it takes the
436 same path as a regular boot. e.g. an x86 system runs from the
437 reset vector at 0xfffffff0 on both resume and warm/cold boot.
439 config HAVE_HARD_RESET
443 This variable specifies whether a given board has a hard_reset
444 function, no matter if it's provided by board code or chipset code.
446 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
448 depends on EARLY_CBMEM_INIT
451 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
453 depends on EARLY_CBMEM_INIT
456 This should be enabled on certain plaforms, such as the AMD
457 SR565x, that cannot handle concurrent CBFS accesses from
458 multiple APs during early startup.
460 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
462 depends on EARLY_CBMEM_INIT
465 config HAVE_MONOTONIC_TIMER
468 The board/chipset provides a monotonic timer.
470 config GENERIC_UDELAY
472 depends on HAVE_MONOTONIC_TIMER
474 The board/chipset uses a generic udelay function utilizing the
479 depends on HAVE_MONOTONIC_TIMER
481 Provide a timer queue for performing time-based callbacks.
483 config COOP_MULTITASKING
485 depends on TIMER_QUEUE && ARCH_X86
487 Cooperative multitasking allows callbacks to be multiplexed on the
488 main thread of ramstage. With this enabled it allows for multiple
489 execution paths to take place when they have udelay() calls within
495 depends on COOP_MULTITASKING
497 How many execution threads to cooperatively multitask with.
499 config HAVE_OPTION_TABLE
503 This variable specifies whether a given board has a cmos.layout
504 file containing NVRAM/CMOS bit definitions.
505 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
511 config HAVE_SMI_HANDLER
515 config PCI_IO_CFG_EXT
523 config CACHE_ROM_SIZE_OVERRIDE
527 # TODO: Can probably be removed once all chipsets have kconfig options for it.
532 config USE_WATCHDOG_ON_BOOT
540 Build board-specific VGA code.
546 Enable Unified Memory Architecture for graphics.
548 config HAVE_ACPI_TABLES
551 This variable specifies whether a given board has ACPI table support.
552 It is usually set in mainboard/*/Kconfig.
557 This variable specifies whether a given board has MP table support.
558 It is usually set in mainboard/*/Kconfig.
559 Whether or not the MP table is actually generated by coreboot
560 is configurable by the user via GENERATE_MP_TABLE.
562 config HAVE_PIRQ_TABLE
565 This variable specifies whether a given board has PIRQ table support.
566 It is usually set in mainboard/*/Kconfig.
567 Whether or not the PIRQ table is actually generated by coreboot
568 is configurable by the user via GENERATE_PIRQ_TABLE.
570 config MAX_PIRQ_LINKS
574 This variable specifies the number of PIRQ interrupt links which are
575 routable. On most chipsets, this is 4, INTA through INTD. Some
576 chipsets offer more than four links, commonly up to INTH. They may
577 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
578 table specifies links greater than 4, pirq_route_irqs will not
579 function properly, unless this variable is correctly set.
589 Build support for NHLT (non HD Audio) ACPI table generation.
591 #These Options are here to avoid "undefined" warnings.
592 #The actual selection and help texts are in the following menu.
596 config GENERATE_MP_TABLE
597 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
599 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
601 Generate an MP table (conforming to the Intel MultiProcessor
602 specification 1.4) for this board.
606 config GENERATE_PIRQ_TABLE
607 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
609 default HAVE_PIRQ_TABLE
611 Generate a PIRQ table for this board.
615 config GENERATE_SMBIOS_TABLES
617 bool "Generate SMBIOS tables"
620 Generate SMBIOS tables for this board.
624 config SMBIOS_PROVIDED_BY_MOBO
628 config MAINBOARD_SERIAL_NUMBER
629 string "SMBIOS Serial Number"
630 depends on GENERATE_SMBIOS_TABLES
631 depends on !SMBIOS_PROVIDED_BY_MOBO
634 The Serial Number to store in SMBIOS structures.
636 config MAINBOARD_VERSION
637 string "SMBIOS Version Number"
638 depends on GENERATE_SMBIOS_TABLES
639 depends on !SMBIOS_PROVIDED_BY_MOBO
642 The Version Number to store in SMBIOS structures.
644 config MAINBOARD_SMBIOS_MANUFACTURER
645 string "SMBIOS Manufacturer"
646 depends on GENERATE_SMBIOS_TABLES
647 depends on !SMBIOS_PROVIDED_BY_MOBO
648 default MAINBOARD_VENDOR
650 Override the default Manufacturer stored in SMBIOS structures.
652 config MAINBOARD_SMBIOS_PRODUCT_NAME
653 string "SMBIOS Product name"
654 depends on GENERATE_SMBIOS_TABLES
655 depends on !SMBIOS_PROVIDED_BY_MOBO
656 default MAINBOARD_PART_NUMBER
658 Override the default Product name stored in SMBIOS structures.
662 source "payloads/Kconfig"
666 # TODO: Better help text and detailed instructions.
668 bool "GDB debugging support"
670 depends on CONSOLE_SERIAL
672 If enabled, you will be able to set breakpoints for gdb debugging.
673 See src/arch/x86/lib/c_start.S for details.
676 bool "Wait for a GDB connection"
680 If enabled, coreboot will wait for a GDB connection.
683 bool "Halt when hitting a BUG() or assertion error"
686 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
689 bool "Output verbose CBFS debug messages"
692 This option enables additional CBFS related debug messages.
694 config HAVE_DEBUG_RAM_SETUP
697 config DEBUG_RAM_SETUP
698 bool "Output verbose RAM init debug messages"
700 depends on HAVE_DEBUG_RAM_SETUP
702 This option enables additional RAM init related debug messages.
703 It is recommended to enable this when debugging issues on your
704 board which might be RAM init related.
706 Note: This option will increase the size of the coreboot image.
710 config HAVE_DEBUG_CAR
715 depends on HAVE_DEBUG_CAR
717 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
718 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
719 # printk(BIOS_DEBUG, ...) calls.
721 bool "Output verbose Cache-as-RAM debug messages"
723 depends on HAVE_DEBUG_CAR
725 This option enables additional CAR related debug messages.
729 bool "Check PIRQ table consistency"
731 depends on GENERATE_PIRQ_TABLE
735 config HAVE_DEBUG_SMBUS
739 bool "Output verbose SMBus debug messages"
741 depends on HAVE_DEBUG_SMBUS
743 This option enables additional SMBus (and SPD) debug messages.
745 Note: This option will increase the size of the coreboot image.
750 bool "Output verbose SMI debug messages"
752 depends on HAVE_SMI_HANDLER
753 select SPI_FLASH_SMM if SPI_CONSOLE
755 This option enables additional SMI related debug messages.
757 Note: This option will increase the size of the coreboot image.
761 config DEBUG_SMM_RELOCATION
762 bool "Debug SMM relocation code"
764 depends on HAVE_SMI_HANDLER
766 This option enables additional SMM handler relocation related
769 Note: This option will increase the size of the coreboot image.
773 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
774 # printk(BIOS_DEBUG, ...) calls.
776 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
780 This option enables additional malloc related debug messages.
782 Note: This option will increase the size of the coreboot image.
786 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
787 # printk(BIOS_DEBUG, ...) calls.
789 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
793 This option enables additional ACPI related debug messages.
795 Note: This option will slightly increase the size of the coreboot image.
799 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
800 # printk(BIOS_DEBUG, ...) calls.
801 config REALMODE_DEBUG
802 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
805 depends on PCI_OPTION_ROM_RUN_REALMODE
807 This option enables additional x86emu related debug messages.
809 Note: This option will increase the time to emulate a ROM.
814 bool "Output verbose x86emu debug messages"
816 depends on PCI_OPTION_ROM_RUN_YABEL
818 This option enables additional x86emu related debug messages.
820 Note: This option will increase the size of the coreboot image.
824 config X86EMU_DEBUG_JMP
825 bool "Trace JMP/RETF"
827 depends on X86EMU_DEBUG
829 Print information about JMP and RETF opcodes from x86emu.
831 Note: This option will increase the size of the coreboot image.
835 config X86EMU_DEBUG_TRACE
836 bool "Trace all opcodes"
838 depends on X86EMU_DEBUG
840 Print _all_ opcodes that are executed by x86emu.
842 WARNING: This will produce a LOT of output and take a long time.
844 Note: This option will increase the size of the coreboot image.
848 config X86EMU_DEBUG_PNP
849 bool "Log Plug&Play accesses"
851 depends on X86EMU_DEBUG
853 Print Plug And Play accesses made by option ROMs.
855 Note: This option will increase the size of the coreboot image.
859 config X86EMU_DEBUG_DISK
862 depends on X86EMU_DEBUG
864 Print Disk I/O related messages.
866 Note: This option will increase the size of the coreboot image.
870 config X86EMU_DEBUG_PMM
873 depends on X86EMU_DEBUG
875 Print messages related to POST Memory Manager (PMM).
877 Note: This option will increase the size of the coreboot image.
882 config X86EMU_DEBUG_VBE
883 bool "Debug VESA BIOS Extensions"
885 depends on X86EMU_DEBUG
887 Print messages related to VESA BIOS Extension (VBE) functions.
889 Note: This option will increase the size of the coreboot image.
893 config X86EMU_DEBUG_INT10
894 bool "Redirect INT10 output to console"
896 depends on X86EMU_DEBUG
898 Let INT10 (i.e. character output) calls print messages to debug output.
900 Note: This option will increase the size of the coreboot image.
904 config X86EMU_DEBUG_INTERRUPTS
905 bool "Log intXX calls"
907 depends on X86EMU_DEBUG
909 Print messages related to interrupt handling.
911 Note: This option will increase the size of the coreboot image.
915 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
916 bool "Log special memory accesses"
918 depends on X86EMU_DEBUG
920 Print messages related to accesses to certain areas of the virtual
921 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
923 Note: This option will increase the size of the coreboot image.
927 config X86EMU_DEBUG_MEM
928 bool "Log all memory accesses"
930 depends on X86EMU_DEBUG
932 Print memory accesses made by option ROM.
933 Note: This also includes accesses to fetch instructions.
935 Note: This option will increase the size of the coreboot image.
939 config X86EMU_DEBUG_IO
940 bool "Log IO accesses"
942 depends on X86EMU_DEBUG
944 Print I/O accesses made by option ROM.
946 Note: This option will increase the size of the coreboot image.
950 config X86EMU_DEBUG_TIMINGS
951 bool "Output timing information"
953 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
955 Print timing information needed by i915tool.
960 bool "Output verbose TPM debug messages"
962 depends on TPM || TPM2
964 This option enables additional TPM related debug messages.
966 config DEBUG_SPI_FLASH
967 bool "Output verbose SPI flash debug messages"
971 This option enables additional SPI flash related debug messages.
973 config DEBUG_USBDEBUG
974 bool "Output verbose USB 2.0 EHCI debug dongle messages"
978 This option enables additional USB 2.0 debug dongle related messages.
980 Select this to debug the connection of usbdebug dongle. Note that
981 you need some other working console to receive the messages.
983 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
984 # Only visible with the right southbridge and loglevel.
985 config DEBUG_INTEL_ME
986 bool "Verbose logging for Intel Management Engine"
989 Enable verbose logging for Intel Management Engine driver that
990 is present on Intel 6-series chipsets.
994 bool "Trace function calls"
997 If enabled, every function will print information to console once
998 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
999 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1000 of calling function. Please note some printk related functions
1001 are omitted from trace to have good looking console dumps.
1003 config DEBUG_COVERAGE
1004 bool "Debug code coverage"
1008 If enabled, the code coverage hooks in coreboot will output some
1009 information about the coverage data that is dumped.
1011 config DEBUG_BOOT_STATE
1012 bool "Debug boot state machine"
1015 Control debugging of the boot state machine. When selected displays
1016 the state boundaries in ramstage.
1018 config DEBUG_PRINT_PAGE_TABLES
1019 bool "Print the page tables after construction"
1021 depends on ARCH_RISCV
1023 After the page tables have been built, print them on the debug
1026 config DEBUG_ADA_CODE
1027 bool "Compile debug code in Ada sources"
1030 Add the compiler switch `-gnata` to compile code guarded by
1036 ###############################################################################
1037 # Set variables with no prompt - these can be set anywhere, and putting at
1038 # the end of this file gives the most flexibility.
1039 config ENABLE_APIC_EXT_ID
1043 config WARNINGS_ARE_ERRORS
1047 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1048 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1049 # mutually exclusive. One of these options must be selected in the
1050 # mainboard Kconfig if the chipset supports enabling and disabling of
1051 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1052 # in mainboard/Kconfig to know if the button should be enabled or not.
1054 config POWER_BUTTON_DEFAULT_ENABLE
1057 Select when the board has a power button which can optionally be
1058 disabled by the user.
1060 config POWER_BUTTON_DEFAULT_DISABLE
1063 Select when the board has a power button which can optionally be
1064 enabled by the user, e.g. when the board ships with a jumper over
1065 the power switch contacts.
1067 config POWER_BUTTON_FORCE_ENABLE
1070 Select when the board requires that the power button is always
1073 config POWER_BUTTON_FORCE_DISABLE
1076 Select when the board requires that the power button is always
1077 disabled, e.g. when it has been hardwired to ground.
1079 config POWER_BUTTON_IS_OPTIONAL
1081 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1082 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1084 Internal option that controls ENABLE_POWER_BUTTON visibility.
1090 Internal option that controls whether we compile in register scripts.
1092 config MAX_REBOOT_CNT
1096 Internal option that sets the maximum number of bootblock executions allowed
1097 with the normal image enabled before assuming the normal image is defective
1098 and switching to the fallback image.
1100 config CREATE_BOARD_CHECKLIST
1104 When selected, creates a webpage showing the implementation status for
1105 the board. Routines highlighted in green are complete, yellow are
1106 optional and red are required and must be implemented. A table is
1107 produced for each stage of the boot process except the bootblock. The
1108 red items may be used as an implementation checklist for the board.
1110 config MAKE_CHECKLIST_PUBLIC
1114 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1115 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1118 config CHECKLIST_DATA_FILE_LOCATION
1121 Location of the <stage>_complete.dat and <stage>_optional.dat files
1122 that are consumed during checklist processing. <stage>_complete.dat
1123 contains the symbols that are expected to be in the resulting image.
1124 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1125 a list of weak symbols which the resulting image may consume. Other
1126 symbols contained only in <stage>_complete.dat will be flagged as
1127 required and not implemented if a weak implementation is found in the
1133 Selected by features that use Ada code in ramstage.
1135 config RAMSTAGE_LIBHWBASE
1139 Selected by features that require `libhwbase` in ramstage.
1141 config HWBASE_DYNAMIC_MMIO
1144 config UNCOMPRESSED_RAMSTAGE
1147 config NO_XIP_EARLY_STAGES
1149 default n if ARCH_X86
1152 Identify if early stages are eXecute-In-Place(XIP).
1154 config EARLY_CBMEM_INIT
1155 def_bool !LATE_CBMEM_INIT
1157 config EARLY_CBMEM_LIST
1161 Enable display of CBMEM during romstage and postcar.
1163 config RELOCATABLE_MODULES
1166 If RELOCATABLE_MODULES is selected then support is enabled for
1167 building relocatable modules in the RAM stage. Those modules can be
1168 loaded anywhere and all the relocations are handled automatically.
1170 config NO_STAGE_CACHE
1173 Do not save any component in stage cache for resume path. On resume,
1174 all components would be read back from CBFS again.
1176 config GENERIC_GPIO_LIB
1179 If enabled, compile the generic GPIO library. A "generic" GPIO
1180 implies configurability usually found on SoCs, particularly the
1181 ability to control internal pull resistors.
1183 config GENERIC_SPD_BIN
1186 If enabled, add support for adding spd.hex files in cbfs as spd.bin
1187 and locating it runtime to load SPD. Additionally provide provision to
1188 fetch SPD over SMBus.
1193 depends on GENERIC_SPD_BIN
1195 Total number of memory DIMM slots available on motherboard.
1196 It is multiplication of number of channel to number of DIMMs per
1199 config DIMM_SPD_SIZE
1203 Total SPD size that will be used for DIMM.
1204 Ex: DDR3 256, DDR4 512.
1206 config BOARD_ID_AUTO
1210 Mainboards that can read a board ID from the hardware straps
1211 (ie. GPIO) select this configuration option.
1213 config BOARD_ID_MANUAL
1216 depends on !BOARD_ID_AUTO
1218 If you want to maintain a board ID, but the hardware does not
1219 have straps to automatically determine the ID, you can say Y
1220 here and add a file named 'board_id' to CBFS. If you don't know
1221 what this is about, say N.
1223 config BOOTBLOCK_CUSTOM
1224 # To be selected by arch, SoC or mainboard if it does not want use the normal
1225 # src/lib/bootblock.c#main() C entry point.
1228 config C_ENVIRONMENT_BOOTBLOCK
1229 # To be selected by arch or platform if a C environment is available during the
1230 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1233 ###############################################################################
1234 # Set default values for symbols created before mainboards. This allows the
1235 # option to be displayed in the general menu, but the default to be loaded in
1236 # the mainboard if desired.
1237 config COMPRESS_RAMSTAGE
1238 default y if !UNCOMPRESSED_RAMSTAGE
1240 config COMPRESS_PRERAM_STAGES
1241 depends on !ARCH_X86
1244 config INCLUDE_CONFIG_FILE
1247 config BOARD_ID_STRING
1249 depends on BOARD_ID_MANUAL
1251 config BOOTSPLASH_FILE
1252 depends on BOOTSPLASH_IMAGE
1253 default "bootsplash.jpg"