src/cpu/intel/model_206ax/acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <acpi/acpi.h>
   5 #include <acpi/acpigen.h>
   6 #include <arch/cpu.h>
   7 #include <cpu/x86/msr.h>
   8 #include <cpu/intel/speedstep.h>
   9 #include <cpu/intel/turbo.h>
  10 #include <device/device.h>
  11 #include <stdint.h>
  12
  13 #include "model_206ax.h"
  14 #include "chip.h"
  15
  16 static int get_logical_cores_per_package(void)
  17 {
  18         msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT);
  19         return msr.lo & 0xffff;
  20 }
  21
  22 static void generate_C_state_entries(void)
  23 {
  24         struct cpu_info *info;
  25         struct cpu_driver *cpu;
  26         struct device *lapic;
  27         struct cpu_intel_model_206ax_config *conf = NULL;
  28
  29         /* Find the SpeedStep CPU in the device tree using magic APIC ID */
  30         lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
  31         if (!lapic)
  32                 return;
  33         conf = lapic->chip_info;
  34         if (!conf)
  35                 return;
  36
  37         /* Find CPU map of supported C-states */
  38         info = cpu_info();
  39         if (!info)
  40                 return;
  41         cpu = find_cpu_driver(info->cpu);
  42         if (!cpu || !cpu->cstates)
  43                 return;
  44
  45         const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 };
  46
  47         acpi_cstate_t acpi_cstate_map[ARRAY_SIZE(acpi_cstates)] = { 0 };
  48
  49         /* Count number of active C-states */
  50         int count = 0;
  51
  52         for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) {
  53                 if (acpi_cstates[i] > 0) {
  54                         acpi_cstate_map[count] = cpu->cstates[acpi_cstates[i]];
  55                         acpi_cstate_map[count].ctype = i + 1;
  56                         count++;
  57                 }
  58         }
  59         acpigen_write_CST_package(acpi_cstate_map, count);
  60 }
  61
  62 static acpi_tstate_t tss_table_fine[] = {
  63         { 100, 1000, 0, 0x00, 0 },
  64         { 94, 940, 0, 0x1f, 0 },
  65         { 88, 880, 0, 0x1e, 0 },
  66         { 82, 820, 0, 0x1d, 0 },
  67         { 75, 760, 0, 0x1c, 0 },
  68         { 69, 700, 0, 0x1b, 0 },
  69         { 63, 640, 0, 0x1a, 0 },
  70         { 57, 580, 0, 0x19, 0 },
  71         { 50, 520, 0, 0x18, 0 },
  72         { 44, 460, 0, 0x17, 0 },
  73         { 38, 400, 0, 0x16, 0 },
  74         { 32, 340, 0, 0x15, 0 },
  75         { 25, 280, 0, 0x14, 0 },
  76         { 19, 220, 0, 0x13, 0 },
  77         { 13, 160, 0, 0x12, 0 },
  78 };
  79
  80 static acpi_tstate_t tss_table_coarse[] = {
  81         { 100, 1000, 0, 0x00, 0 },
  82         { 88, 875, 0, 0x1f, 0 },
  83         { 75, 750, 0, 0x1e, 0 },
  84         { 63, 625, 0, 0x1d, 0 },
  85         { 50, 500, 0, 0x1c, 0 },
  86         { 38, 375, 0, 0x1b, 0 },
  87         { 25, 250, 0, 0x1a, 0 },
  88         { 13, 125, 0, 0x19, 0 },
  89 };
  90
  91 static void generate_T_state_entries(int core, int cores_per_package)
  92 {
  93         /* Indicate SW_ALL coordination for T-states */
  94         acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
  95
  96         /* Indicate FFixedHW so OS will use MSR */
  97         acpigen_write_empty_PTC();
  98
  99         /* Set a T-state limit that can be modified in NVS */
 100         acpigen_write_TPC("\\TLVL");
 101
 102         /*
 103          * CPUID.(EAX=6):EAX[5] indicates support
 104          * for extended throttle levels.
 105          */
 106         if (cpuid_eax(6) & (1 << 5))
 107                 acpigen_write_TSS_package(
 108                         ARRAY_SIZE(tss_table_fine), tss_table_fine);
 109         else
 110                 acpigen_write_TSS_package(
 111                         ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 112 }
 113
 114 static int calculate_power(int tdp, int p1_ratio, int ratio)
 115 {
 116         u32 m;
 117         u32 power;
 118
 119         /*
 120          * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
 121          *
 122          * Power = (ratio / p1_ratio) * m * tdp
 123          */
 124
 125         m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
 126         m = (m * m) / 1000;
 127
 128         power = ((ratio * 100000 / p1_ratio) / 100);
 129         power *= (m / 100) * (tdp / 1000);
 130         power /= 1000;
 131
 132         return (int)power;
 133 }
 134
 135 static void generate_P_state_entries(int core, int cores_per_package)
 136 {
 137         int ratio_min, ratio_max, ratio_turbo, ratio_step;
 138         int coord_type, power_max, power_unit, num_entries;
 139         int ratio, power, clock, clock_max;
 140         msr_t msr;
 141
 142         /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
 143         msr = rdmsr(MSR_MISC_PWR_MGMT);
 144         if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
 145                 coord_type = SW_ANY;
 146         else
 147                 coord_type = HW_ALL;
 148
 149         /* Get bus ratio limits and calculate clock speeds */
 150         msr = rdmsr(MSR_PLATFORM_INFO);
 151         ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
 152
 153         /* Determine if this CPU has configurable TDP */
 154         if (cpu_config_tdp_levels()) {
 155                 /* Set max ratio to nominal TDP ratio */
 156                 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
 157                 ratio_max = msr.lo & 0xff;
 158         } else {
 159                 /* Max Non-Turbo Ratio */
 160                 ratio_max = (msr.lo >> 8) & 0xff;
 161         }
 162         clock_max = ratio_max * SANDYBRIDGE_BCLK;
 163
 164         /* Calculate CPU TDP in mW */
 165         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 166         power_unit = 2 << ((msr.lo & 0xf) - 1);
 167         msr = rdmsr(MSR_PKG_POWER_SKU);
 168         power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
 169
 170         /* Write _PCT indicating use of FFixedHW */
 171         acpigen_write_empty_PCT();
 172
 173         /* Write _PPC with no limit on supported P-state */
 174         acpigen_write_PPC_NVS();
 175
 176         /* Write PSD indicating configured coordination type */
 177         acpigen_write_PSD_package(core, cores_per_package, coord_type);
 178
 179         /* Add P-state entries in _PSS table */
 180         acpigen_write_name("_PSS");
 181
 182         /* Determine ratio points */
 183         ratio_step = PSS_RATIO_STEP;
 184         num_entries = (ratio_max - ratio_min) / ratio_step;
 185         while (num_entries > PSS_MAX_ENTRIES-1) {
 186                 ratio_step <<= 1;
 187                 num_entries >>= 1;
 188         }
 189
 190         /* P[T] is Turbo state if enabled */
 191         if (get_turbo_state() == TURBO_ENABLED) {
 192                 /* _PSS package count including Turbo */
 193                 acpigen_write_package(num_entries + 2);
 194
 195                 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
 196                 ratio_turbo = msr.lo & 0xff;
 197
 198                 /* Add entry for Turbo ratio */
 199                 acpigen_write_PSS_package(
 200                         clock_max + 1,          /*MHz*/
 201                         power_max,              /*mW*/
 202                         PSS_LATENCY_TRANSITION, /*lat1*/
 203                         PSS_LATENCY_BUSMASTER,  /*lat2*/
 204                         ratio_turbo << 8,       /*control*/
 205                         ratio_turbo << 8);      /*status*/
 206         } else {
 207                 /* _PSS package count without Turbo */
 208                 acpigen_write_package(num_entries + 1);
 209         }
 210
 211         /* First regular entry is max non-turbo ratio */
 212         acpigen_write_PSS_package(
 213                 clock_max,              /*MHz*/
 214                 power_max,              /*mW*/
 215                 PSS_LATENCY_TRANSITION, /*lat1*/
 216                 PSS_LATENCY_BUSMASTER,  /*lat2*/
 217                 ratio_max << 8,         /*control*/
 218                 ratio_max << 8);        /*status*/
 219
 220         /* Generate the remaining entries */
 221         for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 222              ratio >= ratio_min; ratio -= ratio_step) {
 223
 224                 /* Calculate power at this ratio */
 225                 power = calculate_power(power_max, ratio_max, ratio);
 226                 clock = ratio * SANDYBRIDGE_BCLK;
 227
 228                 acpigen_write_PSS_package(
 229                         clock,                  /*MHz*/
 230                         power,                  /*mW*/
 231                         PSS_LATENCY_TRANSITION, /*lat1*/
 232                         PSS_LATENCY_BUSMASTER,  /*lat2*/
 233                         ratio << 8,             /*control*/
 234                         ratio << 8);            /*status*/
 235         }
 236
 237         /* Fix package length */
 238         acpigen_pop_len();
 239 }
 240
 241 void generate_cpu_entries(const struct device *device)
 242 {
 243         int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 244         int totalcores = dev_count_cpu();
 245         int cores_per_package = get_logical_cores_per_package();
 246         int numcpus = totalcores/cores_per_package;
 247
 248         printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
 249                numcpus, cores_per_package);
 250
 251         for (cpuID = 1; cpuID <= numcpus; cpuID++) {
 252                 for (coreID = 1; coreID <= cores_per_package; coreID++) {
 253                         if (coreID > 1) {
 254                                 pcontrol_blk = 0;
 255                                 plen = 0;
 256                         }
 257
 258                         /* Generate processor \_SB.CPUx */
 259                         acpigen_write_processor(
 260                                 (cpuID-1)*cores_per_package+coreID-1,
 261                                 pcontrol_blk, plen);
 262
 263                         /* Generate P-state tables */
 264                         generate_P_state_entries(
 265                                 cpuID-1, cores_per_package);
 266
 267                         /* Generate C-state tables */
 268                         generate_C_state_entries();
 269
 270                         /* Generate T-state tables */
 271                         generate_T_state_entries(
 272                                 cpuID-1, cores_per_package);
 273
 274                         acpigen_pop_len();
 275                 }
 276         }
 277
 278         /* PPKG is usually used for thermal management
 279            of the first and only package. */
 280         acpigen_write_processor_package("PPKG", 0, cores_per_package);
 281
 282         /* Add a method to notify processor nodes */
 283         acpigen_write_processor_cnot(cores_per_package);
 284 }
 285
 286 struct chip_operations cpu_intel_model_206ax_ops = {
 287         CHIP_NAME("Intel SandyBridge/IvyBridge CPU")
 288 };