2 * This file is part of msrtool.
4 * Copyright (C) 2013 Olivier Langlois <olivier@olivierlanglois.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 int intel_atom_probe(const struct targetdef
*target
, const struct cpuid_t
*id
) {
23 return (0x6 == id
->family
) &&
27 const struct msrdef intel_atom_msrs
[] = {
28 {0x0, MSRTYPE_RDWR
, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\
29 Machine-Check Exception Address", {
32 {0x1, MSRTYPE_RDWR
, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\
33 Machine-Check Exception Type", {
36 {0x10, MSRTYPE_RDWR
, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", {
39 {0x17, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PLATFORM_ID", "", {
42 {0x2a, MSRTYPE_RDWR
, MSR2(0,0), "MSR_EBL_CR_POWERON", "", {
45 {0xcd, MSRTYPE_RDONLY
, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", {
48 {0xfe, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRRCAP", "", {
51 {0x11e, MSRTYPE_RDWR
, MSR2(0,0), "MSR_BBL_CR_CTL3", "", {
54 {0x198, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERF_STATUS", "", {
56 { 44, 5, "Maximum Bus Ratio", "R/O", PRESENT_DEC
, {
60 { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX
, {
65 {0x19d, MSRTYPE_RDWR
, MSR2(0,0), "MSR_THERM2_CTL", "", {
68 {0x200, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", {
71 {0x201, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", {
74 {0x202, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", {
77 {0x203, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", {
80 {0x204, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", {
83 {0x205, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", {
86 {0x206, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", {
89 {0x207, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", {
92 {0x208, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", {
95 {0x209, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", {
98 {0x20a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", {
101 {0x20b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", {
104 {0x20c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", {
107 {0x20d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", {
111 {0x20e, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", {
114 {0x20f, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", {
118 {0x250, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
121 {0x258, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
124 {0x259, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
127 {0x268, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
130 {0x269, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
133 {0x26a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
136 {0x26b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
139 {0x26c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
142 {0x26d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
145 {0x26e, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
148 {0x26f, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
151 /* if CPUID.01H: ECX[15] = 1 */
152 {0x345, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
153 /* Additional info available at Section 17.4.1 of
154 * Intel 64 and IA-32 Architecures Software Developer's
157 { 63, 50, RESERVED
},
158 { 13, 1, "Counter width", "R/O", PRESENT_BIN
, {
159 { MSR1(0), "Nothing" },
160 { MSR1(1), "Full width of counter writable via IA32_A_PMCx" },
163 { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN
, {
164 { MSR1(0), "Nothing" },
165 { MSR1(1), "Freeze while SMM is supported" },
168 { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX
, {
171 { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN
, {
174 { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN
, {
177 { 5, 6, "LBR Format", "R/O", PRESENT_HEX
, {
182 {0x400, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCO_CTL", "", {
185 {0x401, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCO_STATUS", "", {
188 {0x402, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCO_ADDR", "", {
191 {0x404, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC1_CTL", "", {
194 {0x405, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC1_STATUS", "", {
197 {0x408, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC2_CTL", "", {
200 {0x409, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC2_STATUS", "", {
203 {0x40a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC2_ADDR", "", {
206 {0x40c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC4_CTL", "", {
209 {0x40d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC4_STATUS", "", {
212 {0x40e, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC4_ADDR", "", {
215 {0x410, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC3_CTL", "", {
218 {0x411, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC3_STATUS", "", {
221 {0x412, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MC3_ADDR", "", {
225 /* ==========================================================================
227 * ==========================================================================
230 {0x6, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", {
233 {0x10, MSRTYPE_RDWR
, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", {
236 {0x1b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", {
237 /* In Intel's manual there is MAXPHYWID,
238 * which determine index of highest bit of
239 * APIC Base itself, so marking it as
242 { 63, 52, RESERVED
},
243 { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN
, {
246 { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN
, {
247 { MSR1(0), "x2APIC mode is disabled" },
248 { MSR1(1), "x2APIC mode is enabled" },
252 { 8, 1, "BSP Flag", "R/W", PRESENT_BIN
, {
258 /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */
259 {0x3a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_FEATURE_CONTROL",
260 "Control features in Intel 64Processor", {
261 { 63, 48, RESERVED
},
262 /* if CPUID.01H: ECX[6] = 1 */
263 { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN
, {
264 { MSR1(0), "SENTER leaf functions are disabled" },
265 { MSR1(1), "SENTER leaf functions are enabled" },
268 /* if CPUID.01H: ECX[6] = 1 */
269 { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN
, {
273 /* if CPUID.01H: ECX[5 or 6] = 1 */
274 { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN
, {
275 /* This bit enables VMX for system executive
276 * that do not require SMX.
278 { MSR1(0), "VMX outside of SMX operation disabled" },
279 { MSR1(1), "VMX outside of SMX operation enabled" },
282 { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN
, {
283 /* This bit enables a system executive to use
284 * VMX in conjuction with SMX to support Intel
285 * Trusted Execution Technology.
287 { MSR1(0), "VMX inside of SMX operation disabled" },
288 { MSR1(1), "VMX inside of SMX operation enabled" },
291 /* if CPUID.01H: ECX[5 or 6] = 1 */
292 { 0, 1, "Lock bit", "R/WO", PRESENT_BIN
, {
293 /* Once the Lock bit is set, the contents
294 * of this register cannot be modified.
295 * Therefore the lock bit must be set after
296 * configuring support for Intel Virtualization
297 * Technology and prior transferring control
298 * to an Option ROM or bootloader. Hence, once
299 * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR
300 * contents are preserved across RESET when
301 * PWRGOOD it not deasserted.
303 { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" },
304 { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" },
309 {0x40, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", {
312 {0x41, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", {
315 {0x42, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", {
318 {0x43, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", {
321 {0x44, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", {
324 {0x45, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "", {
327 {0x46, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", {
330 {0x47, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "", {
333 {0x60, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", {
336 {0x61, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", {
339 {0x62, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", {
342 {0x63, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", {
345 {0x64, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "", {
348 {0x65, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "", {
351 {0x66, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "", {
354 {0x67, MSRTYPE_RDWR
, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "", {
357 {0x8b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_BIOS_SIGN_ID",
358 "BIOS Update Signature ID (RO)", {
361 {0xc1, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PMC0",
362 "Performance counter register", {
365 {0xc2, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PMC1",
366 "Performance counter register", {
369 {0xe7, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MPERF", "", {
372 {0xe8, MSRTYPE_RDWR
, MSR2(0,0), "IA32_APERF", "", {
375 {0x174, MSRTYPE_RDWR
, MSR2(0,0), "IA32_SYSENTER_CS", "", {
378 {0x175, MSRTYPE_RDWR
, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
381 {0x176, MSRTYPE_RDWR
, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
384 {0x17a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MCG_STATUS", "", {
385 { 63, 61, RESERVED
},
386 { 2, 1, "MCIP", "R/W", PRESENT_BIN
, {
387 /* When set, bit indicates that a machine check has been
388 * generated. If a second machine check is detected while
389 * this bit is still set, the processor enters a shutdown state.
390 * Software should write this bit to 0 after processing
391 * a machine check exception.
393 { MSR1(0), "Nothing" },
394 { MSR1(1), "Machine check has been generated" },
397 { 1, 1, "EPIV", "R/W", PRESENT_BIN
, {
398 /* When set, bit indicates that the instruction addressed
399 * by the instruction pointer pushed on the stack (when
400 * the machine check was generated) is directly associated
403 { MSR1(0), "Nothing" },
404 { MSR1(1), "Instruction addressed directly associated with the error" },
407 { 0, 1, "RIPV", "R/W", PRESENT_BIN
, {
408 /* When set, bit indicates that the instruction addressed
409 * by the instruction pointer pushed on the stack (when
410 * the machine check was generated) can be used to restart
411 * the program. If cleared, the program cannot be reliably restarted
413 { MSR1(0), "Program cannot be reliably restarted" },
414 { MSR1(1), "Instruction addressed can be used to restart the program" },
419 /* if CPUID.0AH: EAX[15:8] > 0 */
420 {0x186, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERFEVTSEL0",
421 "Performance Event Select Register 0", {
422 { 63, 32, RESERVED
},
423 { 31, 8, "CMASK", "R/W", PRESENT_HEX
, {
424 /* When CMASK is not zero, the corresponding performance
425 * counter 0 increments each cycle if the event count
426 * is greater than or equal to the CMASK.
430 { 23, 1, "INV", "R/W", PRESENT_BIN
, {
431 { MSR1(0), "CMASK using as is" },
432 { MSR1(1), "CMASK inerting" },
435 { 22, 1, "EN", "R/W", PRESENT_BIN
, {
436 { MSR1(0), "No commence counting" },
437 { MSR1(1), "Commence counting" },
440 { 21, 1, "AnyThread", "R/W", PRESENT_BIN
, {
443 { 20, 1, "INT", "R/W", PRESENT_BIN
, {
444 { MSR1(0), "Interrupt on counter overflow is disabled" },
445 { MSR1(1), "Interrupt on counter overflow is enabled" },
448 { 19, 1, "PC", "R/W", PRESENT_BIN
, {
449 { MSR1(0), "Disabled pin control" },
450 { MSR1(1), "Enabled pin control" },
453 { 18, 1, "Edge", "R/W", PRESENT_BIN
, {
454 { MSR1(0), "Disabled edge detection" },
455 { MSR1(1), "Enabled edge detection" },
458 { 17, 1, "OS", "R/W", PRESENT_BIN
, {
459 { MSR1(0), "Nothing" },
460 { MSR1(1), "Counts while in privilege level is ring 0" },
463 { 16, 1, "USR", "R/W", PRESENT_BIN
, {
464 { MSR1(0), "Nothing" },
465 { MSR1(1), "Counts while in privilege level is not ring 0" },
468 { 15, 8, "UMask", "R/W", PRESENT_HEX
, {
469 /* Qualifies the microarchitectural condition
470 * to detect on the selected event logic. */
473 { 7, 8, "Event Select", "R/W", PRESENT_HEX
, {
474 /* Selects a performance event logic unit. */
479 /* if CPUID.0AH: EAX[15:8] > 0 */
480 {0x187, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERFEVTSEL1",
481 "Performance Event Select Register 1", {
482 { 63, 32, RESERVED
},
483 { 31, 8, "CMASK", "R/W", PRESENT_HEX
, {
484 /* When CMASK is not zero, the corresponding performance
485 * counter 1 increments each cycle if the event count
486 * is greater than or equal to the CMASK.
490 { 23, 1, "INV", "R/W", PRESENT_BIN
, {
491 { MSR1(0), "CMASK using as is" },
492 { MSR1(1), "CMASK inerting" },
495 { 22, 1, "EN", "R/W", PRESENT_BIN
, {
496 { MSR1(0), "No commence counting" },
497 { MSR1(1), "Commence counting" },
500 { 21, 1, "AnyThread", "R/W", PRESENT_BIN
, {
503 { 20, 1, "INT", "R/W", PRESENT_BIN
, {
504 { MSR1(0), "Interrupt on counter overflow is disabled" },
505 { MSR1(1), "Interrupt on counter overflow is enabled" },
508 { 19, 1, "PC", "R/W", PRESENT_BIN
, {
509 { MSR1(0), "Disabled pin control" },
510 { MSR1(1), "Enabled pin control" },
513 { 18, 1, "Edge", "R/W", PRESENT_BIN
, {
514 { MSR1(0), "Disabled edge detection" },
515 { MSR1(1), "Enabled edge detection" },
518 { 17, 1, "OS", "R/W", PRESENT_BIN
, {
519 { MSR1(0), "Nothing" },
520 { MSR1(1), "Counts while in privilege level is ring 0" },
523 { 16, 1, "USR", "R/W", PRESENT_BIN
, {
524 { MSR1(0), "Nothing" },
525 { MSR1(1), "Counts while in privilege level is not ring 0" },
528 { 15, 8, "UMask", "R/W", PRESENT_HEX
, {
529 /* Qualifies the microarchitectural condition
530 * to detect on the selected event logic. */
533 { 7, 8, "Event Select", "R/W", PRESENT_HEX
, {
534 /* Selects a performance event logic unit. */
539 {0x199, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERF_CTL", "", {
542 {0x19a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_CLOCK_MODULATION",
543 "Clock Modulation", {
544 { 63, 59, RESERVED
},
545 { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN
, {
546 { MSR1(0), "On demand Clock Modulation is disabled" },
547 { MSR1(1), "On demand Clock Modulation is enabled" },
550 { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX
, {
556 {0x19b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_THERM_INTERRUPT",
557 "Thermal Interrupt Control", {
560 {0x19c, MSRTYPE_RDWR
, MSR2(0,0), "IA32_THERM_STATUS",
561 "Thermal Monitor Status", {
564 {0x1a0, MSRTYPE_RDWR
, MSR2(0,0), "IA32_MISC_ENABLE",
565 "Enable miscellaneous processor features", {
566 { 63, 25, RESERVED
},
567 /* Note: [38] bit using for whole package,
568 * while some other bits can be Core or Thread
571 { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN
, {
572 /* When set to a 0 on processors that support IDA,
573 * CPUID.06H: EAX[1] reports the processor's
574 * support of turbo mode is enabled.
576 { MSR1(0), "Turbo Mode enabled" },
577 /* When set 1 on processors that support Intel Turbo Boost
578 * technology, the turbo mode feature is disabled and
579 * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
581 { MSR1(1), "Turbo Mode disabled" },
583 /* Note: the power-on default value is used by BIOS to detect
584 * hardware support of turbo mode. If power-on default value is 1,
585 * turbo mode is available in the processor. If power-on default
586 * value is 0, turbo mode not available.
590 { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN
, {
593 { 33, 10, RESERVED
},
594 { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN
, {
597 { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN
, {
601 { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN
, {
604 { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN
, {
607 /* Note: [16] bit using for whole package,
608 * while some other bits can be Core or Thread
611 { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W",
616 { 12, 1, "Precise Event Based Sampling Unavailable", "R/O",
620 { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN
, {
624 { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN
, {
628 { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W"
633 { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN
, {
638 {0x1c9, MSRTYPE_RDONLY
, MSR2(0,0), "MSR_LASTBRANCH_TOS",
639 "Last Branch Record Stack TOS", {
640 /* Contains an index (bits 0-3) that points to the MSR containing
641 * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680).
645 {0x1d9, MSRTYPE_RDWR
, MSR2(0,0), "IA32_DEBUGCTL",
646 "Debug/Trace/Profile Resource Control", {
647 /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */
648 { 63, 49, RESERVED
},
649 /* Only if IA32_PERF_CAPABILITIES[12] = 1 */
650 { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN
, {
651 { MSR1(0), "Nothing" },
652 { MSR1(1), "Freeze perfmon and trace messages while in SMM" },
655 { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN
, {
656 { MSR1(0), "Nothing" },
657 { MSR1(1), "Logical processor can receive and generate PMI \
658 on behalf of the uncore" },
661 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
662 { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN
, {
663 { MSR1(0), "Nothing" },
664 { MSR1(1), "Each ENABLE bit of the global counter control MSR \
665 are frozen (address 0x3bf) on PMI request" },
668 /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */
669 { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN
, {
670 { MSR1(0), "Nothing" },
671 { MSR1(1), "LBR stack is frozen on PMI request" },
674 { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN
, {
675 { MSR1(0), "Nothing" },
676 { MSR1(1), "BTS or BTM is skipped if CPL > 0" },
679 { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN
, {
680 { MSR1(0), "Nothing" },
681 { MSR1(1), "BTS or BTM is skipped if CPL = 0" },
684 { 8, 1, "BTINT", "R/O", PRESENT_BIN
, {
685 { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" },
686 { MSR1(1), "An interrupt is generated by the BTS facility \
687 when the BTS buffer is full" },
690 { 7, 1, "BTS", "R/O", PRESENT_BIN
, {
691 { MSR1(0), "Logging of BTMs (branch trace messages) \
692 in BTS buffer is disabled" },
693 { MSR1(1), "Logging of BTMs (branch trace messages) \
694 in BTS buffer is enabled" },
697 { 6, 1, "TR", "R/O", PRESENT_BIN
, {
698 { MSR1(0), "Branch trace messages are disabled" },
699 { MSR1(1), "Branch trace messages are enabled" },
703 { 1, 1, "BTF", "R/O", PRESENT_BIN
, {
704 { MSR1(0), "Nothing" },
705 { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \
706 branches instead of single-step on instructions" },
709 { 0, 1, "LBR", "R/O", PRESENT_BIN
, {
710 { MSR1(0), "Nothing" },
711 { MSR1(1), "Enabled recording a running trace of the most \
712 recent branches taken by the processor in the LBR stack" },
717 {0x1dd, MSRTYPE_RDONLY
, MSR2(0,0), "MSR_LER_FROM_LIP",
718 "Last Exception Record From Linear IP", {
719 /* Contains a pointer to the last branch instruction
720 * that the processor executed prior to the last exception
721 * that was generated or the last interrupt that was handled.
725 {0x1de, MSRTYPE_RDONLY
, MSR2(0,0), "MSR_LER_TO_LIP",
726 "Last Exception Record To Linear IP", {
727 /* This area contains a pointer to the target of the
728 * last branch instruction that the processor executed
729 * prior to the last exception that was generated or
730 * the last interrupt that was handled
734 {0x277, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PAT", "IA32_PAT", {
736 { 58, 3, "PA7", "R/W", PRESENT_BIN
, {
740 { 40, 3, "PA6", "R/W", PRESENT_BIN
, {
744 { 42, 3, "PA5", "R/W", PRESENT_BIN
, {
748 { 34, 3, "PA4", "R/W", PRESENT_BIN
, {
752 { 26, 3, "PA3", "R/W", PRESENT_BIN
, {
756 { 18, 3, "PA2", "R/W", PRESENT_BIN
, {
760 { 10, 3, "PA1", "R/W", PRESENT_BIN
, {
764 { 2, 3, "PA0", "R/W", PRESENT_BIN
, {
769 /* if CPUID.0AH: EDX[4:0] > 0 */
770 {0x309, MSRTYPE_RDWR
, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \
771 Performance Counter Register 0: Counts Instr_Retired.Any", {
772 /* Also known as MSR_PERF_FIXED_CTR0 */
775 /* if CPUID.0AH: EDX[4:0] > 1 */
776 {0x30a, MSRTYPE_RDWR
, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \
777 Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", {
778 /* Also known as MSR_PERF_FIXED_CTR1 */
781 /* if CPUID.0AH: EDX[4:0] > 2 */
782 {0x30b, MSRTYPE_RDWR
, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \
783 Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", {
784 /* Also known as MSR_PERF_FIXED_CTR2 */
787 /* if CPUID.0AH: EAX[7:0] > 1*/
788 {0x38d, MSRTYPE_RDWR
, MSR2(0,0), "IA32_FIXED_CTR_CTRL",
789 "Fixed-Function-Counter Control Register", {
790 /* Also known as MSR_PERF_FIXED_CTR_CTRL.
791 * Counter increments while the results of ANDing respective enable bit
792 * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits
793 * in this MSR is true. */
794 { 63, 52, RESERVED
},
795 { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN
, {
796 { MSR1(0), "Nothing" },
797 { MSR1(1), "PMI when fixed counter 2 overflows is enabled" },
800 /* if CPUID.0AH EAX[7:0] > 2 */
801 { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN
, {
802 { MSR1(0), "Counter only increments the associated event \
803 conditions occuring in the logical processor which programmed the MSR" },
804 { MSR1(1), "Counting the associated event conditions \
805 occuring across all logical processors sharing a processor core" },
808 { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN
, {
809 { MSR1(0), "Nothing" },
810 { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" },
813 { 8, 1, "EN2_OS", "R/W", PRESENT_BIN
, {
814 { MSR1(0), "Nothing" },
815 { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" },
818 { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN
, {
819 { MSR1(0), "Nothing" },
820 { MSR1(1), "PMI when fixed counter 1 overflows is enabled" },
823 /* if CPUID.0AH: EAX[7:0] > 2 */
824 { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN
, {
825 { MSR1(0), "Counter only increments the associated event \
826 conditions occuring in the logical processor which programmed the MSR" },
827 { MSR1(1), "Counting the associated event conditions \
828 occuring across all logical processors sharing a processor core" },
831 { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN
, {
832 { MSR1(0), "Nothing" },
833 { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" },
836 { 4, 1, "EN1_OS", "R/W", PRESENT_BIN
, {
837 { MSR1(0), "Nothing" },
838 { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" },
841 { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN
, {
842 { MSR1(0), "Nothing" },
843 { MSR1(1), "PMI when fixed counter 0 overflows is enabled" },
846 /* if CPUID.0AH: EAX[7:0] > 2 */
847 { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN
, {
848 { MSR1(0), "Counter only increments the associated event \
849 conditions occuring in the logical processor which programmed the MSR" },
850 { MSR1(1), "Counting the associated event conditions \
851 occuring across all logical processors sharing a processor core" },
854 { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN
, {
855 { MSR1(0), "Nothing" },
856 { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" },
859 { 0, 1, "EN0_OS", "R/W", PRESENT_BIN
, {
860 { MSR1(0), "Nothing" },
861 { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" },
866 /* if CPUID.0AH: EAX[7:0] > 0 */
867 {0x38e, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS",
868 "Global Performance Counter Status", {
869 /* Also known as MSR_PERF_GLOBAL_STATUS */
870 /* if CPUID.0AH: EAX[7:0] > 0 */
871 { 63, 1, "CondChg: Status bits of this register has changed",
872 "R/O", PRESENT_BIN
, {
875 /* if CPUID.0AH: EAX[7:0] > 0 */
876 { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status",
877 "R/O", PRESENT_BIN
, {
880 /* if CPUID.0AH: EAX[7:0] > 2 */
881 { 61, 1, "Ovf_Uncore: Uncore counter overflow status",
882 "R/O", PRESENT_BIN
, {
885 { 60, 26, RESERVED
},
886 /* if CPUID.0AH: EAX[7:0] > 1 */
887 { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2",
888 "R/O", PRESENT_BIN
, {
891 /* if CPUID.0AH: EAX[7:0] > 1 */
892 { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1",
893 "R/O", PRESENT_BIN
, {
896 /* if CPUID.0AH: EAX[7:0] > 1 */
897 { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0",
898 "R/O", PRESENT_BIN
, {
901 { 31, 28, RESERVED
},
902 /* presented only in 06_2EH Nehalem model */
903 { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN
, {
906 /* presented only in 06_2EH Nehalem model */
907 { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN
, {
910 /* if CPUID.0AH: EAX[7:0] > 0 */
911 { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN
, {
914 /* if CPUID.0AH: EAX[7:0] > 0 */
915 { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN
, {
920 /* if CPUID.0AH: EAX[7:0] > 0 */
921 {0x38f, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERF_GLOBAL_CTL",
922 "Global Performance Counter Control", {
923 /* Counter increments while the result of ANDing respective
924 * enable bit in this MSR with corresponding OS or USR bits
925 * in general-purpose or fixed counter control MSR is true.
927 { 63, 29, RESERVED
},
928 /* if CPUID.0AH: EAX[7:0] > 1 */
929 { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN
, {
932 /* if CPUID.0AH: EAX[7:0] > 1 */
933 { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN
, {
936 /* if CPUID.0AH: EAX[7:0] > 1 */
937 { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN
, {
940 { 31, 30, RESERVED
},
941 /* if CPUID.0AH: EAX[7:0] > 0 */
942 { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN
, {
945 /* if CPUID.0AH: EAX[7:0] > 0 */
946 { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN
, {
951 /* if CPUID.0AH: EAX[7:0] > 0 */
952 {0x390, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL",
953 "Global Performance Counter Overflow Control", {
954 /* if CPUID.0AH: EAX[7:0] > 0 */
955 { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN
, {
958 /* if CPUID.0AH: EAX[7:0] > 0 */
959 { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN
, {
962 /* Presented only in 06_2EH Nehalem model */
963 { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN
, {
966 { 60, 26, RESERVED
},
967 /* if CPUID.0AH: EAX[7:0] > 1 */
968 { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN
, {
971 /* if CPUID.0AH: EAX[7:0] > 1 */
972 { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN
, {
975 /* if CPUID.0AH: EAX[7:0] > 1 */
976 { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN
, {
979 { 31, 30, RESERVED
},
980 /* if CPUID.0AH: EAX[7:0] > 0 */
981 { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN
, {
984 /* if CPUID.0AH: EAX[7:0] > 0 */
985 { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN
, {
990 /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures
991 * Software Developer's Manual, Volume 3,
992 * "Precise Event Based Sampling (PEBS)".
994 {0x3f1, MSRTYPE_RDWR
, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", {
995 { 63, 28, RESERVED
},
996 { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN
, {
997 { MSR1(0), "Disabled" },
998 { MSR1(1), "Enabled" },
1001 { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN
, {
1002 { MSR1(0), "Disabled" },
1003 { MSR1(1), "Enabled" },
1006 { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN
, {
1007 { MSR1(0), "Disabled" },
1008 { MSR1(1), "Enabled" },
1011 { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN
, {
1012 { MSR1(0), "Disabled" },
1013 { MSR1(1), "Enabled" },
1016 { 31, 28, RESERVED
},
1017 { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN
, {
1018 { MSR1(0), "Disabled" },
1019 { MSR1(1), "Enabled" },
1022 { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN
, {
1023 { MSR1(0), "Disabled" },
1024 { MSR1(1), "Enabled" },
1027 { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN
, {
1028 { MSR1(0), "Disabled" },
1029 { MSR1(1), "Enabled" },
1032 { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN
, {
1033 { MSR1(0), "Disabled" },
1034 { MSR1(1), "Enabled" },
1040 {0x480, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_BASIC",
1041 "Reporting Register of Basic VMX Capabilities", {
1042 /* Additional info available at
1043 * Appendix A.1, "Basic VMX Information" */
1044 { 63, 10, RESERVED
},
1045 { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX
, {
1048 { 49, 1, "Support of dual-treatment of system-management functions",
1049 "R/O", PRESENT_BIN
, {
1052 { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN
, {
1055 { 47, 3, RESERVED
},
1056 { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC
, {
1059 { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX
, {
1064 {0x481, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_PINBASED_CTLS",
1065 "Capability Reporting Register of \
1066 Pin-based VM-execution Controls", {
1067 /* Additional info available at Appendix A.3,
1068 * "VM-Execution Controls" */
1071 {0x482, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_PROCBASED_CTLS",
1072 "Capability Reporting Register of \
1073 Primary Processor-based VM-execution Controls", {
1074 /* Additional info available at Appendix A.3,
1075 * "VM-Execution Controls" */
1078 {0x483, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_EXIT_CTLS",
1079 "Capability Reporting Register of VM-exit Controls", {
1080 /* Additional info available at Appendix A.4,
1081 * "VM-Exit Controls" */
1084 {0x484, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_ENTRY_CTLS",
1085 "Capability Reporting Register of VM-entry Controls", {
1086 /* Additional info available at Appendix A.5,
1087 * "VM-Entry Controls" */
1090 {0x485, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_MISC",
1091 "Reporting Register of Miscellaneous VMX Capabilities", {
1092 /* Additional info available at Appendix A.6,
1093 * "Miscellaneous Data" */
1096 {0x486, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_CR0_FIXED0",
1097 "Capability Reporting Register of CR0 Bits Fixed to 0", {
1098 /* Additional info available at Appendix A.7,
1099 * "VMX-Fixed Bits in CR0" */
1102 {0x487, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_CR0_FIXED1",
1103 "Capability Reporting Register of CR0 Bits Fixed to 1", {
1104 /* Additional info available at Appendix A.7,
1105 * "VMX-Fixed Bits in CR0" */
1108 {0x488, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_CR4_FIXED0",
1109 "Capability Reporting Register of CR4 Bits Fixed to 0", {
1110 /* Additional info available at Appendix A.8,
1111 * "VMX-Fixed Bits in CR4" */
1114 {0x489, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_CR4_FIXED1",
1115 "Capability Reporting Register of CR4 Bits Fixed to 1", {
1116 /* Additional info available at Appendix A.8,
1117 * "VMX-Fixed Bits in CR4" */
1120 {0x48a, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_VMCS_ENUM",
1121 "Capability Reporting Register of VMCS Field Enumeration", {
1122 /* Additional info available at Appendix A.9,
1123 * "VMCS Enumeration" */
1126 {0x48b, MSRTYPE_RDONLY
, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2",
1127 "Capability Reporting Register of Secondary \
1128 Processor-based VM-execution Controls", {
1129 /* Additional info available at Appendix A.3,
1130 * "VM-Execution Controls" */
1134 {0x600, MSRTYPE_RDWR
, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", {
1135 /* Additional info available at Section 18.10.4 of Intel 64
1136 * and IA-32 Architectures Software Developer's Manual,
1137 * "Debug Store (DS) Mechanism".
1139 { 63, 32, RESERVED
}, // reserved if not in IA-32e mode
1140 { 31, 32, "Linear address of DS buffer management area",
1141 "R/W", PRESENT_HEX
, {