mainboards: Drop PWRS from GNVS
[coreboot.git] / src / southbridge / intel / i82801jx / include / soc / nvs.h
blob96c55882e8890cd3d939ae39ae58ee40c9a810b9
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef SOUTHBRIDGE_INTEL_I82801JX_NVS_H
4 #define SOUTHBRIDGE_INTEL_I82801JX_NVS_H
5 #include <stdint.h>
7 struct __packed global_nvs {
8 /* Miscellaneous */
9 u16 osys; /* 0x00 - Operating System */
10 u8 smif; /* 0x02 - SMI function call ("TRAP") */
11 u8 prm0; /* 0x03 - SMI function call parameter */
12 u8 prm1; /* 0x04 - SMI function call parameter */
13 u8 scif; /* 0x05 - SCI function call (via _L00) */
14 u8 prm2; /* 0x06 - SCI function call parameter */
15 u8 prm3; /* 0x07 - SCI function call parameter */
16 u8 lckf; /* 0x08 - Global Lock function for EC */
17 u8 prm4; /* 0x09 - Lock function parameter */
18 u8 prm5; /* 0x0a - Lock function parameter */
19 u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
20 u8 lids; /* 0x0f - LID state (open = 1) */
21 u8 unused_was_pwrs; /* 0x10 - Power state (AC = 1) */
22 u8 dbgs; /* 0x11 - Debug state */
23 u8 linx; /* 0x12 - Linux OS */
24 u8 dckn; /* 0x13 - PCIe docking state */
25 /* Thermal policy */
26 u8 actt; /* 0x14 - active trip point */
27 u8 tpsv; /* 0x15 - passive trip point */
28 u8 tc1v; /* 0x16 - passive trip point TC1 */
29 u8 tc2v; /* 0x17 - passive trip point TC2 */
30 u8 tspv; /* 0x18 - passive trip point TSP */
31 u8 tcrt; /* 0x19 - critical trip point */
32 u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
33 u8 dts1; /* 0x1b - DT sensor 1 */
34 u8 flvl; /* 0x1c - current fan level */
35 u8 rsvd2;
36 /* Battery Support */
37 u8 bnum; /* 0x1e - number of batteries */
38 u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
39 u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
40 u8 rsvd3[3];
41 /* Processor Identification */
42 u8 unused_was_apic; /* 0x28 - APIC enabled */
43 u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
44 u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
45 u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
46 u8 ppcm; /* 0x2c - Max. PPC state */
47 u8 rsvd4[5];
48 /* Super I/O & CMOS config */
49 u8 natp; /* 0x32 - SIO type */
50 u8 cmap; /* 0x33 - */
51 u8 cmbp; /* 0x34 - */
52 u8 lptp; /* 0x35 - LPT port */
53 u8 fdcp; /* 0x36 - Floppy Disk Controller */
54 u8 rfdv; /* 0x37 - */
55 u8 hotk; /* 0x38 - Hot Key */
56 u8 rtcf;
57 u8 util;
58 u8 acin;
59 /* Integrated Graphics Device */
60 u8 igds; /* 0x3c - IGD state */
61 u8 tlst; /* 0x3d - Display Toggle List Pointer */
62 u8 cadl; /* 0x3e - currently attached devices */
63 u8 padl; /* 0x3f - previously attached devices */
64 u8 rsvd5[36];
65 /* Backlight Control */
66 u8 blcs; /* 0x64 - Backlight Control possible */
67 u8 brtl;
68 u8 odds;
69 u8 rsvd6[0x7];
70 /* Ambient Light Sensors*/
71 u8 alse; /* 0x6e - ALS enable */
72 u8 alaf;
73 u8 llow;
74 u8 lhih;
75 u8 rsvd7[0x6];
76 /* EMA */
77 u8 emae; /* 0x78 - EMA enable */
78 u16 emap;
79 u16 emal;
80 u8 rsvd8[0x5];
81 /* MEF */
82 u8 mefe; /* 0x82 - MEF enable */
83 u8 rsvd9[0x9];
84 /* TPM support */
85 u8 tpmp; /* 0x8c - TPM */
86 u8 tpme;
87 u8 rsvd10[8];
88 /* SATA */
89 u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
90 u8 gtf1[7];
91 u8 gtf2[7];
92 u8 idem;
93 u8 idet;
94 u8 rsvd11[67];
95 /* Mainboard specific */
96 u8 dock; /* 0xf0 - Docking Status */
97 u8 bten;
99 u32 cbmc;
101 /* Required for future unified acpi_save_wake_source. */
102 u32 pm1i;
103 u32 gpei;
106 #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */