util/autoport/sandybridge.go

   1 package main
   2
   3 type sandybridgemc struct {
   4 }
   5
   6 func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
   7         inteltool := ctx.InfoSource.GetInteltool()
   8
   9         /* FIXME:XX Move this somewhere else.  */
  10         MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
  11         MainboardEnable += (`   /* FIXME: fix these values. */
  12         install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
  13                                         GMA_INT15_PANEL_FIT_DEFAULT,
  14                                         GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
  15 `)
  16
  17         pchLVDS := inteltool.IGD[0xe1180]
  18         dualChannel := pchLVDS&(3<<2) == (3 << 2)
  19         pipe := (pchLVDS >> 30) & 1
  20         link_m1 := inteltool.IGD[0x60040+0x1000*pipe]
  21         link_n1 := inteltool.IGD[0x60044+0x1000*pipe]
  22         link_factor := float32(link_m1) / float32(link_n1)
  23         fp0 := inteltool.IGD[0xc6040+8*pipe]
  24         dpll := inteltool.IGD[0xc6014+4*pipe]
  25         pixel_m2 := fp0 & 0xff
  26         pixel_m1 := (fp0>>8)&0xff + 2
  27         pixel_p1 := uint32(1)
  28         for i := dpll & 0x1ffff; i != 0 && i&1 == 0; i >>= 1 {
  29                 pixel_p1++
  30         }
  31         pixel_n := ((fp0 >> 16) & 0xff) + 2
  32         pixel_frequency := float32(120000*(5*pixel_m1+pixel_m2)) / float32(pixel_n*pixel_p1*7.0)
  33         if !dualChannel {
  34                 pixel_frequency /= 2
  35         }
  36         link_frequency := pixel_frequency / link_factor
  37         DevTree = DevTreeNode{
  38                 Chip:          "northbridge/intel/sandybridge",
  39                 MissingParent: "northbridge",
  40                 Comment:       "FIXME: GPU registers may not always apply.",
  41                 Registers: map[string]string{
  42                         "gpu_dp_b_hotplug":                    FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
  43                         "gpu_dp_c_hotplug":                    FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
  44                         "gpu_dp_d_hotplug":                    FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
  45                         "gpu_panel_port_select":               FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
  46                         "gpu_panel_power_up_delay":            FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
  47                         "gpu_panel_power_backlight_on_delay":  FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
  48                         "gpu_panel_power_down_delay":          FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
  49                         "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
  50                         "gpu_panel_power_cycle_delay":         FormatInt32(inteltool.IGD[0xc7210] & 0xff),
  51                         "gpu_cpu_backlight":                   FormatHex32(inteltool.IGD[0x48254]),
  52                         "gpu_pch_backlight":                   FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
  53                         "gfx.use_spread_spectrum_clock":       FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
  54                         "gfx.link_frequency_270_mhz":          FormatBool(link_frequency > 200000),
  55                 },
  56                 Children: []DevTreeNode{
  57                         {
  58                                 Chip: "cpu_cluster",
  59                                 Dev:  0,
  60                                 Children: []DevTreeNode{
  61                                         {
  62                                                 Chip:    "cpu/intel/model_206ax",
  63                                                 Comment: "FIXME: check all registers",
  64                                                 Registers: map[string]string{
  65                                                         /* FIXME:XX hardcoded.  */
  66                                                         "c1_acpower": "1",
  67                                                         "c2_acpower": "3",
  68                                                         "c3_acpower": "5",
  69                                                         "c1_battery": "1",
  70                                                         "c2_battery": "3",
  71                                                         "c3_battery": "5",
  72                                                 },
  73                                                 Children: []DevTreeNode{
  74                                                         {
  75                                                                 Chip: "lapic",
  76                                                                 Dev:  0,
  77                                                         },
  78                                                         {
  79                                                                 Chip:     "lapic",
  80                                                                 Dev:      0xacac,
  81                                                                 Disabled: true,
  82                                                         },
  83                                                 },
  84                                         },
  85                                 },
  86                         },
  87
  88                         {
  89                                 Chip:          "domain",
  90                                 Dev:           0,
  91                                 PCIController: true,
  92                                 ChildPCIBus:   0,
  93                                 PCISlots: []PCISlot{
  94                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
  95                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"},
  96                                         PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"},
  97                                 },
  98                         },
  99                 },
 100         }
 101
 102         PutPCIDev(addr, "Host bridge")
 103
 104         /* FIXME:XX some configs are unsupported.  */
 105         KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true
 106         KconfigBool["USE_NATIVE_RAMINIT"] = true
 107         KconfigBool["INTEL_INT15"] = true
 108         KconfigBool["HAVE_ACPI_TABLES"] = true
 109         KconfigBool["HAVE_ACPI_RESUME"] = true
 110
 111         KconfigInt["MAX_CPUS"] = 8
 112
 113         DSDTIncludes = append(DSDTIncludes, DSDTInclude{
 114                 File: "cpu/intel/common/acpi/cpu.asl",
 115         })
 116
 117         DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
 118                 File: "northbridge/intel/sandybridge/acpi/sandybridge.asl",
 119         }, DSDTInclude{
 120                 File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
 121         })
 122 }
 123
 124 func init() {
 125         RegisterPCI(0x8086, 0x0100, sandybridgemc{})
 126         RegisterPCI(0x8086, 0x0104, sandybridgemc{})
 127         RegisterPCI(0x8086, 0x0150, sandybridgemc{})
 128         RegisterPCI(0x8086, 0x0154, sandybridgemc{})
 129         RegisterPCI(0x8086, 0x0158, sandybridgemc{})
 130         for _, id := range []uint16{
 131                 0x0102, 0x0106, 0x010a,
 132                 0x0112, 0x0116, 0x0122, 0x0126,
 133                 0x0152, 0x0156, 0x0162, 0x0166,
 134         } {
 135                 RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}})
 136         }
 137
 138         /* PCIe bridge */
 139         for _, id := range []uint16{
 140                 0x0101, 0x0105, 0x0109, 0x010d,
 141                 0x0151, 0x0155, 0x0159, 0x015d,
 142         } {
 143                 RegisterPCI(0x8086, id, GenericPCI{})
 144         }
 145 }