src/soc/intel/cannonlake/cpu.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2017-2018 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/cpu.h>
  17 #include <console/console.h>
  18 #include <device/pci.h>
  19 #include <cpu/x86/lapic.h>
  20 #include <cpu/x86/mp.h>
  21 #include <cpu/x86/msr.h>
  22 #include <cpu/intel/smm_reloc.h>
  23 #include <cpu/intel/turbo.h>
  24 #include <intelblocks/cpulib.h>
  25 #include <intelblocks/mp_init.h>
  26 #include <romstage_handoff.h>
  27 #include <soc/cpu.h>
  28 #include <soc/msr.h>
  29 #include <soc/pci_devs.h>
  30 #include <soc/pm.h>
  31 #include <soc/smm.h>
  32 #include <soc/systemagent.h>
  33 #include <cpu/x86/mtrr.h>
  34 #include <cpu/intel/microcode.h>
  35 #include <cpu/intel/common/common.h>
  36
  37 #include "chip.h"
  38
  39 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
  40 static const u8 power_limit_time_sec_to_msr[] = {
  41         [0]   = 0x00,
  42         [1]   = 0x0a,
  43         [2]   = 0x0b,
  44         [3]   = 0x4b,
  45         [4]   = 0x0c,
  46         [5]   = 0x2c,
  47         [6]   = 0x4c,
  48         [7]   = 0x6c,
  49         [8]   = 0x0d,
  50         [10]  = 0x2d,
  51         [12]  = 0x4d,
  52         [14]  = 0x6d,
  53         [16]  = 0x0e,
  54         [20]  = 0x2e,
  55         [24]  = 0x4e,
  56         [28]  = 0x6e,
  57         [32]  = 0x0f,
  58         [40]  = 0x2f,
  59         [48]  = 0x4f,
  60         [56]  = 0x6f,
  61         [64]  = 0x10,
  62         [80]  = 0x30,
  63         [96]  = 0x50,
  64         [112] = 0x70,
  65         [128] = 0x11,
  66 };
  67
  68 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
  69 static const u8 power_limit_time_msr_to_sec[] = {
  70         [0x00] = 0,
  71         [0x0a] = 1,
  72         [0x0b] = 2,
  73         [0x4b] = 3,
  74         [0x0c] = 4,
  75         [0x2c] = 5,
  76         [0x4c] = 6,
  77         [0x6c] = 7,
  78         [0x0d] = 8,
  79         [0x2d] = 10,
  80         [0x4d] = 12,
  81         [0x6d] = 14,
  82         [0x0e] = 16,
  83         [0x2e] = 20,
  84         [0x4e] = 24,
  85         [0x6e] = 28,
  86         [0x0f] = 32,
  87         [0x2f] = 40,
  88         [0x4f] = 48,
  89         [0x6f] = 56,
  90         [0x10] = 64,
  91         [0x30] = 80,
  92         [0x50] = 96,
  93         [0x70] = 112,
  94         [0x11] = 128,
  95 };
  96
  97 /*
  98  * Configure processor power limits if possible
  99  * This must be done AFTER set of BIOS_RESET_CPL
 100  */
 101 void set_power_limits(u8 power_limit_1_time)
 102 {
 103         msr_t msr = rdmsr(MSR_PLATFORM_INFO);
 104         msr_t limit;
 105         unsigned int power_unit;
 106         unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
 107         u8 power_limit_1_val;
 108
 109         config_t *conf = config_of_soc();
 110
 111         if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
 112                 power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1;
 113
 114         if (!(msr.lo & PLATFORM_INFO_SET_TDP))
 115                 return;
 116
 117         /* Get units */
 118         msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 119         power_unit = 1 << (msr.lo & 0xf);
 120
 121         /* Get power defaults for this SKU */
 122         msr = rdmsr(MSR_PKG_POWER_SKU);
 123         tdp = msr.lo & 0x7fff;
 124         min_power = (msr.lo >> 16) & 0x7fff;
 125         max_power = msr.hi & 0x7fff;
 126         max_time = (msr.hi >> 16) & 0x7f;
 127
 128         printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
 129
 130         if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
 131                 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
 132
 133         if (min_power > 0 && tdp < min_power)
 134                 tdp = min_power;
 135
 136         if (max_power > 0 && tdp > max_power)
 137                 tdp = max_power;
 138
 139         power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
 140
 141         /* Set long term power limit to TDP */
 142         limit.lo = 0;
 143         tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
 144                 tdp : (conf->tdp_pl1_override * power_unit));
 145         limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
 146
 147         /* Set PL1 Pkg Power clamp bit */
 148         limit.lo |= PKG_POWER_LIMIT_CLAMP;
 149
 150         limit.lo |= PKG_POWER_LIMIT_EN;
 151         limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
 152                 PKG_POWER_LIMIT_TIME_SHIFT;
 153
 154         /* Set short term power limit to 1.25 * TDP if no config given */
 155         limit.hi = 0;
 156         tdp_pl2 = (conf->tdp_pl2_override == 0) ?
 157                 (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit);
 158         printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", tdp_pl2 / power_unit);
 159         limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK;
 160         limit.hi |= PKG_POWER_LIMIT_CLAMP;
 161         limit.hi |= PKG_POWER_LIMIT_EN;
 162
 163         /* Power limit 2 time is only programmable on server SKU */
 164         wrmsr(MSR_PKG_POWER_LIMIT, limit);
 165
 166         /* Set PL2 power limit values in MCHBAR and disable PL1 */
 167         MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN));
 168         MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi;
 169
 170         /* Set PsysPl2 */
 171         if (conf->tdp_psyspl2) {
 172                 limit = rdmsr(MSR_PLATFORM_POWER_LIMIT);
 173                 limit.hi = 0;
 174                 printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n",
 175                         conf->tdp_psyspl2);
 176                 limit.hi |= (conf->tdp_psyspl2 * power_unit) &
 177                         PKG_POWER_LIMIT_MASK;
 178                 limit.hi |= PKG_POWER_LIMIT_CLAMP;
 179                 limit.hi |= PKG_POWER_LIMIT_EN;
 180
 181                 wrmsr(MSR_PLATFORM_POWER_LIMIT, limit);
 182         }
 183
 184         /* Set PsysPl3 */
 185         if (conf->tdp_psyspl3) {
 186                 limit = rdmsr(MSR_PL3_CONTROL);
 187                 limit.lo = 0;
 188                 printk(BIOS_DEBUG, "CPU PsysPL3 = %u Watts\n",
 189                        conf->tdp_psyspl3);
 190                 limit.lo |= (conf->tdp_psyspl3 * power_unit) &
 191                         PKG_POWER_LIMIT_MASK;
 192                 /* Enable PsysPl3 */
 193                 limit.lo |= PKG_POWER_LIMIT_EN;
 194                 /* set PsysPl3 time window */
 195                 limit.lo |= (conf->tdp_psyspl3_time &
 196                              PKG_POWER_LIMIT_TIME_MASK) <<
 197                         PKG_POWER_LIMIT_TIME_SHIFT;
 198                 /* set PsysPl3  duty cycle */
 199                 limit.lo |= (conf->tdp_psyspl3_dutycycle &
 200                              PKG_POWER_LIMIT_DUTYCYCLE_MASK) <<
 201                         PKG_POWER_LIMIT_DUTYCYCLE_SHIFT;
 202                 wrmsr(MSR_PL3_CONTROL, limit);
 203         }
 204
 205         /* Set Pl4 */
 206         if (conf->tdp_pl4) {
 207                 limit = rdmsr(MSR_VR_CURRENT_CONFIG);
 208                 limit.lo = 0;
 209                 printk(BIOS_DEBUG, "CPU PL4 = %u Watts\n",
 210                        conf->tdp_pl4);
 211                 limit.lo |= (conf->tdp_pl4 * power_unit) &
 212                         PKG_POWER_LIMIT_MASK;
 213                 wrmsr(MSR_VR_CURRENT_CONFIG, limit);
 214         }
 215
 216         /* Set DDR RAPL power limit by copying from MMIO to MSR */
 217         msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO);
 218         msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI);
 219         wrmsr(MSR_DDR_RAPL_LIMIT, msr);
 220
 221         /* Use nominal TDP values for CPUs with configurable TDP */
 222         if (cpu_config_tdp_levels()) {
 223                 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
 224                 limit.hi = 0;
 225                 limit.lo = cpu_get_tdp_nominal_ratio();
 226                 wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
 227         }
 228 }
 229
 230 static void soc_fsp_load(void)
 231 {
 232         fsps_load(romstage_handoff_is_resume());
 233 }
 234
 235 static void configure_isst(void)
 236 {
 237         config_t *conf = config_of_soc();
 238         msr_t msr;
 239
 240         if (conf->speed_shift_enable) {
 241                 /*
 242                  * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
 243                  * is supported or not. coreboot needs to configure MSR 0x1AA
 244                  * which is then reflected in the CPUID register.
 245                  */
 246                 msr = rdmsr(MSR_MISC_PWR_MGMT);
 247                 msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
 248                 msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
 249                 msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
 250                 wrmsr(MSR_MISC_PWR_MGMT, msr);
 251         } else {
 252                 msr = rdmsr(MSR_MISC_PWR_MGMT);
 253                 msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
 254                 msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
 255                 msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
 256                 wrmsr(MSR_MISC_PWR_MGMT, msr);
 257         }
 258 }
 259
 260 static void configure_misc(void)
 261 {
 262         config_t *conf = config_of_soc();
 263         msr_t msr;
 264
 265         msr = rdmsr(IA32_MISC_ENABLE);
 266         msr.lo |= (1 << 0);     /* Fast String enable */
 267         msr.lo |= (1 << 3);     /* TM1/TM2/EMTTM enable */
 268         /* Set EIST status */
 269         cpu_set_eist(conf->eist_enable);
 270         wrmsr(IA32_MISC_ENABLE, msr);
 271
 272         /* Disable Thermal interrupts */
 273         msr.lo = 0;
 274         msr.hi = 0;
 275         wrmsr(IA32_THERM_INTERRUPT, msr);
 276
 277         /* Enable package critical interrupt only */
 278         msr.lo = 1 << 4;
 279         msr.hi = 0;
 280         wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
 281
 282         /* Enable PROCHOT */
 283         msr = rdmsr(MSR_POWER_CTL);
 284         msr.lo |= (1 << 0);     /* Enable Bi-directional PROCHOT as an input*/
 285         msr.lo |= (1 << 23);    /* Lock it */
 286         wrmsr(MSR_POWER_CTL, msr);
 287 }
 288
 289 static void enable_lapic_tpr(void)
 290 {
 291         msr_t msr;
 292
 293         msr = rdmsr(MSR_PIC_MSG_CONTROL);
 294         msr.lo &= ~(1 << 10);   /* Enable APIC TPR updates */
 295         wrmsr(MSR_PIC_MSG_CONTROL, msr);
 296 }
 297
 298 static void configure_dca_cap(void)
 299 {
 300         uint32_t feature_flag;
 301         msr_t msr;
 302
 303         /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
 304         feature_flag = cpu_get_feature_flags_ecx();
 305         if (feature_flag & CPUID_DCA) {
 306                 msr = rdmsr(IA32_PLATFORM_DCA_CAP);
 307                 msr.lo |= 1;
 308                 wrmsr(IA32_PLATFORM_DCA_CAP, msr);
 309         }
 310 }
 311
 312 static void set_energy_perf_bias(u8 policy)
 313 {
 314         msr_t msr;
 315         int ecx;
 316
 317         /* Determine if energy efficient policy is supported. */
 318         ecx = cpuid_ecx(0x6);
 319         if (!(ecx & (1 << 3)))
 320                 return;
 321
 322         /* Energy Policy is bits 3:0 */
 323         msr = rdmsr(IA32_ENERGY_PERF_BIAS);
 324         msr.lo &= ~0xf;
 325         msr.lo |= policy & 0xf;
 326         wrmsr(IA32_ENERGY_PERF_BIAS, msr);
 327 }
 328
 329 static void configure_c_states(void)
 330 {
 331         msr_t msr;
 332
 333         /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
 334         msr.hi = 0;
 335         msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
 336         wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
 337
 338         /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
 339         msr.hi = 0;
 340         msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
 341         wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 342
 343         /* C-state Interrupt Response Latency Control 3 - package C8 */
 344         msr.hi = 0;
 345         msr.lo = IRTL_VALID | IRTL_32768_NS |
 346                 C_STATE_LATENCY_CONTROL_3_LIMIT;
 347         wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 348
 349         /* C-state Interrupt Response Latency Control 4 - package C9 */
 350         msr.hi = 0;
 351         msr.lo = IRTL_VALID | IRTL_32768_NS |
 352                 C_STATE_LATENCY_CONTROL_4_LIMIT;
 353         wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 354
 355         /* C-state Interrupt Response Latency Control 5 - package C10 */
 356         msr.hi = 0;
 357         msr.lo = IRTL_VALID | IRTL_32768_NS |
 358                 C_STATE_LATENCY_CONTROL_5_LIMIT;
 359         wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 360 }
 361
 362 static void configure_thermal_target(void)
 363 {
 364         config_t *conf = config_of_soc();
 365         msr_t msr;
 366
 367         /* Set TCC activation offset if supported */
 368         msr = rdmsr(MSR_PLATFORM_INFO);
 369         if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
 370                 msr = rdmsr(MSR_TEMPERATURE_TARGET);
 371                 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
 372                 msr.lo |= (conf->tcc_offset & 0xf) << 24;
 373                 wrmsr(MSR_TEMPERATURE_TARGET, msr);
 374         }
 375         msr = rdmsr(MSR_TEMPERATURE_TARGET);
 376         msr.lo &= ~0x7f; /* Bits 6:0 */
 377         msr.lo |= 0xe6; /* setting 100ms thermal time window */
 378         wrmsr(MSR_TEMPERATURE_TARGET, msr);
 379 }
 380
 381 /*
 382  * The emulated ACPI timer allows replacing of the ACPI timer
 383  * (PM1_TMR) to have no impart on the system.
 384  */
 385 static void enable_pm_timer_emulation(void)
 386 {
 387         const struct soc_intel_cannonlake_config *config;
 388         msr_t msr;
 389
 390         config = config_of_soc();
 391
 392         /* Enable PM timer emulation only if ACPI PM timer is disabled */
 393         if (!config->PmTimerDisabled)
 394                 return;
 395         /*
 396          * The derived frequency is calculated as follows:
 397          *    (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
 398          * Back solve the multiplier so the 3.579545MHz ACPI timer
 399          * frequency is used.
 400          */
 401         msr.hi = (3579545ULL << 32) / CTC_FREQ;
 402         /* Set PM1 timer IO port and enable*/
 403         msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
 404                         EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
 405         wrmsr(MSR_EMULATE_PM_TIMER, msr);
 406 }
 407
 408 /* All CPUs including BSP will run the following function. */
 409 void soc_core_init(struct device *cpu)
 410 {
 411         /* Clear out pending MCEs */
 412         /* TODO(adurbin): This should only be done on a cold boot. Also, some
 413          * of these banks are core vs package scope. For now every CPU clears
 414          * every bank. */
 415         mca_configure();
 416
 417         /* Enable the local CPU apics */
 418         enable_lapic_tpr();
 419         setup_lapic();
 420
 421         /* Configure c-state interrupt response time */
 422         configure_c_states();
 423
 424         /* Configure Enhanced SpeedStep and Thermal Sensors */
 425         configure_misc();
 426
 427         /* Configure Intel Speed Shift */
 428         configure_isst();
 429
 430         /* Enable ACPI Timer Emulation via MSR 0x121 */
 431         enable_pm_timer_emulation();
 432
 433         /* Enable Direct Cache Access */
 434         configure_dca_cap();
 435
 436         /* Set energy policy */
 437         set_energy_perf_bias(ENERGY_POLICY_NORMAL);
 438
 439         /* Enable Turbo */
 440         enable_turbo();
 441
 442         /* Enable Vmx */
 443         set_vmx_and_lock();
 444 }
 445
 446 static void per_cpu_smm_trigger(void)
 447 {
 448         /* Relocate the SMM handler. */
 449         smm_relocate();
 450 }
 451
 452 static void post_mp_init(void)
 453 {
 454         /* Set Max Ratio */
 455         cpu_set_max_ratio();
 456
 457         /*
 458          * Now that all APs have been relocated as well as the BSP let SMIs
 459          * start flowing.
 460          */
 461         smm_southbridge_enable(GBL_EN);
 462
 463         /* Lock down the SMRAM space. */
 464         smm_lock();
 465 }
 466
 467 static const struct mp_ops mp_ops = {
 468         /*
 469          * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
 470          * that are set prior to ramstage.
 471          * Real MTRRs programming are being done after resource allocation.
 472          */
 473         .pre_mp_init = soc_fsp_load,
 474         .get_cpu_count = get_cpu_count,
 475         .get_smm_info = smm_info,
 476         .get_microcode_info = get_microcode_info,
 477         .pre_mp_smm_init = smm_initialize,
 478         .per_cpu_smm_trigger = per_cpu_smm_trigger,
 479         .relocation_handler = smm_relocation_handler,
 480         .post_mp_init = post_mp_init,
 481 };
 482
 483 void soc_init_cpus(struct bus *cpu_bus)
 484 {
 485         if (mp_init_with_smm(cpu_bus, &mp_ops))
 486                 printk(BIOS_ERR, "MP initialization failure.\n");
 487
 488         /* Thermal throttle activation offset */
 489         configure_thermal_target();
 490 }
 491
 492 int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
 493 {
 494         msr_t msr1;
 495         msr_t msr2;
 496
 497         /*
 498          * CFL and WHL CPU die are based on KBL CPU so we need to
 499          * have this check, where CNL CPU die is not based on KBL CPU
 500          * so skip this check for CNL.
 501          */
 502         if (!CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS))
 503                 return 0;
 504
 505         /*
 506          * If PRMRR/SGX is supported the FIT microcode load will set the msr
 507          * 0x08b with the Patch revision id one less than the id in the
 508          * microcode binary. The PRMRR support is indicated in the MSR
 509          * MTRRCAP[12]. If SGX is not enabled, check and avoid reloading the
 510          * same microcode during CPU initialization. If SGX is enabled, as
 511          * part of SGX BIOS initialization steps, the same microcode needs to
 512          * be reloaded after the core PRMRR MSRs are programmed.
 513          */
 514         msr1 = rdmsr(MTRR_CAP_MSR);
 515         msr2 = rdmsr(MSR_PRMRR_PHYS_BASE);
 516         if (msr2.lo && (current_patch_id == new_patch_id - 1))
 517                 return 0;
 518
 519         return (msr1.lo & PRMRR_SUPPORTED) &&
 520                 (current_patch_id == new_patch_id - 1);
 521 }